drivers/net/atl1c/atl1c.h

   1 /*
   2  * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
   3  *
   4  * Derived from Intel e1000 driver
   5  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the Free
   9  * Software Foundation; either version 2 of the License, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 59
  19  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  */
  21
  22 #ifndef _ATL1C_H_
  23 #define _ATL1C_H_
  24
  25 #include <linux/version.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ioport.h>
  35 #include <linux/slab.h>
  36 #include <linux/list.h>
  37 #include <linux/delay.h>
  38 #include <linux/sched.h>
  39 #include <linux/in.h>
  40 #include <linux/ip.h>
  41 #include <linux/ipv6.h>
  42 #include <linux/udp.h>
  43 #include <linux/mii.h>
  44 #include <linux/io.h>
  45 #include <linux/vmalloc.h>
  46 #include <linux/pagemap.h>
  47 #include <linux/tcp.h>
  48 #include <linux/ethtool.h>
  49 #include <linux/if_vlan.h>
  50 #include <linux/workqueue.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53
  54 #include "atl1c_hw.h"
  55
  56 /* Wake Up Filter Control */
  57 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  58 #define AT_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  59 #define AT_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  60 #define AT_WUFC_MC   0x00000008 /* Multicast Wakeup Enable */
  61 #define AT_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  62
  63 #define AT_VLAN_TO_TAG(_vlan, _tag)        \
  64         _tag =  ((((_vlan) >> 8) & 0xFF)  |\
  65                  (((_vlan) & 0xFF) << 8))
  66
  67 #define AT_TAG_TO_VLAN(_tag, _vlan)      \
  68         _vlan = ((((_tag) >> 8) & 0xFF) |\
  69                 (((_tag) & 0xFF) << 8))
  70
  71 #define SPEED_0            0xffff
  72 #define HALF_DUPLEX        1
  73 #define FULL_DUPLEX        2
  74
  75 #define AT_RX_BUF_SIZE          (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
  76 #define MAX_JUMBO_FRAME_SIZE    (9*1024)
  77 #define MAX_TX_OFFLOAD_THRESH   (9*1024)
  78
  79 #define AT_MAX_RECEIVE_QUEUE    4
  80 #define AT_DEF_RECEIVE_QUEUE    1
  81 #define AT_MAX_TRANSMIT_QUEUE   2
  82
  83 #define AT_DMA_HI_ADDR_MASK     0xffffffff00000000ULL
  84 #define AT_DMA_LO_ADDR_MASK     0x00000000ffffffffULL
  85
  86 #define AT_TX_WATCHDOG  (5 * HZ)
  87 #define AT_MAX_INT_WORK         5
  88 #define AT_TWSI_EEPROM_TIMEOUT  100
  89 #define AT_HW_MAX_IDLE_DELAY    10
  90 #define AT_SUSPEND_LINK_TIMEOUT 28
  91
  92 #define AT_ASPM_L0S_TIMER       6
  93 #define AT_ASPM_L1_TIMER        12
  94
  95 #define ATL1C_PCIE_L0S_L1_DISABLE       0x01
  96 #define ATL1C_PCIE_PHY_RESET            0x02
  97
  98 #define ATL1C_ASPM_L0s_ENABLE           0x0001
  99 #define ATL1C_ASPM_L1_ENABLE            0x0002
 100
 101 #define AT_REGS_LEN     (75 * sizeof(u32))
 102 #define AT_EEPROM_LEN   512
 103
 104 #define ATL1C_GET_DESC(R, i, type)      (&(((type *)((R)->desc))[i]))
 105 #define ATL1C_RFD_DESC(R, i)    ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
 106 #define ATL1C_TPD_DESC(R, i)    ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
 107 #define ATL1C_RRD_DESC(R, i)    ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
 108
 109 /* tpd word 1 bit 0:7 General Checksum task offload */
 110 #define TPD_L4HDR_OFFSET_MASK   0x00FF
 111 #define TPD_L4HDR_OFFSET_SHIFT  0
 112
 113 /* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
 114 #define TPD_TCPHDR_OFFSET_MASK  0x00FF
 115 #define TPD_TCPHDR_OFFSET_SHIFT 0
 116
 117 /* tpd word 1 bit 0:7 Custom Checksum task offload */
 118 #define TPD_PLOADOFFSET_MASK    0x00FF
 119 #define TPD_PLOADOFFSET_SHIFT   0
 120
 121 /* tpd word 1 bit 8:17 */
 122 #define TPD_CCSUM_EN_MASK       0x0001
 123 #define TPD_CCSUM_EN_SHIFT      8
 124 #define TPD_IP_CSUM_MASK        0x0001
 125 #define TPD_IP_CSUM_SHIFT       9
 126 #define TPD_TCP_CSUM_MASK       0x0001
 127 #define TPD_TCP_CSUM_SHIFT      10
 128 #define TPD_UDP_CSUM_MASK       0x0001
 129 #define TPD_UDP_CSUM_SHIFT      11
 130 #define TPD_LSO_EN_MASK         0x0001  /* TCP Large Send Offload */
 131 #define TPD_LSO_EN_SHIFT        12
 132 #define TPD_LSO_VER_MASK        0x0001
 133 #define TPD_LSO_VER_SHIFT       13      /* 0 : ipv4; 1 : ipv4/ipv6 */
 134 #define TPD_CON_VTAG_MASK       0x0001
 135 #define TPD_CON_VTAG_SHIFT      14
 136 #define TPD_INS_VTAG_MASK       0x0001
 137 #define TPD_INS_VTAG_SHIFT      15
 138 #define TPD_IPV4_PACKET_MASK    0x0001  /* valid when LSO VER  is 1 */
 139 #define TPD_IPV4_PACKET_SHIFT   16
 140 #define TPD_ETH_TYPE_MASK       0x0001
 141 #define TPD_ETH_TYPE_SHIFT      17      /* 0 : 802.3 frame; 1 : Ethernet */
 142
 143 /* tpd word 18:25 Custom Checksum task offload */
 144 #define TPD_CCSUM_OFFSET_MASK   0x00FF
 145 #define TPD_CCSUM_OFFSET_SHIFT  18
 146 #define TPD_CCSUM_EPAD_MASK     0x0001
 147 #define TPD_CCSUM_EPAD_SHIFT    30
 148
 149 /* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
 150 #define TPD_MSS_MASK            0x1FFF
 151 #define TPD_MSS_SHIFT           18
 152
 153 #define TPD_EOP_MASK            0x0001
 154 #define TPD_EOP_SHIFT           31
 155
 156 struct atl1c_tpd_desc {
 157         __le16  buffer_len; /* include 4-byte CRC */
 158         __le16  vlan_tag;
 159         __le32  word1;
 160         __le64  buffer_addr;
 161 };
 162
 163 struct atl1c_tpd_ext_desc {
 164         u32 reservd_0;
 165         __le32 word1;
 166         __le32 pkt_len;
 167         u32 reservd_1;
 168 };
 169 /* rrs word 0 bit 0:31 */
 170 #define RRS_RX_CSUM_MASK        0xFFFF
 171 #define RRS_RX_CSUM_SHIFT       0
 172 #define RRS_RX_RFD_CNT_MASK     0x000F
 173 #define RRS_RX_RFD_CNT_SHIFT    16
 174 #define RRS_RX_RFD_INDEX_MASK   0x0FFF
 175 #define RRS_RX_RFD_INDEX_SHIFT  20
 176
 177 /* rrs flag bit 0:16 */
 178 #define RRS_HEAD_LEN_MASK       0x00FF
 179 #define RRS_HEAD_LEN_SHIFT      0
 180 #define RRS_HDS_TYPE_MASK       0x0003
 181 #define RRS_HDS_TYPE_SHIFT      8
 182 #define RRS_CPU_NUM_MASK        0x0003
 183 #define RRS_CPU_NUM_SHIFT       10
 184 #define RRS_HASH_FLG_MASK       0x000F
 185 #define RRS_HASH_FLG_SHIFT      12
 186
 187 #define RRS_HDS_TYPE_HEAD       1
 188 #define RRS_HDS_TYPE_DATA       2
 189
 190 #define RRS_IS_NO_HDS_TYPE(flag) \
 191         ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0)
 192
 193 #define RRS_IS_HDS_HEAD(flag) \
 194         ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
 195                         RRS_HDS_TYPE_HEAD)
 196
 197 #define RRS_IS_HDS_DATA(flag) \
 198         ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
 199                         RRS_HDS_TYPE_DATA)
 200
 201 /* rrs word 3 bit 0:31 */
 202 #define RRS_PKT_SIZE_MASK       0x3FFF
 203 #define RRS_PKT_SIZE_SHIFT      0
 204 #define RRS_ERR_L4_CSUM_MASK    0x0001
 205 #define RRS_ERR_L4_CSUM_SHIFT   14
 206 #define RRS_ERR_IP_CSUM_MASK    0x0001
 207 #define RRS_ERR_IP_CSUM_SHIFT   15
 208 #define RRS_VLAN_INS_MASK       0x0001
 209 #define RRS_VLAN_INS_SHIFT      16
 210 #define RRS_PROT_ID_MASK        0x0007
 211 #define RRS_PROT_ID_SHIFT       17
 212 #define RRS_RX_ERR_SUM_MASK     0x0001
 213 #define RRS_RX_ERR_SUM_SHIFT    20
 214 #define RRS_RX_ERR_CRC_MASK     0x0001
 215 #define RRS_RX_ERR_CRC_SHIFT    21
 216 #define RRS_RX_ERR_FAE_MASK     0x0001
 217 #define RRS_RX_ERR_FAE_SHIFT    22
 218 #define RRS_RX_ERR_TRUNC_MASK   0x0001
 219 #define RRS_RX_ERR_TRUNC_SHIFT  23
 220 #define RRS_RX_ERR_RUNC_MASK    0x0001
 221 #define RRS_RX_ERR_RUNC_SHIFT   24
 222 #define RRS_RX_ERR_ICMP_MASK    0x0001
 223 #define RRS_RX_ERR_ICMP_SHIFT   25
 224 #define RRS_PACKET_BCAST_MASK   0x0001
 225 #define RRS_PACKET_BCAST_SHIFT  26
 226 #define RRS_PACKET_MCAST_MASK   0x0001
 227 #define RRS_PACKET_MCAST_SHIFT  27
 228 #define RRS_PACKET_TYPE_MASK    0x0001
 229 #define RRS_PACKET_TYPE_SHIFT   28
 230 #define RRS_FIFO_FULL_MASK      0x0001
 231 #define RRS_FIFO_FULL_SHIFT     29
 232 #define RRS_802_3_LEN_ERR_MASK  0x0001
 233 #define RRS_802_3_LEN_ERR_SHIFT 30
 234 #define RRS_RXD_UPDATED_MASK    0x0001
 235 #define RRS_RXD_UPDATED_SHIFT   31
 236
 237 #define RRS_ERR_L4_CSUM         0x00004000
 238 #define RRS_ERR_IP_CSUM         0x00008000
 239 #define RRS_VLAN_INS            0x00010000
 240 #define RRS_RX_ERR_SUM          0x00100000
 241 #define RRS_RX_ERR_CRC          0x00200000
 242 #define RRS_802_3_LEN_ERR       0x40000000
 243 #define RRS_RXD_UPDATED         0x80000000
 244
 245 #define RRS_PACKET_TYPE_802_3   1
 246 #define RRS_PACKET_TYPE_ETH     0
 247 #define RRS_PACKET_IS_ETH(word) \
 248         ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \
 249                         RRS_PACKET_TYPE_ETH)
 250 #define RRS_RXD_IS_VALID(word) \
 251         ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
 252
 253 #define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
 254         ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
 255 #define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
 256         ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
 257
 258 struct atl1c_recv_ret_status {
 259         __le32  word0;
 260         __le32  rss_hash;
 261         __le16  vlan_tag;
 262         __le16  flag;
 263         __le32  word3;
 264 };
 265
 266 /* RFD desciptor */
 267 struct atl1c_rx_free_desc {
 268         __le64  buffer_addr;
 269 };
 270
 271 /* DMA Order Settings */
 272 enum atl1c_dma_order {
 273         atl1c_dma_ord_in = 1,
 274         atl1c_dma_ord_enh = 2,
 275         atl1c_dma_ord_out = 4
 276 };
 277
 278 enum atl1c_dma_rcb {
 279         atl1c_rcb_64 = 0,
 280         atl1c_rcb_128 = 1
 281 };
 282
 283 enum atl1c_mac_speed {
 284         atl1c_mac_speed_0 = 0,
 285         atl1c_mac_speed_10_100 = 1,
 286         atl1c_mac_speed_1000 = 2
 287 };
 288
 289 enum atl1c_dma_req_block {
 290         atl1c_dma_req_128 = 0,
 291         atl1c_dma_req_256 = 1,
 292         atl1c_dma_req_512 = 2,
 293         atl1c_dma_req_1024 = 3,
 294         atl1c_dma_req_2048 = 4,
 295         atl1c_dma_req_4096 = 5
 296 };
 297
 298 enum atl1c_rss_mode {
 299         atl1c_rss_mode_disable = 0,
 300         atl1c_rss_sig_que = 1,
 301         atl1c_rss_mul_que_sig_int = 2,
 302         atl1c_rss_mul_que_mul_int = 4,
 303 };
 304
 305 enum atl1c_rss_type {
 306         atl1c_rss_disable = 0,
 307         atl1c_rss_ipv4 = 1,
 308         atl1c_rss_ipv4_tcp = 2,
 309         atl1c_rss_ipv6 = 4,
 310         atl1c_rss_ipv6_tcp = 8
 311 };
 312
 313 enum atl1c_nic_type {
 314         athr_l1c = 0,
 315         athr_l2c = 1,
 316 };
 317
 318 enum atl1c_trans_queue {
 319         atl1c_trans_normal = 0,
 320         atl1c_trans_high = 1
 321 };
 322
 323 struct atl1c_hw_stats {
 324         /* rx */
 325         unsigned long rx_ok;            /* The number of good packet received. */
 326         unsigned long rx_bcast;         /* The number of good broadcast packet received. */
 327         unsigned long rx_mcast;         /* The number of good multicast packet received. */
 328         unsigned long rx_pause;         /* The number of Pause packet received. */
 329         unsigned long rx_ctrl;          /* The number of Control packet received other than Pause frame. */
 330         unsigned long rx_fcs_err;       /* The number of packets with bad FCS. */
 331         unsigned long rx_len_err;       /* The number of packets with mismatch of length field and actual size. */
 332         unsigned long rx_byte_cnt;      /* The number of bytes of good packet received. FCS is NOT included. */
 333         unsigned long rx_runt;          /* The number of packets received that are less than 64 byte long and with good FCS. */
 334         unsigned long rx_frag;          /* The number of packets received that are less than 64 byte long and with bad FCS. */
 335         unsigned long rx_sz_64;         /* The number of good and bad packets received that are 64 byte long. */
 336         unsigned long rx_sz_65_127;     /* The number of good and bad packets received that are between 65 and 127-byte long. */
 337         unsigned long rx_sz_128_255;    /* The number of good and bad packets received that are between 128 and 255-byte long. */
 338         unsigned long rx_sz_256_511;    /* The number of good and bad packets received that are between 256 and 511-byte long. */
 339         unsigned long rx_sz_512_1023;   /* The number of good and bad packets received that are between 512 and 1023-byte long. */
 340         unsigned long rx_sz_1024_1518;  /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
 341         unsigned long rx_sz_1519_max;   /* The number of good and bad packets received that are between 1519-byte and MTU. */
 342         unsigned long rx_sz_ov;         /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
 343         unsigned long rx_rxf_ov;        /* The number of frame dropped due to occurrence of RX FIFO overflow. */
 344         unsigned long rx_rrd_ov;        /* The number of frame dropped due to occurrence of RRD overflow. */
 345         unsigned long rx_align_err;     /* Alignment Error */
 346         unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
 347         unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
 348         unsigned long rx_err_addr;      /* The number of packets dropped due to address filtering. */
 349
 350         /* tx */
 351         unsigned long tx_ok;            /* The number of good packet transmitted. */
 352         unsigned long tx_bcast;         /* The number of good broadcast packet transmitted. */
 353         unsigned long tx_mcast;         /* The number of good multicast packet transmitted. */
 354         unsigned long tx_pause;         /* The number of Pause packet transmitted. */
 355         unsigned long tx_exc_defer;     /* The number of packets transmitted with excessive deferral. */
 356         unsigned long tx_ctrl;          /* The number of packets transmitted is a control frame, excluding Pause frame. */
 357         unsigned long tx_defer;         /* The number of packets transmitted that is deferred. */
 358         unsigned long tx_byte_cnt;      /* The number of bytes of data transmitted. FCS is NOT included. */
 359         unsigned long tx_sz_64;         /* The number of good and bad packets transmitted that are 64 byte long. */
 360         unsigned long tx_sz_65_127;     /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
 361         unsigned long tx_sz_128_255;    /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
 362         unsigned long tx_sz_256_511;    /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
 363         unsigned long tx_sz_512_1023;   /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
 364         unsigned long tx_sz_1024_1518;  /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
 365         unsigned long tx_sz_1519_max;   /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
 366         unsigned long tx_1_col;         /* The number of packets subsequently transmitted successfully with a single prior collision. */
 367         unsigned long tx_2_col;         /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
 368         unsigned long tx_late_col;      /* The number of packets transmitted with late collisions. */
 369         unsigned long tx_abort_col;     /* The number of transmit packets aborted due to excessive collisions. */
 370         unsigned long tx_underrun;      /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
 371         unsigned long tx_rd_eop;        /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
 372         unsigned long tx_len_err;       /* The number of transmit packets with length field does NOT match the actual frame size. */
 373         unsigned long tx_trunc;         /* The number of transmit packets truncated due to size exceeding MTU. */
 374         unsigned long tx_bcast_byte;    /* The byte count of broadcast packet transmitted, excluding FCS. */
 375         unsigned long tx_mcast_byte;    /* The byte count of multicast packet transmitted, excluding FCS. */
 376 };
 377
 378 struct atl1c_hw {
 379         u8 __iomem      *hw_addr;            /* inner register address */
 380         struct atl1c_adapter *adapter;
 381         enum atl1c_nic_type  nic_type;
 382         enum atl1c_dma_order dma_order;
 383         enum atl1c_dma_rcb   rcb_value;
 384         enum atl1c_dma_req_block dmar_block;
 385         enum atl1c_dma_req_block dmaw_block;
 386
 387         u16 device_id;
 388         u16 vendor_id;
 389         u16 subsystem_id;
 390         u16 subsystem_vendor_id;
 391         u8 revision_id;
 392
 393         u32 intr_mask;
 394         u8 dmaw_dly_cnt;
 395         u8 dmar_dly_cnt;
 396
 397         u8 preamble_len;
 398         u16 max_frame_size;
 399         u16 min_frame_size;
 400
 401         enum atl1c_mac_speed mac_speed;
 402         bool mac_duplex;
 403         bool hibernate;
 404         u16 media_type;
 405 #define MEDIA_TYPE_AUTO_SENSOR  0
 406 #define MEDIA_TYPE_100M_FULL    1
 407 #define MEDIA_TYPE_100M_HALF    2
 408 #define MEDIA_TYPE_10M_FULL     3
 409 #define MEDIA_TYPE_10M_HALF     4
 410
 411         u16 autoneg_advertised;
 412         u16 mii_autoneg_adv_reg;
 413         u16 mii_1000t_ctrl_reg;
 414
 415         u16 tx_imt;     /* TX Interrupt Moderator timer ( 2us resolution) */
 416         u16 rx_imt;     /* RX Interrupt Moderator timer ( 2us resolution) */
 417         u16 ict;        /* Interrupt Clear timer (2us resolution) */
 418         u16 ctrl_flags;
 419 #define ATL1C_INTR_CLEAR_ON_READ        0x0001
 420 #define ATL1C_INTR_MODRT_ENABLE         0x0002
 421 #define ATL1C_CMB_ENABLE                0x0004
 422 #define ATL1C_SMB_ENABLE                0x0010
 423 #define ATL1C_TXQ_MODE_ENHANCE          0x0020
 424 #define ATL1C_RX_IPV6_CHKSUM            0x0040
 425 #define ATL1C_ASPM_L0S_SUPPORT          0x0080
 426 #define ATL1C_ASPM_L1_SUPPORT           0x0100
 427 #define ATL1C_ASPM_CTRL_MON             0x0200
 428 #define ATL1C_HIB_DISABLE               0x0400
 429 #define ATL1C_LINK_CAP_1000M            0x0800
 430 #define ATL1C_FPGA_VERSION              0x8000
 431         u16 cmb_tpd;
 432         u16 cmb_rrd;
 433         u16 cmb_rx_timer; /* 2us resolution */
 434         u16 cmb_tx_timer;
 435         u32 smb_timer;
 436
 437         u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
 438                           interrupt request */
 439         u16 tpd_thresh;
 440         u8 tpd_burst;   /* Number of TPD to prefetch in cache-aligned burst. */
 441         u8 rfd_burst;
 442         enum atl1c_rss_type rss_type;
 443         enum atl1c_rss_mode rss_mode;
 444         u8 rss_hash_bits;
 445         u32 base_cpu;
 446         u32 indirect_tab;
 447         u8 mac_addr[ETH_ALEN];
 448         u8 perm_mac_addr[ETH_ALEN];
 449
 450         bool phy_configured;
 451         bool re_autoneg;
 452         bool emi_ca;
 453 };
 454
 455 /*
 456  * atl1c_ring_header represents a single, contiguous block of DMA space
 457  * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
 458  * message blocks (cmb, smb) described below
 459  */
 460 struct atl1c_ring_header {
 461         void *desc;             /* virtual address */
 462         dma_addr_t dma;         /* physical address*/
 463         unsigned int size;      /* length in bytes */
 464 };
 465
 466 /*
 467  * atl1c_buffer is wrapper around a pointer to a socket buffer
 468  * so a DMA handle can be stored along with the skb
 469  */
 470 struct atl1c_buffer {
 471         struct sk_buff *skb;    /* socket buffer */
 472         u16 length;             /* rx buffer length */
 473         u16 flags;              /* information of buffer */
 474 #define ATL1C_BUFFER_FREE               0x0001
 475 #define ATL1C_BUFFER_BUSY               0x0002
 476 #define ATL1C_BUFFER_STATE_MASK         0x0003
 477
 478 #define ATL1C_PCIMAP_SINGLE             0x0004
 479 #define ATL1C_PCIMAP_PAGE               0x0008
 480 #define ATL1C_PCIMAP_TYPE_MASK          0x000C
 481
 482 #define ATL1C_PCIMAP_TODEVICE           0x0010
 483 #define ATL1C_PCIMAP_FROMDEVICE         0x0020
 484 #define ATL1C_PCIMAP_DIRECTION_MASK     0x0030
 485         dma_addr_t dma;
 486 };
 487
 488 #define ATL1C_SET_BUFFER_STATE(buff, state) do {        \
 489         ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK;    \
 490         ((buff)->flags) |= (state);                     \
 491         } while (0)
 492
 493 #define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do {       \
 494         ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK;             \
 495         ((buff)->flags) |= (type);                              \
 496         ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK;        \
 497         ((buff)->flags) |= (direction);                         \
 498         } while (0)
 499
 500 /* transimit packet descriptor (tpd) ring */
 501 struct atl1c_tpd_ring {
 502         void *desc;             /* descriptor ring virtual address */
 503         dma_addr_t dma;         /* descriptor ring physical address */
 504         u16 size;               /* descriptor ring length in bytes */
 505         u16 count;              /* number of descriptors in the ring */
 506         u16 next_to_use;        /* this is protectd by adapter->tx_lock */
 507         atomic_t next_to_clean;
 508         struct atl1c_buffer *buffer_info;
 509 };
 510
 511 /* receive free descriptor (rfd) ring */
 512 struct atl1c_rfd_ring {
 513         void *desc;             /* descriptor ring virtual address */
 514         dma_addr_t dma;         /* descriptor ring physical address */
 515         u16 size;               /* descriptor ring length in bytes */
 516         u16 count;              /* number of descriptors in the ring */
 517         u16 next_to_use;
 518         u16 next_to_clean;
 519         struct atl1c_buffer *buffer_info;
 520 };
 521
 522 /* receive return desciptor (rrd) ring */
 523 struct atl1c_rrd_ring {
 524         void *desc;             /* descriptor ring virtual address */
 525         dma_addr_t dma;         /* descriptor ring physical address */
 526         u16 size;               /* descriptor ring length in bytes */
 527         u16 count;              /* number of descriptors in the ring */
 528         u16 next_to_use;
 529         u16 next_to_clean;
 530 };
 531
 532 struct atl1c_cmb {
 533         void *cmb;
 534         dma_addr_t dma;
 535 };
 536
 537 struct atl1c_smb {
 538         void *smb;
 539         dma_addr_t dma;
 540 };
 541
 542 /* board specific private data structure */
 543 struct atl1c_adapter {
 544         struct net_device   *netdev;
 545         struct pci_dev      *pdev;
 546         struct vlan_group   *vlgrp;
 547         struct napi_struct  napi;
 548         struct atl1c_hw        hw;
 549         struct atl1c_hw_stats  hw_stats;
 550         struct net_device_stats net_stats;
 551         struct mii_if_info  mii;    /* MII interface info */
 552         u16 rx_buffer_len;
 553
 554         unsigned long flags;
 555 #define __AT_TESTING        0x0001
 556 #define __AT_RESETTING      0x0002
 557 #define __AT_DOWN           0x0003
 558         u8 work_event;
 559 #define ATL1C_WORK_EVENT_RESET          0x01
 560 #define ATL1C_WORK_EVENT_LINK_CHANGE    0x02
 561         u32 msg_enable;
 562
 563         bool have_msi;
 564         u32 wol;
 565         u16 link_speed;
 566         u16 link_duplex;
 567
 568         spinlock_t mdio_lock;
 569         spinlock_t tx_lock;
 570         atomic_t irq_sem;
 571
 572         struct work_struct common_task;
 573         struct timer_list watchdog_timer;
 574         struct timer_list phy_config_timer;
 575
 576         /* All Descriptor memory */
 577         struct atl1c_ring_header ring_header;
 578         struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
 579         struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
 580         struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
 581         struct atl1c_cmb cmb;
 582         struct atl1c_smb smb;
 583         int num_rx_queues;
 584         u32 bd_number;     /* board number;*/
 585 };
 586
 587 #define AT_WRITE_REG(a, reg, value) ( \
 588                 writel((value), ((a)->hw_addr + reg)))
 589
 590 #define AT_WRITE_FLUSH(a) (\
 591                 readl((a)->hw_addr))
 592
 593 #define AT_READ_REG(a, reg, pdata) do {                                 \
 594                 if (unlikely((a)->hibernate)) {                         \
 595                         readl((a)->hw_addr + reg);                      \
 596                         *(u32 *)pdata = readl((a)->hw_addr + reg);      \
 597                 } else {                                                \
 598                         *(u32 *)pdata = readl((a)->hw_addr + reg);      \
 599                 }                                                       \
 600         } while (0)
 601
 602 #define AT_WRITE_REGB(a, reg, value) (\
 603                 writeb((value), ((a)->hw_addr + reg)))
 604
 605 #define AT_READ_REGB(a, reg) (\
 606                 readb((a)->hw_addr + reg))
 607
 608 #define AT_WRITE_REGW(a, reg, value) (\
 609                 writew((value), ((a)->hw_addr + reg)))
 610
 611 #define AT_READ_REGW(a, reg) (\
 612                 readw((a)->hw_addr + reg))
 613
 614 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
 615                 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
 616
 617 #define AT_READ_REG_ARRAY(a, reg, offset) ( \
 618                 readl(((a)->hw_addr + reg) + ((offset) << 2)))
 619
 620 extern char atl1c_driver_name[];
 621 extern char atl1c_driver_version[];
 622
 623 extern int atl1c_up(struct atl1c_adapter *adapter);
 624 extern void atl1c_down(struct atl1c_adapter *adapter);
 625 extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
 626 extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
 627 extern void atl1c_set_ethtool_ops(struct net_device *netdev);
 628 #endif /* _ATL1C_H_ */