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Linux 2.6.33-rc8
[linux-2.6/lguest.git] / drivers / serial / sh-sci.c
blob42f3333c4ad09c9ccaf38973b3722dbb68b5e2e6
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #endif
55
56 #ifdef CONFIG_H8300
57 #include <asm/gpio.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 struct sci_port {
63 struct uart_port port;
64
65 /* Port type */
66 unsigned int type;
67
68 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
69 unsigned int irqs[SCIx_NR_IRQS];
70
71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
80
81 /* Interface clock */
82 struct clk *iclk;
83 /* Data clock */
84 struct clk *dclk;
85
86 struct list_head node;
87 };
88
89 struct sh_sci_priv {
90 spinlock_t lock;
91 struct list_head ports;
92 struct notifier_block clk_nb;
93 };
94
95 /* Function prototypes */
96 static void sci_stop_tx(struct uart_port *port);
97
98 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
99
100 static struct sci_port sci_ports[SCI_NPORTS];
101 static struct uart_driver sci_uart_driver;
102
103 static inline struct sci_port *
104 to_sci_port(struct uart_port *uart)
105 {
106 return container_of(uart, struct sci_port, port);
107 }
108
109 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
110
111 #ifdef CONFIG_CONSOLE_POLL
112 static inline void handle_error(struct uart_port *port)
113 {
114 /* Clear error flags */
115 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
116 }
117
118 static int sci_poll_get_char(struct uart_port *port)
119 {
120 unsigned short status;
121 int c;
122
123 do {
124 status = sci_in(port, SCxSR);
125 if (status & SCxSR_ERRORS(port)) {
126 handle_error(port);
127 continue;
128 }
129 } while (!(status & SCxSR_RDxF(port)));
130
131 c = sci_in(port, SCxRDR);
132
133 /* Dummy read */
134 sci_in(port, SCxSR);
135 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
136
137 return c;
138 }
139 #endif
140
141 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
142 {
143 unsigned short status;
144
145 do {
146 status = sci_in(port, SCxSR);
147 } while (!(status & SCxSR_TDxE(port)));
148
149 sci_out(port, SCxTDR, c);
150 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
151 }
152 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
153
154 #if defined(__H8300H__) || defined(__H8300S__)
155 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
156 {
157 int ch = (port->mapbase - SMR0) >> 3;
158
159 /* set DDR regs */
160 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
161 h8300_sci_pins[ch].rx,
162 H8300_GPIO_INPUT);
163 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
164 h8300_sci_pins[ch].tx,
165 H8300_GPIO_OUTPUT);
166
167 /* tx mark output*/
168 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
169 }
170 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
171 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
172 {
173 if (port->mapbase == 0xA4400000) {
174 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
175 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
176 } else if (port->mapbase == 0xA4410000)
177 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
178 }
179 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
180 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
181 {
182 unsigned short data;
183
184 if (cflag & CRTSCTS) {
185 /* enable RTS/CTS */
186 if (port->mapbase == 0xa4430000) { /* SCIF0 */
187 /* Clear PTCR bit 9-2; enable all scif pins but sck */
188 data = __raw_readw(PORT_PTCR);
189 __raw_writew((data & 0xfc03), PORT_PTCR);
190 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
191 /* Clear PVCR bit 9-2 */
192 data = __raw_readw(PORT_PVCR);
193 __raw_writew((data & 0xfc03), PORT_PVCR);
194 }
195 } else {
196 if (port->mapbase == 0xa4430000) { /* SCIF0 */
197 /* Clear PTCR bit 5-2; enable only tx and rx */
198 data = __raw_readw(PORT_PTCR);
199 __raw_writew((data & 0xffc3), PORT_PTCR);
200 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
201 /* Clear PVCR bit 5-2 */
202 data = __raw_readw(PORT_PVCR);
203 __raw_writew((data & 0xffc3), PORT_PVCR);
204 }
205 }
206 }
207 #elif defined(CONFIG_CPU_SH3)
208 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
209 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
210 {
211 unsigned short data;
212
213 /* We need to set SCPCR to enable RTS/CTS */
214 data = __raw_readw(SCPCR);
215 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
216 __raw_writew(data & 0x0fcf, SCPCR);
217
218 if (!(cflag & CRTSCTS)) {
219 /* We need to set SCPCR to enable RTS/CTS */
220 data = __raw_readw(SCPCR);
221 /* Clear out SCP7MD1,0, SCP4MD1,0,
222 Set SCP6MD1,0 = {01} (output) */
223 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
224
225 data = __raw_readb(SCPDR);
226 /* Set /RTS2 (bit6) = 0 */
227 __raw_writeb(data & 0xbf, SCPDR);
228 }
229 }
230 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
231 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
232 {
233 unsigned short data;
234
235 if (port->mapbase == 0xffe00000) {
236 data = __raw_readw(PSCR);
237 data &= ~0x03cf;
238 if (!(cflag & CRTSCTS))
239 data |= 0x0340;
240
241 __raw_writew(data, PSCR);
242 }
243 }
244 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
245 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
246 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
247 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
248 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
249 defined(CONFIG_CPU_SUBTYPE_SHX3)
250 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
251 {
252 if (!(cflag & CRTSCTS))
253 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
254 }
255 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
256 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
257 {
258 if (!(cflag & CRTSCTS))
259 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
260 }
261 #else
262 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
263 {
264 /* Nothing to do */
265 }
266 #endif
267
268 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
269 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
270 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7786)
272 static inline int scif_txroom(struct uart_port *port)
273 {
274 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
275 }
276
277 static inline int scif_rxroom(struct uart_port *port)
278 {
279 return sci_in(port, SCRFDR) & 0xff;
280 }
281 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
282 static inline int scif_txroom(struct uart_port *port)
283 {
284 if ((port->mapbase == 0xffe00000) ||
285 (port->mapbase == 0xffe08000)) {
286 /* SCIF0/1*/
287 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
288 } else {
289 /* SCIF2 */
290 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
291 }
292 }
293
294 static inline int scif_rxroom(struct uart_port *port)
295 {
296 if ((port->mapbase == 0xffe00000) ||
297 (port->mapbase == 0xffe08000)) {
298 /* SCIF0/1*/
299 return sci_in(port, SCRFDR) & 0xff;
300 } else {
301 /* SCIF2 */
302 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
303 }
304 }
305 #else
306 static inline int scif_txroom(struct uart_port *port)
307 {
308 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
309 }
310
311 static inline int scif_rxroom(struct uart_port *port)
312 {
313 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
314 }
315 #endif
316
317 static inline int sci_txroom(struct uart_port *port)
318 {
319 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
320 }
321
322 static inline int sci_rxroom(struct uart_port *port)
323 {
324 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
325 }
326
327 /* ********************************************************************** *
328 * the interrupt related routines *
329 * ********************************************************************** */
330
331 static void sci_transmit_chars(struct uart_port *port)
332 {
333 struct circ_buf *xmit = &port->state->xmit;
334 unsigned int stopped = uart_tx_stopped(port);
335 unsigned short status;
336 unsigned short ctrl;
337 int count;
338
339 status = sci_in(port, SCxSR);
340 if (!(status & SCxSR_TDxE(port))) {
341 ctrl = sci_in(port, SCSCR);
342 if (uart_circ_empty(xmit))
343 ctrl &= ~SCI_CTRL_FLAGS_TIE;
344 else
345 ctrl |= SCI_CTRL_FLAGS_TIE;
346 sci_out(port, SCSCR, ctrl);
347 return;
348 }
349
350 if (port->type == PORT_SCI)
351 count = sci_txroom(port);
352 else
353 count = scif_txroom(port);
354
355 do {
356 unsigned char c;
357
358 if (port->x_char) {
359 c = port->x_char;
360 port->x_char = 0;
361 } else if (!uart_circ_empty(xmit) && !stopped) {
362 c = xmit->buf[xmit->tail];
363 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
364 } else {
365 break;
366 }
367
368 sci_out(port, SCxTDR, c);
369
370 port->icount.tx++;
371 } while (--count > 0);
372
373 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
374
375 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
376 uart_write_wakeup(port);
377 if (uart_circ_empty(xmit)) {
378 sci_stop_tx(port);
379 } else {
380 ctrl = sci_in(port, SCSCR);
381
382 if (port->type != PORT_SCI) {
383 sci_in(port, SCxSR); /* Dummy read */
384 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
385 }
386
387 ctrl |= SCI_CTRL_FLAGS_TIE;
388 sci_out(port, SCSCR, ctrl);
389 }
390 }
391
392 /* On SH3, SCIF may read end-of-break as a space->mark char */
393 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
394
395 static inline void sci_receive_chars(struct uart_port *port)
396 {
397 struct sci_port *sci_port = to_sci_port(port);
398 struct tty_struct *tty = port->state->port.tty;
399 int i, count, copied = 0;
400 unsigned short status;
401 unsigned char flag;
402
403 status = sci_in(port, SCxSR);
404 if (!(status & SCxSR_RDxF(port)))
405 return;
406
407 while (1) {
408 if (port->type == PORT_SCI)
409 count = sci_rxroom(port);
410 else
411 count = scif_rxroom(port);
412
413 /* Don't copy more bytes than there is room for in the buffer */
414 count = tty_buffer_request_room(tty, count);
415
416 /* If for any reason we can't copy more data, we're done! */
417 if (count == 0)
418 break;
419
420 if (port->type == PORT_SCI) {
421 char c = sci_in(port, SCxRDR);
422 if (uart_handle_sysrq_char(port, c) ||
423 sci_port->break_flag)
424 count = 0;
425 else
426 tty_insert_flip_char(tty, c, TTY_NORMAL);
427 } else {
428 for (i = 0; i < count; i++) {
429 char c = sci_in(port, SCxRDR);
430 status = sci_in(port, SCxSR);
431 #if defined(CONFIG_CPU_SH3)
432 /* Skip "chars" during break */
433 if (sci_port->break_flag) {
434 if ((c == 0) &&
435 (status & SCxSR_FER(port))) {
436 count--; i--;
437 continue;
438 }
439
440 /* Nonzero => end-of-break */
441 dev_dbg(port->dev, "debounce<%02x>\n", c);
442 sci_port->break_flag = 0;
443
444 if (STEPFN(c)) {
445 count--; i--;
446 continue;
447 }
448 }
449 #endif /* CONFIG_CPU_SH3 */
450 if (uart_handle_sysrq_char(port, c)) {
451 count--; i--;
452 continue;
453 }
454
455 /* Store data and status */
456 if (status&SCxSR_FER(port)) {
457 flag = TTY_FRAME;
458 dev_notice(port->dev, "frame error\n");
459 } else if (status&SCxSR_PER(port)) {
460 flag = TTY_PARITY;
461 dev_notice(port->dev, "parity error\n");
462 } else
463 flag = TTY_NORMAL;
464
465 tty_insert_flip_char(tty, c, flag);
466 }
467 }
468
469 sci_in(port, SCxSR); /* dummy read */
470 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
471
472 copied += count;
473 port->icount.rx += count;
474 }
475
476 if (copied) {
477 /* Tell the rest of the system the news. New characters! */
478 tty_flip_buffer_push(tty);
479 } else {
480 sci_in(port, SCxSR); /* dummy read */
481 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
482 }
483 }
484
485 #define SCI_BREAK_JIFFIES (HZ/20)
486 /* The sci generates interrupts during the break,
487 * 1 per millisecond or so during the break period, for 9600 baud.
488 * So dont bother disabling interrupts.
489 * But dont want more than 1 break event.
490 * Use a kernel timer to periodically poll the rx line until
491 * the break is finished.
492 */
493 static void sci_schedule_break_timer(struct sci_port *port)
494 {
495 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
496 add_timer(&port->break_timer);
497 }
498 /* Ensure that two consecutive samples find the break over. */
499 static void sci_break_timer(unsigned long data)
500 {
501 struct sci_port *port = (struct sci_port *)data;
502
503 if (sci_rxd_in(&port->port) == 0) {
504 port->break_flag = 1;
505 sci_schedule_break_timer(port);
506 } else if (port->break_flag == 1) {
507 /* break is over. */
508 port->break_flag = 2;
509 sci_schedule_break_timer(port);
510 } else
511 port->break_flag = 0;
512 }
513
514 static inline int sci_handle_errors(struct uart_port *port)
515 {
516 int copied = 0;
517 unsigned short status = sci_in(port, SCxSR);
518 struct tty_struct *tty = port->state->port.tty;
519
520 if (status & SCxSR_ORER(port)) {
521 /* overrun error */
522 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
523 copied++;
524
525 dev_notice(port->dev, "overrun error");
526 }
527
528 if (status & SCxSR_FER(port)) {
529 if (sci_rxd_in(port) == 0) {
530 /* Notify of BREAK */
531 struct sci_port *sci_port = to_sci_port(port);
532
533 if (!sci_port->break_flag) {
534 sci_port->break_flag = 1;
535 sci_schedule_break_timer(sci_port);
536
537 /* Do sysrq handling. */
538 if (uart_handle_break(port))
539 return 0;
540
541 dev_dbg(port->dev, "BREAK detected\n");
542
543 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
544 copied++;
545 }
546
547 } else {
548 /* frame error */
549 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
550 copied++;
551
552 dev_notice(port->dev, "frame error\n");
553 }
554 }
555
556 if (status & SCxSR_PER(port)) {
557 /* parity error */
558 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
559 copied++;
560
561 dev_notice(port->dev, "parity error");
562 }
563
564 if (copied)
565 tty_flip_buffer_push(tty);
566
567 return copied;
568 }
569
570 static inline int sci_handle_fifo_overrun(struct uart_port *port)
571 {
572 struct tty_struct *tty = port->state->port.tty;
573 int copied = 0;
574
575 if (port->type != PORT_SCIF)
576 return 0;
577
578 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
579 sci_out(port, SCLSR, 0);
580
581 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
582 tty_flip_buffer_push(tty);
583
584 dev_notice(port->dev, "overrun error\n");
585 copied++;
586 }
587
588 return copied;
589 }
590
591 static inline int sci_handle_breaks(struct uart_port *port)
592 {
593 int copied = 0;
594 unsigned short status = sci_in(port, SCxSR);
595 struct tty_struct *tty = port->state->port.tty;
596 struct sci_port *s = to_sci_port(port);
597
598 if (uart_handle_break(port))
599 return 0;
600
601 if (!s->break_flag && status & SCxSR_BRK(port)) {
602 #if defined(CONFIG_CPU_SH3)
603 /* Debounce break */
604 s->break_flag = 1;
605 #endif
606 /* Notify of BREAK */
607 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
608 copied++;
609
610 dev_dbg(port->dev, "BREAK detected\n");
611 }
612
613 if (copied)
614 tty_flip_buffer_push(tty);
615
616 copied += sci_handle_fifo_overrun(port);
617
618 return copied;
619 }
620
621 static irqreturn_t sci_rx_interrupt(int irq, void *port)
622 {
623 /* I think sci_receive_chars has to be called irrespective
624 * of whether the I_IXOFF is set, otherwise, how is the interrupt
625 * to be disabled?
626 */
627 sci_receive_chars(port);
628
629 return IRQ_HANDLED;
630 }
631
632 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
633 {
634 struct uart_port *port = ptr;
635 unsigned long flags;
636
637 spin_lock_irqsave(&port->lock, flags);
638 sci_transmit_chars(port);
639 spin_unlock_irqrestore(&port->lock, flags);
640
641 return IRQ_HANDLED;
642 }
643
644 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
645 {
646 struct uart_port *port = ptr;
647
648 /* Handle errors */
649 if (port->type == PORT_SCI) {
650 if (sci_handle_errors(port)) {
651 /* discard character in rx buffer */
652 sci_in(port, SCxSR);
653 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
654 }
655 } else {
656 sci_handle_fifo_overrun(port);
657 sci_rx_interrupt(irq, ptr);
658 }
659
660 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
661
662 /* Kick the transmission */
663 sci_tx_interrupt(irq, ptr);
664
665 return IRQ_HANDLED;
666 }
667
668 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
669 {
670 struct uart_port *port = ptr;
671
672 /* Handle BREAKs */
673 sci_handle_breaks(port);
674 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
675
676 return IRQ_HANDLED;
677 }
678
679 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
680 {
681 unsigned short ssr_status, scr_status, err_enabled;
682 struct uart_port *port = ptr;
683 irqreturn_t ret = IRQ_NONE;
684
685 ssr_status = sci_in(port, SCxSR);
686 scr_status = sci_in(port, SCSCR);
687 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
688
689 /* Tx Interrupt */
690 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE))
691 ret = sci_tx_interrupt(irq, ptr);
692 /* Rx Interrupt */
693 if ((ssr_status & SCxSR_RDxF(port)) && (scr_status & SCI_CTRL_FLAGS_RIE))
694 ret = sci_rx_interrupt(irq, ptr);
695 /* Error Interrupt */
696 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
697 ret = sci_er_interrupt(irq, ptr);
698 /* Break Interrupt */
699 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
700 ret = sci_br_interrupt(irq, ptr);
701
702 return ret;
703 }
704
705 /*
706 * Here we define a transistion notifier so that we can update all of our
707 * ports' baud rate when the peripheral clock changes.
708 */
709 static int sci_notifier(struct notifier_block *self,
710 unsigned long phase, void *p)
711 {
712 struct sh_sci_priv *priv = container_of(self,
713 struct sh_sci_priv, clk_nb);
714 struct sci_port *sci_port;
715 unsigned long flags;
716
717 if ((phase == CPUFREQ_POSTCHANGE) ||
718 (phase == CPUFREQ_RESUMECHANGE)) {
719 spin_lock_irqsave(&priv->lock, flags);
720 list_for_each_entry(sci_port, &priv->ports, node)
721 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
722 spin_unlock_irqrestore(&priv->lock, flags);
723 }
724
725 return NOTIFY_OK;
726 }
727
728 static void sci_clk_enable(struct uart_port *port)
729 {
730 struct sci_port *sci_port = to_sci_port(port);
731
732 clk_enable(sci_port->dclk);
733 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
734
735 if (sci_port->iclk)
736 clk_enable(sci_port->iclk);
737 }
738
739 static void sci_clk_disable(struct uart_port *port)
740 {
741 struct sci_port *sci_port = to_sci_port(port);
742
743 if (sci_port->iclk)
744 clk_disable(sci_port->iclk);
745
746 clk_disable(sci_port->dclk);
747 }
748
749 static int sci_request_irq(struct sci_port *port)
750 {
751 int i;
752 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
753 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
754 sci_br_interrupt,
755 };
756 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
757 "SCI Transmit Data Empty", "SCI Break" };
758
759 if (port->irqs[0] == port->irqs[1]) {
760 if (unlikely(!port->irqs[0]))
761 return -ENODEV;
762
763 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
764 IRQF_DISABLED, "sci", port)) {
765 dev_err(port->port.dev, "Can't allocate IRQ\n");
766 return -ENODEV;
767 }
768 } else {
769 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
770 if (unlikely(!port->irqs[i]))
771 continue;
772
773 if (request_irq(port->irqs[i], handlers[i],
774 IRQF_DISABLED, desc[i], port)) {
775 dev_err(port->port.dev, "Can't allocate IRQ\n");
776 return -ENODEV;
777 }
778 }
779 }
780
781 return 0;
782 }
783
784 static void sci_free_irq(struct sci_port *port)
785 {
786 int i;
787
788 if (port->irqs[0] == port->irqs[1])
789 free_irq(port->irqs[0], port);
790 else {
791 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
792 if (!port->irqs[i])
793 continue;
794
795 free_irq(port->irqs[i], port);
796 }
797 }
798 }
799
800 static unsigned int sci_tx_empty(struct uart_port *port)
801 {
802 unsigned short status = sci_in(port, SCxSR);
803 return status & SCxSR_TEND(port) ? TIOCSER_TEMT : 0;
804 }
805
806 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
807 {
808 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
809 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
810 /* If you have signals for DTR and DCD, please implement here. */
811 }
812
813 static unsigned int sci_get_mctrl(struct uart_port *port)
814 {
815 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
816 and CTS/RTS */
817
818 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
819 }
820
821 static void sci_start_tx(struct uart_port *port)
822 {
823 unsigned short ctrl;
824
825 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
826 ctrl = sci_in(port, SCSCR);
827 ctrl |= SCI_CTRL_FLAGS_TIE;
828 sci_out(port, SCSCR, ctrl);
829 }
830
831 static void sci_stop_tx(struct uart_port *port)
832 {
833 unsigned short ctrl;
834
835 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
836 ctrl = sci_in(port, SCSCR);
837 ctrl &= ~SCI_CTRL_FLAGS_TIE;
838 sci_out(port, SCSCR, ctrl);
839 }
840
841 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
842 {
843 unsigned short ctrl;
844
845 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
846 ctrl = sci_in(port, SCSCR);
847 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
848 sci_out(port, SCSCR, ctrl);
849 }
850
851 static void sci_stop_rx(struct uart_port *port)
852 {
853 unsigned short ctrl;
854
855 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
856 ctrl = sci_in(port, SCSCR);
857 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
858 sci_out(port, SCSCR, ctrl);
859 }
860
861 static void sci_enable_ms(struct uart_port *port)
862 {
863 /* Nothing here yet .. */
864 }
865
866 static void sci_break_ctl(struct uart_port *port, int break_state)
867 {
868 /* Nothing here yet .. */
869 }
870
871 static int sci_startup(struct uart_port *port)
872 {
873 struct sci_port *s = to_sci_port(port);
874
875 if (s->enable)
876 s->enable(port);
877
878 sci_request_irq(s);
879 sci_start_tx(port);
880 sci_start_rx(port, 1);
881
882 return 0;
883 }
884
885 static void sci_shutdown(struct uart_port *port)
886 {
887 struct sci_port *s = to_sci_port(port);
888
889 sci_stop_rx(port);
890 sci_stop_tx(port);
891 sci_free_irq(s);
892
893 if (s->disable)
894 s->disable(port);
895 }
896
897 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
898 struct ktermios *old)
899 {
900 unsigned int status, baud, smr_val, max_baud;
901 int t = -1;
902
903 /*
904 * earlyprintk comes here early on with port->uartclk set to zero.
905 * the clock framework is not up and running at this point so here
906 * we assume that 115200 is the maximum baud rate. please note that
907 * the baud rate is not programmed during earlyprintk - it is assumed
908 * that the previous boot loader has enabled required clocks and
909 * setup the baud rate generator hardware for us already.
910 */
911 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
912
913 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
914 if (likely(baud && port->uartclk))
915 t = SCBRR_VALUE(baud, port->uartclk);
916
917 do {
918 status = sci_in(port, SCxSR);
919 } while (!(status & SCxSR_TEND(port)));
920
921 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
922
923 if (port->type != PORT_SCI)
924 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
925
926 smr_val = sci_in(port, SCSMR) & 3;
927 if ((termios->c_cflag & CSIZE) == CS7)
928 smr_val |= 0x40;
929 if (termios->c_cflag & PARENB)
930 smr_val |= 0x20;
931 if (termios->c_cflag & PARODD)
932 smr_val |= 0x30;
933 if (termios->c_cflag & CSTOPB)
934 smr_val |= 0x08;
935
936 uart_update_timeout(port, termios->c_cflag, baud);
937
938 sci_out(port, SCSMR, smr_val);
939
940 if (t > 0) {
941 if (t >= 256) {
942 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
943 t >>= 2;
944 } else
945 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
946
947 sci_out(port, SCBRR, t);
948 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
949 }
950
951 sci_init_pins(port, termios->c_cflag);
952 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
953
954 sci_out(port, SCSCR, SCSCR_INIT(port));
955
956 if ((termios->c_cflag & CREAD) != 0)
957 sci_start_rx(port, 0);
958 }
959
960 static const char *sci_type(struct uart_port *port)
961 {
962 switch (port->type) {
963 case PORT_IRDA:
964 return "irda";
965 case PORT_SCI:
966 return "sci";
967 case PORT_SCIF:
968 return "scif";
969 case PORT_SCIFA:
970 return "scifa";
971 }
972
973 return NULL;
974 }
975
976 static void sci_release_port(struct uart_port *port)
977 {
978 /* Nothing here yet .. */
979 }
980
981 static int sci_request_port(struct uart_port *port)
982 {
983 /* Nothing here yet .. */
984 return 0;
985 }
986
987 static void sci_config_port(struct uart_port *port, int flags)
988 {
989 struct sci_port *s = to_sci_port(port);
990
991 port->type = s->type;
992
993 if (port->membase)
994 return;
995
996 if (port->flags & UPF_IOREMAP) {
997 port->membase = ioremap_nocache(port->mapbase, 0x40);
998
999 if (IS_ERR(port->membase))
1000 dev_err(port->dev, "can't remap port#%d\n", port->line);
1001 } else {
1002 /*
1003 * For the simple (and majority of) cases where we don't
1004 * need to do any remapping, just cast the cookie
1005 * directly.
1006 */
1007 port->membase = (void __iomem *)port->mapbase;
1008 }
1009 }
1010
1011 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1012 {
1013 struct sci_port *s = to_sci_port(port);
1014
1015 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1016 return -EINVAL;
1017 if (ser->baud_base < 2400)
1018 /* No paper tape reader for Mitch.. */
1019 return -EINVAL;
1020
1021 return 0;
1022 }
1023
1024 static struct uart_ops sci_uart_ops = {
1025 .tx_empty = sci_tx_empty,
1026 .set_mctrl = sci_set_mctrl,
1027 .get_mctrl = sci_get_mctrl,
1028 .start_tx = sci_start_tx,
1029 .stop_tx = sci_stop_tx,
1030 .stop_rx = sci_stop_rx,
1031 .enable_ms = sci_enable_ms,
1032 .break_ctl = sci_break_ctl,
1033 .startup = sci_startup,
1034 .shutdown = sci_shutdown,
1035 .set_termios = sci_set_termios,
1036 .type = sci_type,
1037 .release_port = sci_release_port,
1038 .request_port = sci_request_port,
1039 .config_port = sci_config_port,
1040 .verify_port = sci_verify_port,
1041 #ifdef CONFIG_CONSOLE_POLL
1042 .poll_get_char = sci_poll_get_char,
1043 .poll_put_char = sci_poll_put_char,
1044 #endif
1045 };
1046
1047 static void __devinit sci_init_single(struct platform_device *dev,
1048 struct sci_port *sci_port,
1049 unsigned int index,
1050 struct plat_sci_port *p)
1051 {
1052 sci_port->port.ops = &sci_uart_ops;
1053 sci_port->port.iotype = UPIO_MEM;
1054 sci_port->port.line = index;
1055
1056 switch (p->type) {
1057 case PORT_SCIFA:
1058 sci_port->port.fifosize = 64;
1059 break;
1060 case PORT_SCIF:
1061 sci_port->port.fifosize = 16;
1062 break;
1063 default:
1064 sci_port->port.fifosize = 1;
1065 break;
1066 }
1067
1068 if (dev) {
1069 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1070 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1071 sci_port->enable = sci_clk_enable;
1072 sci_port->disable = sci_clk_disable;
1073 sci_port->port.dev = &dev->dev;
1074 }
1075
1076 sci_port->break_timer.data = (unsigned long)sci_port;
1077 sci_port->break_timer.function = sci_break_timer;
1078 init_timer(&sci_port->break_timer);
1079
1080 sci_port->port.mapbase = p->mapbase;
1081 sci_port->port.membase = p->membase;
1082
1083 sci_port->port.irq = p->irqs[SCIx_TXI_IRQ];
1084 sci_port->port.flags = p->flags;
1085 sci_port->type = sci_port->port.type = p->type;
1086
1087 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1088 }
1089
1090 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1091 static struct tty_driver *serial_console_device(struct console *co, int *index)
1092 {
1093 struct uart_driver *p = &sci_uart_driver;
1094 *index = co->index;
1095 return p->tty_driver;
1096 }
1097
1098 static void serial_console_putchar(struct uart_port *port, int ch)
1099 {
1100 sci_poll_put_char(port, ch);
1101 }
1102
1103 /*
1104 * Print a string to the serial port trying not to disturb
1105 * any possible real use of the port...
1106 */
1107 static void serial_console_write(struct console *co, const char *s,
1108 unsigned count)
1109 {
1110 struct uart_port *port = co->data;
1111 struct sci_port *sci_port = to_sci_port(port);
1112 unsigned short bits;
1113
1114 if (sci_port->enable)
1115 sci_port->enable(port);
1116
1117 uart_console_write(port, s, count, serial_console_putchar);
1118
1119 /* wait until fifo is empty and last bit has been transmitted */
1120 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1121 while ((sci_in(port, SCxSR) & bits) != bits)
1122 cpu_relax();
1123
1124 if (sci_port->disable)
1125 sci_port->disable(port);
1126 }
1127
1128 static int __devinit serial_console_setup(struct console *co, char *options)
1129 {
1130 struct sci_port *sci_port;
1131 struct uart_port *port;
1132 int baud = 115200;
1133 int bits = 8;
1134 int parity = 'n';
1135 int flow = 'n';
1136 int ret;
1137
1138 /*
1139 * Check whether an invalid uart number has been specified, and
1140 * if so, search for the first available port that does have
1141 * console support.
1142 */
1143 if (co->index >= SCI_NPORTS)
1144 co->index = 0;
1145
1146 if (co->data) {
1147 port = co->data;
1148 sci_port = to_sci_port(port);
1149 } else {
1150 sci_port = &sci_ports[co->index];
1151 port = &sci_port->port;
1152 co->data = port;
1153 }
1154
1155 /*
1156 * Also need to check port->type, we don't actually have any
1157 * UPIO_PORT ports, but uart_report_port() handily misreports
1158 * it anyways if we don't have a port available by the time this is
1159 * called.
1160 */
1161 if (!port->type)
1162 return -ENODEV;
1163
1164 sci_config_port(port, 0);
1165
1166 if (sci_port->enable)
1167 sci_port->enable(port);
1168
1169 if (options)
1170 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171
1172 ret = uart_set_options(port, co, baud, parity, bits, flow);
1173 #if defined(__H8300H__) || defined(__H8300S__)
1174 /* disable rx interrupt */
1175 if (ret == 0)
1176 sci_stop_rx(port);
1177 #endif
1178 /* TODO: disable clock */
1179 return ret;
1180 }
1181
1182 static struct console serial_console = {
1183 .name = "ttySC",
1184 .device = serial_console_device,
1185 .write = serial_console_write,
1186 .setup = serial_console_setup,
1187 .flags = CON_PRINTBUFFER,
1188 .index = -1,
1189 };
1190
1191 static int __init sci_console_init(void)
1192 {
1193 register_console(&serial_console);
1194 return 0;
1195 }
1196 console_initcall(sci_console_init);
1197
1198 static struct sci_port early_serial_port;
1199 static struct console early_serial_console = {
1200 .name = "early_ttySC",
1201 .write = serial_console_write,
1202 .flags = CON_PRINTBUFFER,
1203 };
1204 static char early_serial_buf[32];
1205
1206 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1207
1208 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1209 #define SCI_CONSOLE (&serial_console)
1210 #else
1211 #define SCI_CONSOLE 0
1212 #endif
1213
1214 static char banner[] __initdata =
1215 KERN_INFO "SuperH SCI(F) driver initialized\n";
1216
1217 static struct uart_driver sci_uart_driver = {
1218 .owner = THIS_MODULE,
1219 .driver_name = "sci",
1220 .dev_name = "ttySC",
1221 .major = SCI_MAJOR,
1222 .minor = SCI_MINOR_START,
1223 .nr = SCI_NPORTS,
1224 .cons = SCI_CONSOLE,
1225 };
1226
1227
1228 static int sci_remove(struct platform_device *dev)
1229 {
1230 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1231 struct sci_port *p;
1232 unsigned long flags;
1233
1234 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1235
1236 spin_lock_irqsave(&priv->lock, flags);
1237 list_for_each_entry(p, &priv->ports, node)
1238 uart_remove_one_port(&sci_uart_driver, &p->port);
1239 spin_unlock_irqrestore(&priv->lock, flags);
1240
1241 kfree(priv);
1242 return 0;
1243 }
1244
1245 static int __devinit sci_probe_single(struct platform_device *dev,
1246 unsigned int index,
1247 struct plat_sci_port *p,
1248 struct sci_port *sciport)
1249 {
1250 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1251 unsigned long flags;
1252 int ret;
1253
1254 /* Sanity check */
1255 if (unlikely(index >= SCI_NPORTS)) {
1256 dev_notice(&dev->dev, "Attempting to register port "
1257 "%d when only %d are available.\n",
1258 index+1, SCI_NPORTS);
1259 dev_notice(&dev->dev, "Consider bumping "
1260 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1261 return 0;
1262 }
1263
1264 sci_init_single(dev, sciport, index, p);
1265
1266 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1267 if (ret)
1268 return ret;
1269
1270 INIT_LIST_HEAD(&sciport->node);
1271
1272 spin_lock_irqsave(&priv->lock, flags);
1273 list_add(&sciport->node, &priv->ports);
1274 spin_unlock_irqrestore(&priv->lock, flags);
1275
1276 return 0;
1277 }
1278
1279 /*
1280 * Register a set of serial devices attached to a platform device. The
1281 * list is terminated with a zero flags entry, which means we expect
1282 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1283 * remapping (such as sh64) should also set UPF_IOREMAP.
1284 */
1285 static int __devinit sci_probe(struct platform_device *dev)
1286 {
1287 struct plat_sci_port *p = dev->dev.platform_data;
1288 struct sh_sci_priv *priv;
1289 int i, ret = -EINVAL;
1290
1291 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1292 if (is_early_platform_device(dev)) {
1293 if (dev->id == -1)
1294 return -ENOTSUPP;
1295 early_serial_console.index = dev->id;
1296 early_serial_console.data = &early_serial_port.port;
1297 sci_init_single(NULL, &early_serial_port, dev->id, p);
1298 serial_console_setup(&early_serial_console, early_serial_buf);
1299 if (!strstr(early_serial_buf, "keep"))
1300 early_serial_console.flags |= CON_BOOT;
1301 register_console(&early_serial_console);
1302 return 0;
1303 }
1304 #endif
1305
1306 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1307 if (!priv)
1308 return -ENOMEM;
1309
1310 INIT_LIST_HEAD(&priv->ports);
1311 spin_lock_init(&priv->lock);
1312 platform_set_drvdata(dev, priv);
1313
1314 priv->clk_nb.notifier_call = sci_notifier;
1315 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1316
1317 if (dev->id != -1) {
1318 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1319 if (ret)
1320 goto err_unreg;
1321 } else {
1322 for (i = 0; p && p->flags != 0; p++, i++) {
1323 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1324 if (ret)
1325 goto err_unreg;
1326 }
1327 }
1328
1329 #ifdef CONFIG_SH_STANDARD_BIOS
1330 sh_bios_gdb_detach();
1331 #endif
1332
1333 return 0;
1334
1335 err_unreg:
1336 sci_remove(dev);
1337 return ret;
1338 }
1339
1340 static int sci_suspend(struct device *dev)
1341 {
1342 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1343 struct sci_port *p;
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&priv->lock, flags);
1347 list_for_each_entry(p, &priv->ports, node)
1348 uart_suspend_port(&sci_uart_driver, &p->port);
1349 spin_unlock_irqrestore(&priv->lock, flags);
1350
1351 return 0;
1352 }
1353
1354 static int sci_resume(struct device *dev)
1355 {
1356 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1357 struct sci_port *p;
1358 unsigned long flags;
1359
1360 spin_lock_irqsave(&priv->lock, flags);
1361 list_for_each_entry(p, &priv->ports, node)
1362 uart_resume_port(&sci_uart_driver, &p->port);
1363 spin_unlock_irqrestore(&priv->lock, flags);
1364
1365 return 0;
1366 }
1367
1368 static const struct dev_pm_ops sci_dev_pm_ops = {
1369 .suspend = sci_suspend,
1370 .resume = sci_resume,
1371 };
1372
1373 static struct platform_driver sci_driver = {
1374 .probe = sci_probe,
1375 .remove = sci_remove,
1376 .driver = {
1377 .name = "sh-sci",
1378 .owner = THIS_MODULE,
1379 .pm = &sci_dev_pm_ops,
1380 },
1381 };
1382
1383 static int __init sci_init(void)
1384 {
1385 int ret;
1386
1387 printk(banner);
1388
1389 ret = uart_register_driver(&sci_uart_driver);
1390 if (likely(ret == 0)) {
1391 ret = platform_driver_register(&sci_driver);
1392 if (unlikely(ret))
1393 uart_unregister_driver(&sci_uart_driver);
1394 }
1395
1396 return ret;
1397 }
1398
1399 static void __exit sci_exit(void)
1400 {
1401 platform_driver_unregister(&sci_driver);
1402 uart_unregister_driver(&sci_uart_driver);
1403 }
1404
1405 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1406 early_platform_init_buffer("earlyprintk", &sci_driver,
1407 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1408 #endif
1409 module_init(sci_init);
1410 module_exit(sci_exit);
1411
1412 MODULE_LICENSE("GPL");
1413 MODULE_ALIAS("platform:sh-sci");
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