arch/arm/mach-omap2/omap-smp.c

   1 /*
   2  * OMAP4 SMP source file. It contains platform specific functions
   3  * needed for the linux smp kernel.
   4  *
   5  * Copyright (C) 2009 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Platform file needed for the OMAP4 SMP. This file is based on arm
  11  * realview smp platform.
  12  * * Copyright (c) 2002 ARM Limited.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #include <asm/sections.h>
  25 #include <asm/smp_scu.h>
  26 #include <asm/virt.h>
  27
  28 #include "omap-secure.h"
  29 #include "omap-wakeupgen.h"
  30 #include <asm/cputype.h>
  31
  32 #include "soc.h"
  33 #include "iomap.h"
  34 #include "common.h"
  35 #include "clockdomain.h"
  36 #include "pm.h"
  37
  38 #define CPU_MASK                0xff0ffff0
  39 #define CPU_CORTEX_A9           0x410FC090
  40 #define CPU_CORTEX_A15          0x410FC0F0
  41
  42 #define OMAP5_CORE_COUNT        0x2
  43
  44 #define AUX_CORE_BOOT0_GP_RELEASE       0x020
  45 #define AUX_CORE_BOOT0_HS_RELEASE       0x200
  46
  47 struct omap_smp_config {
  48         unsigned long cpu1_rstctrl_pa;
  49         void __iomem *cpu1_rstctrl_va;
  50         void __iomem *scu_base;
  51         void __iomem *wakeupgen_base;
  52         void *startup_addr;
  53 };
  54
  55 static struct omap_smp_config cfg;
  56
  57 static const struct omap_smp_config omap443x_cfg __initconst = {
  58         .cpu1_rstctrl_pa = 0x4824380c,
  59         .startup_addr = omap4_secondary_startup,
  60 };
  61
  62 static const struct omap_smp_config omap446x_cfg __initconst = {
  63         .cpu1_rstctrl_pa = 0x4824380c,
  64         .startup_addr = omap4460_secondary_startup,
  65 };
  66
  67 static const struct omap_smp_config omap5_cfg __initconst = {
  68         .cpu1_rstctrl_pa = 0x48243810,
  69         .startup_addr = omap5_secondary_startup,
  70 };
  71
  72 void __iomem *omap4_get_scu_base(void)
  73 {
  74         return cfg.scu_base;
  75 }
  76
  77 #ifdef CONFIG_OMAP5_ERRATA_801819
  78 void omap5_erratum_workaround_801819(void)
  79 {
  80         u32 acr, revidr;
  81         u32 acr_mask;
  82
  83         /* REVIDR[3] indicates erratum fix available on silicon */
  84         asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
  85         if (revidr & (0x1 << 3))
  86                 return;
  87
  88         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  89         /*
  90          * BIT(27) - Disables streaming. All write-allocate lines allocate in
  91          * the L1 or L2 cache.
  92          * BIT(25) - Disables streaming. All write-allocate lines allocate in
  93          * the L1 cache.
  94          */
  95         acr_mask = (0x3 << 25) | (0x3 << 27);
  96         /* do we already have it done.. if yes, skip expensive smc */
  97         if ((acr & acr_mask) == acr_mask)
  98                 return;
  99
 100         acr |= acr_mask;
 101         omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
 102
 103         pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
 104                  __func__, smp_processor_id());
 105 }
 106 #else
 107 static inline void omap5_erratum_workaround_801819(void) { }
 108 #endif
 109
 110 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 111 /*
 112  * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
 113  * ICIALLU) to activate the workaround for secondary Core.
 114  * NOTE: it is assumed that the primary core's configuration is done
 115  * by the boot loader (kernel will detect a misconfiguration and complain
 116  * if this is not done).
 117  *
 118  * In General Purpose(GP) devices, ACR bit settings can only be done
 119  * by ROM code in "secure world" using the smc call and there is no
 120  * option to update the "firmware" on such devices. This also works for
 121  * High security(HS) devices, as a backup option in case the
 122  * "update" is not done in the "security firmware".
 123  */
 124 static void omap5_secondary_harden_predictor(void)
 125 {
 126         u32 acr, acr_mask;
 127
 128         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 129
 130         /*
 131          * ACTLR[0] (Enable invalidates of BTB with ICIALLU)
 132          */
 133         acr_mask = BIT(0);
 134
 135         /* Do we already have it done.. if yes, skip expensive smc */
 136         if ((acr & acr_mask) == acr_mask)
 137                 return;
 138
 139         acr |= acr_mask;
 140         omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
 141
 142         pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
 143                  __func__, smp_processor_id());
 144 }
 145 #else
 146 static inline void omap5_secondary_harden_predictor(void) { }
 147 #endif
 148
 149 static void omap4_secondary_init(unsigned int cpu)
 150 {
 151         /*
 152          * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
 153          * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
 154          * init and for CPU1, a secure PPA API provided. CPU0 must be ON
 155          * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
 156          * OMAP443X GP devices- SMP bit isn't accessible.
 157          * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
 158          */
 159         if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 160                 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
 161                                                         4, 0, 0, 0, 0, 0);
 162
 163         if (soc_is_omap54xx() || soc_is_dra7xx()) {
 164                 /*
 165                  * Configure the CNTFRQ register for the secondary cpu's which
 166                  * indicates the frequency of the cpu local timers.
 167                  */
 168                 set_cntfreq();
 169                 /* Configure ACR to disable streaming WA for 801819 */
 170                 omap5_erratum_workaround_801819();
 171                 /* Enable ACR to allow for ICUALLU workaround */
 172                 omap5_secondary_harden_predictor();
 173         }
 174 }
 175
 176 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 177 {
 178         static struct clockdomain *cpu1_clkdm;
 179         static bool booted;
 180         static struct powerdomain *cpu1_pwrdm;
 181
 182         /*
 183          * Update the AuxCoreBoot0 with boot state for secondary core.
 184          * omap4_secondary_startup() routine will hold the secondary core till
 185          * the AuxCoreBoot1 register is updated with cpu state
 186          * A barrier is added to ensure that write buffer is drained
 187          */
 188         if (omap_secure_apis_support())
 189                 omap_modify_auxcoreboot0(AUX_CORE_BOOT0_HS_RELEASE,
 190                                          0xfffffdff);
 191         else
 192                 writel_relaxed(AUX_CORE_BOOT0_GP_RELEASE,
 193                                cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 194
 195         if (!cpu1_clkdm && !cpu1_pwrdm) {
 196                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 197                 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
 198         }
 199
 200         /*
 201          * The SGI(Software Generated Interrupts) are not wakeup capable
 202          * from low power states. This is known limitation on OMAP4 and
 203          * needs to be worked around by using software forced clockdomain
 204          * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
 205          * software force wakeup. The clockdomain is then put back to
 206          * hardware supervised mode.
 207          * More details can be found in OMAP4430 TRM - Version J
 208          * Section :
 209          *      4.3.4.2 Power States of CPU0 and CPU1
 210          */
 211         if (booted && cpu1_pwrdm && cpu1_clkdm) {
 212                 /*
 213                  * GIC distributor control register has changed between
 214                  * CortexA9 r1pX and r2pX. The Control Register secure
 215                  * banked version is now composed of 2 bits:
 216                  * bit 0 == Secure Enable
 217                  * bit 1 == Non-Secure Enable
 218                  * The Non-Secure banked register has not changed
 219                  * Because the ROM Code is based on the r1pX GIC, the CPU1
 220                  * GIC restoration will cause a problem to CPU0 Non-Secure SW.
 221                  * The workaround must be:
 222                  * 1) Before doing the CPU1 wakeup, CPU0 must disable
 223                  * the GIC distributor
 224                  * 2) CPU1 must re-enable the GIC distributor on
 225                  * it's wakeup path.
 226                  */
 227                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 228                         local_irq_disable();
 229                         gic_dist_disable();
 230                 }
 231
 232                 /*
 233                  * Ensure that CPU power state is set to ON to avoid CPU
 234                  * powerdomain transition on wfi
 235                  */
 236                 clkdm_deny_idle_nolock(cpu1_clkdm);
 237                 pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
 238                 clkdm_allow_idle_nolock(cpu1_clkdm);
 239
 240                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 241                         while (gic_dist_disabled()) {
 242                                 udelay(1);
 243                                 cpu_relax();
 244                         }
 245                         gic_timer_retrigger();
 246                         local_irq_enable();
 247                 }
 248         } else {
 249                 dsb_sev();
 250                 booted = true;
 251         }
 252
 253         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 254
 255         return 0;
 256 }
 257
 258 /*
 259  * Initialise the CPU possible map early - this describes the CPUs
 260  * which may be present or become present in the system.
 261  */
 262 static void __init omap4_smp_init_cpus(void)
 263 {
 264         unsigned int i = 0, ncores = 1, cpu_id;
 265
 266         /* Use ARM cpuid check here, as SoC detection will not work so early */
 267         cpu_id = read_cpuid_id() & CPU_MASK;
 268         if (cpu_id == CPU_CORTEX_A9) {
 269                 /*
 270                  * Currently we can't call ioremap here because
 271                  * SoC detection won't work until after init_early.
 272                  */
 273                 cfg.scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
 274                 BUG_ON(!cfg.scu_base);
 275                 ncores = scu_get_core_count(cfg.scu_base);
 276         } else if (cpu_id == CPU_CORTEX_A15) {
 277                 ncores = OMAP5_CORE_COUNT;
 278         }
 279
 280         /* sanity check */
 281         if (ncores > nr_cpu_ids) {
 282                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 283                         ncores, nr_cpu_ids);
 284                 ncores = nr_cpu_ids;
 285         }
 286
 287         for (i = 0; i < ncores; i++)
 288                 set_cpu_possible(i, true);
 289 }
 290
 291 /*
 292  * For now, just make sure the start-up address is not within the booting
 293  * kernel space as that means we just overwrote whatever secondary_startup()
 294  * code there was.
 295  */
 296 static bool __init omap4_smp_cpu1_startup_valid(unsigned long addr)
 297 {
 298         if ((addr >= __pa(PAGE_OFFSET)) && (addr <= __pa(__bss_start)))
 299                 return false;
 300
 301         return true;
 302 }
 303
 304 /*
 305  * We may need to reset CPU1 before configuring, otherwise kexec boot can end
 306  * up trying to use old kernel startup address or suspend-resume will
 307  * occasionally fail to bring up CPU1 on 4430 if CPU1 fails to enter deeper
 308  * idle states.
 309  */
 310 static void __init omap4_smp_maybe_reset_cpu1(struct omap_smp_config *c)
 311 {
 312         unsigned long cpu1_startup_pa, cpu1_ns_pa_addr;
 313         bool needs_reset = false;
 314         u32 released;
 315
 316         if (omap_secure_apis_support())
 317                 released = omap_read_auxcoreboot0() & AUX_CORE_BOOT0_HS_RELEASE;
 318         else
 319                 released = readl_relaxed(cfg.wakeupgen_base +
 320                                          OMAP_AUX_CORE_BOOT_0) &
 321                                                 AUX_CORE_BOOT0_GP_RELEASE;
 322         if (released) {
 323                 pr_warn("smp: CPU1 not parked?\n");
 324
 325                 return;
 326         }
 327
 328         cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base +
 329                                         OMAP_AUX_CORE_BOOT_1);
 330
 331         /* Did the configured secondary_startup() get overwritten? */
 332         if (!omap4_smp_cpu1_startup_valid(cpu1_startup_pa))
 333                 needs_reset = true;
 334
 335         /*
 336          * If omap4 or 5 has NS_PA_ADDR configured, CPU1 may be in a
 337          * deeper idle state in WFI and will wake to an invalid address.
 338          */
 339         if ((soc_is_omap44xx() || soc_is_omap54xx())) {
 340                 cpu1_ns_pa_addr = omap4_get_cpu1_ns_pa_addr();
 341                 if (!omap4_smp_cpu1_startup_valid(cpu1_ns_pa_addr))
 342                         needs_reset = true;
 343         } else {
 344                 cpu1_ns_pa_addr = 0;
 345         }
 346
 347         if (!needs_reset || !c->cpu1_rstctrl_va)
 348                 return;
 349
 350         pr_info("smp: CPU1 parked within kernel, needs reset (0x%lx 0x%lx)\n",
 351                 cpu1_startup_pa, cpu1_ns_pa_addr);
 352
 353         writel_relaxed(1, c->cpu1_rstctrl_va);
 354         readl_relaxed(c->cpu1_rstctrl_va);
 355         writel_relaxed(0, c->cpu1_rstctrl_va);
 356 }
 357
 358 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 359 {
 360         const struct omap_smp_config *c = NULL;
 361
 362         if (soc_is_omap443x())
 363                 c = &omap443x_cfg;
 364         else if (soc_is_omap446x())
 365                 c = &omap446x_cfg;
 366         else if (soc_is_dra74x() || soc_is_omap54xx() || soc_is_dra76x())
 367                 c = &omap5_cfg;
 368
 369         if (!c) {
 370                 pr_err("%s Unknown SMP SoC?\n", __func__);
 371                 return;
 372         }
 373
 374         /* Must preserve cfg.scu_base set earlier */
 375         cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;
 376         cfg.startup_addr = c->startup_addr;
 377         cfg.wakeupgen_base = omap_get_wakeupgen_base();
 378
 379         if (soc_is_dra74x() || soc_is_omap54xx() || soc_is_dra76x()) {
 380                 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
 381                         cfg.startup_addr = omap5_secondary_hyp_startup;
 382                 omap5_erratum_workaround_801819();
 383         }
 384
 385         cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);
 386         if (!cfg.cpu1_rstctrl_va)
 387                 return;
 388
 389         /*
 390          * Initialise the SCU and wake up the secondary core using
 391          * wakeup_secondary().
 392          */
 393         if (cfg.scu_base)
 394                 scu_enable(cfg.scu_base);
 395
 396         omap4_smp_maybe_reset_cpu1(&cfg);
 397
 398         /*
 399          * Write the address of secondary startup routine into the
 400          * AuxCoreBoot1 where ROM code will jump and start executing
 401          * on secondary core once out of WFE
 402          * A barrier is added to ensure that write buffer is drained
 403          */
 404         if (omap_secure_apis_support())
 405                 omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));
 406         else
 407                 writel_relaxed(__pa_symbol(cfg.startup_addr),
 408                                cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
 409 }
 410
 411 const struct smp_operations omap4_smp_ops __initconst = {
 412         .smp_init_cpus          = omap4_smp_init_cpus,
 413         .smp_prepare_cpus       = omap4_smp_prepare_cpus,
 414         .smp_secondary_init     = omap4_secondary_init,
 415         .smp_boot_secondary     = omap4_boot_secondary,
 416 #ifdef CONFIG_HOTPLUG_CPU
 417         .cpu_die                = omap4_cpu_die,
 418         .cpu_kill               = omap4_cpu_kill,
 419 #endif
 420 };