| blob | 787d7850e0643d80197e29bcfbfedf6d40ab46eb |
1 config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
22 select ARCH_HAS_KCOV
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_SG_CHAIN
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
33 select ARCH_HAVE_NMI_SAFE_CMPXCHG
34 select ARCH_INLINE_READ_LOCK if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
60 select ARCH_USE_CMPXCHG_LOCKREF
61 select ARCH_USE_QUEUED_RWLOCKS
62 select ARCH_USE_QUEUED_SPINLOCKS
63 select ARCH_SUPPORTS_MEMORY_FAILURE
64 select ARCH_SUPPORTS_ATOMIC_RMW
65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
66 select ARCH_SUPPORTS_NUMA_BALANCING
67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
68 select ARCH_WANT_FRAME_POINTERS
69 select ARCH_HAS_UBSAN_SANITIZE_ALL
70 select ARM_AMBA
71 select ARM_ARCH_TIMER
72 select ARM_GIC
73 select AUDIT_ARCH_COMPAT_GENERIC
74 select ARM_GIC_V2M if PCI
75 select ARM_GIC_V3
76 select ARM_GIC_V3_ITS if PCI
77 select ARM_PSCI_FW
78 select BUILDTIME_EXTABLE_SORT
79 select CLONE_BACKWARDS
80 select COMMON_CLK
81 select CPU_PM if (SUSPEND || CPU_IDLE)
82 select CRC32
83 select DCACHE_WORD_ACCESS
84 select DMA_DIRECT_OPS
85 select EDAC_SUPPORT
86 select FRAME_POINTER
87 select GENERIC_ALLOCATOR
88 select GENERIC_ARCH_TOPOLOGY
89 select GENERIC_CLOCKEVENTS
90 select GENERIC_CLOCKEVENTS_BROADCAST
91 select GENERIC_CPU_AUTOPROBE
92 select GENERIC_EARLY_IOREMAP
93 select GENERIC_IDLE_POLL_SETUP
94 select GENERIC_IRQ_MULTI_HANDLER
95 select GENERIC_IRQ_PROBE
96 select GENERIC_IRQ_SHOW
97 select GENERIC_IRQ_SHOW_LEVEL
98 select GENERIC_PCI_IOMAP
99 select GENERIC_SCHED_CLOCK
100 select GENERIC_SMP_IDLE_THREAD
101 select GENERIC_STRNCPY_FROM_USER
102 select GENERIC_STRNLEN_USER
103 select GENERIC_TIME_VSYSCALL
104 select HANDLE_DOMAIN_IRQ
105 select HARDIRQS_SW_RESEND
106 select HAVE_ACPI_APEI if (ACPI && EFI)
107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
108 select HAVE_ARCH_AUDITSYSCALL
109 select HAVE_ARCH_BITREVERSE
110 select HAVE_ARCH_HUGE_VMAP
111 select HAVE_ARCH_JUMP_LABEL
112 select HAVE_ARCH_JUMP_LABEL_RELATIVE
113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
114 select HAVE_ARCH_KGDB
115 select HAVE_ARCH_MMAP_RND_BITS
116 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
117 select HAVE_ARCH_PREL32_RELOCATIONS
118 select HAVE_ARCH_SECCOMP_FILTER
119 select HAVE_ARCH_STACKLEAK
120 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
121 select HAVE_ARCH_TRACEHOOK
122 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
123 select HAVE_ARCH_VMAP_STACK
124 select HAVE_ARM_SMCCC
125 select HAVE_EBPF_JIT
126 select HAVE_C_RECORDMCOUNT
127 select HAVE_CMPXCHG_DOUBLE
128 select HAVE_CMPXCHG_LOCAL
129 select HAVE_CONTEXT_TRACKING
130 select HAVE_DEBUG_BUGVERBOSE
131 select HAVE_DEBUG_KMEMLEAK
132 select HAVE_DMA_CONTIGUOUS
133 select HAVE_DYNAMIC_FTRACE
134 select HAVE_EFFICIENT_UNALIGNED_ACCESS
135 select HAVE_FTRACE_MCOUNT_RECORD
136 select HAVE_FUNCTION_TRACER
137 select HAVE_FUNCTION_GRAPH_TRACER
138 select HAVE_GCC_PLUGINS
139 select HAVE_GENERIC_DMA_COHERENT
140 select HAVE_HW_BREAKPOINT if PERF_EVENTS
141 select HAVE_IRQ_TIME_ACCOUNTING
142 select HAVE_MEMBLOCK_NODE_MAP if NUMA
143 select HAVE_NMI
144 select HAVE_PATA_PLATFORM
145 select HAVE_PERF_EVENTS
146 select HAVE_PERF_REGS
147 select HAVE_PERF_USER_STACK_DUMP
148 select HAVE_REGS_AND_STACK_ACCESS_API
149 select HAVE_RCU_TABLE_FREE
150 select HAVE_RCU_TABLE_INVALIDATE
151 select HAVE_RSEQ
152 select HAVE_STACKPROTECTOR
153 select HAVE_SYSCALL_TRACEPOINTS
154 select HAVE_KPROBES
155 select HAVE_KRETPROBES
156 select IOMMU_DMA if IOMMU_SUPPORT
157 select IRQ_DOMAIN
158 select IRQ_FORCED_THREADING
159 select MODULES_USE_ELF_RELA
160 select MULTI_IRQ_HANDLER
161 select NEED_DMA_MAP_STATE
162 select NEED_SG_DMA_LENGTH
163 select OF
164 select OF_EARLY_FLATTREE
165 select OF_RESERVED_MEM
166 select PCI_ECAM if ACPI
167 select POWER_RESET
168 select POWER_SUPPLY
169 select REFCOUNT_FULL
170 select SPARSE_IRQ
171 select SWIOTLB
172 select SYSCTL_EXCEPTION_TRACE
173 select THREAD_INFO_IN_TASK
174 help
175 ARM 64-bit (AArch64) Linux support.
177 config 64BIT
178 def_bool y
180 config MMU
181 def_bool y
183 config ARM64_PAGE_SHIFT
184 int
185 default 16 if ARM64_64K_PAGES
186 default 14 if ARM64_16K_PAGES
187 default 12
189 config ARM64_CONT_SHIFT
190 int
191 default 5 if ARM64_64K_PAGES
192 default 7 if ARM64_16K_PAGES
193 default 4
195 config ARCH_MMAP_RND_BITS_MIN
196 default 14 if ARM64_64K_PAGES
197 default 16 if ARM64_16K_PAGES
198 default 18
200 # max bits determined by the following formula:
201 # VA_BITS - PAGE_SHIFT - 3
202 config ARCH_MMAP_RND_BITS_MAX
203 default 19 if ARM64_VA_BITS=36
204 default 24 if ARM64_VA_BITS=39
205 default 27 if ARM64_VA_BITS=42
206 default 30 if ARM64_VA_BITS=47
207 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
208 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
209 default 33 if ARM64_VA_BITS=48
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
212 default 18
214 config ARCH_MMAP_RND_COMPAT_BITS_MIN
215 default 7 if ARM64_64K_PAGES
216 default 9 if ARM64_16K_PAGES
217 default 11
219 config ARCH_MMAP_RND_COMPAT_BITS_MAX
220 default 16
222 config NO_IOPORT_MAP
223 def_bool y if !PCI
225 config STACKTRACE_SUPPORT
226 def_bool y
228 config ILLEGAL_POINTER_VALUE
229 hex
230 default 0xdead000000000000
232 config LOCKDEP_SUPPORT
233 def_bool y
235 config TRACE_IRQFLAGS_SUPPORT
236 def_bool y
238 config RWSEM_XCHGADD_ALGORITHM
239 def_bool y
241 config GENERIC_BUG
242 def_bool y
243 depends on BUG
245 config GENERIC_BUG_RELATIVE_POINTERS
246 def_bool y
247 depends on GENERIC_BUG
249 config GENERIC_HWEIGHT
250 def_bool y
252 config GENERIC_CSUM
253 def_bool y
255 config GENERIC_CALIBRATE_DELAY
256 def_bool y
258 config ZONE_DMA32
259 def_bool y
261 config HAVE_GENERIC_GUP
262 def_bool y
264 config SMP
265 def_bool y
267 config KERNEL_MODE_NEON
268 def_bool y
270 config FIX_EARLYCON_MEM
271 def_bool y
273 config PGTABLE_LEVELS
274 int
275 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
276 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
277 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
278 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
279 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
280 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
282 config ARCH_SUPPORTS_UPROBES
283 def_bool y
285 config ARCH_PROC_KCORE_TEXT
286 def_bool y
288 source "arch/arm64/Kconfig.platforms"
290 menu "Bus support"
292 config PCI
293 bool "PCI support"
294 help
295 This feature enables support for PCI bus system. If you say Y
296 here, the kernel will include drivers and infrastructure code
297 to support PCI bus devices.
299 config PCI_DOMAINS
300 def_bool PCI
302 config PCI_DOMAINS_GENERIC
303 def_bool PCI
305 config PCI_SYSCALL
306 def_bool PCI
308 source "drivers/pci/Kconfig"
310 endmenu
312 menu "Kernel Features"
314 menu "ARM errata workarounds via the alternatives framework"
316 config ARM64_ERRATUM_826319
317 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
318 default y
319 help
320 This option adds an alternative code sequence to work around ARM
321 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
322 AXI master interface and an L2 cache.
324 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
325 and is unable to accept a certain write via this interface, it will
326 not progress on read data presented on the read data channel and the
327 system can deadlock.
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this does not necessarily enable the workaround,
332 as it depends on the alternative framework, which will only patch
333 the kernel if an affected CPU is detected.
335 If unsure, say Y.
337 config ARM64_ERRATUM_827319
338 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
339 default y
340 help
341 This option adds an alternative code sequence to work around ARM
342 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
343 master interface and an L2 cache.
345 Under certain conditions this erratum can cause a clean line eviction
346 to occur at the same time as another transaction to the same address
347 on the AMBA 5 CHI interface, which can cause data corruption if the
348 interconnect reorders the two transactions.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
356 If unsure, say Y.
358 config ARM64_ERRATUM_824069
359 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
360 default y
361 help
362 This option adds an alternative code sequence to work around ARM
363 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
364 to a coherent interconnect.
366 If a Cortex-A53 processor is executing a store or prefetch for
367 write instruction at the same time as a processor in another
368 cluster is executing a cache maintenance operation to the same
369 address, then this erratum might cause a clean cache line to be
370 incorrectly marked as dirty.
372 The workaround promotes data cache clean instructions to
373 data cache clean-and-invalidate.
374 Please note that this option does not necessarily enable the
375 workaround, as it depends on the alternative framework, which will
376 only patch the kernel if an affected CPU is detected.
378 If unsure, say Y.
380 config ARM64_ERRATUM_819472
381 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
382 default y
383 help
384 This option adds an alternative code sequence to work around ARM
385 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
386 present when it is connected to a coherent interconnect.
388 If the processor is executing a load and store exclusive sequence at
389 the same time as a processor in another cluster is executing a cache
390 maintenance operation to the same address, then this erratum might
391 cause data corruption.
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
399 If unsure, say Y.
401 config ARM64_ERRATUM_832075
402 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
403 default y
404 help
405 This option adds an alternative code sequence to work around ARM
406 erratum 832075 on Cortex-A57 parts up to r1p2.
408 Affected Cortex-A57 parts might deadlock when exclusive load/store
409 instructions to Write-Back memory are mixed with Device loads.
411 The workaround is to promote device loads to use Load-Acquire
412 semantics.
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
417 If unsure, say Y.
419 config ARM64_ERRATUM_834220
420 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
421 depends on KVM
422 default y
423 help
424 This option adds an alternative code sequence to work around ARM
425 erratum 834220 on Cortex-A57 parts up to r1p2.
427 Affected Cortex-A57 parts might report a Stage 2 translation
428 fault as the result of a Stage 1 fault for load crossing a
429 page boundary when there is a permission or device memory
430 alignment fault at Stage 1 and a translation fault at Stage 2.
432 The workaround is to verify that the Stage 1 translation
433 doesn't generate a fault before handling the Stage 2 fault.
434 Please note that this does not necessarily enable the workaround,
435 as it depends on the alternative framework, which will only patch
436 the kernel if an affected CPU is detected.
438 If unsure, say Y.
440 config ARM64_ERRATUM_845719
441 bool "Cortex-A53: 845719: a load might read incorrect data"
442 depends on COMPAT
443 default y
444 help
445 This option adds an alternative code sequence to work around ARM
446 erratum 845719 on Cortex-A53 parts up to r0p4.
448 When running a compat (AArch32) userspace on an affected Cortex-A53
449 part, a load at EL0 from a virtual address that matches the bottom 32
450 bits of the virtual address used by a recent load at (AArch64) EL1
451 might return incorrect data.
453 The workaround is to write the contextidr_el1 register on exception
454 return to a 32-bit task.
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
459 If unsure, say Y.
461 config ARM64_ERRATUM_843419
462 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
463 default y
464 select ARM64_MODULE_PLTS if MODULES
465 help
466 This option links the kernel with '--fix-cortex-a53-843419' and
467 enables PLT support to replace certain ADRP instructions, which can
468 cause subsequent memory accesses to use an incorrect address on
469 Cortex-A53 parts up to r0p4.
471 If unsure, say Y.
473 config ARM64_ERRATUM_1024718
474 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
475 default y
476 help
477 This option adds work around for Arm Cortex-A55 Erratum 1024718.
479 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
480 update of the hardware dirty bit when the DBM/AP bits are updated
481 without a break-before-make. The work around is to disable the usage
482 of hardware DBM locally on the affected cores. CPUs not affected by
483 erratum will continue to use the feature.
485 If unsure, say Y.
487 config ARM64_ERRATUM_1188873
488 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
489 default y
490 select ARM_ARCH_TIMER_OOL_WORKAROUND
491 help
492 This option adds work arounds for ARM Cortex-A76 erratum 1188873
494 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
495 register corruption when accessing the timer registers from
496 AArch32 userspace.
498 If unsure, say Y.
500 config CAVIUM_ERRATUM_22375
501 bool "Cavium erratum 22375, 24313"
502 default y
503 help
504 Enable workaround for erratum 22375, 24313.
506 This implements two gicv3-its errata workarounds for ThunderX. Both
507 with small impact affecting only ITS table allocation.
509 erratum 22375: only alloc 8MB table size
510 erratum 24313: ignore memory access type
512 The fixes are in ITS initialization and basically ignore memory access
513 type and table size provided by the TYPER and BASER registers.
515 If unsure, say Y.
517 config CAVIUM_ERRATUM_23144
518 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
519 depends on NUMA
520 default y
521 help
522 ITS SYNC command hang for cross node io and collections/cpu mapping.
524 If unsure, say Y.
526 config CAVIUM_ERRATUM_23154
527 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
528 default y
529 help
530 The gicv3 of ThunderX requires a modified version for
531 reading the IAR status to ensure data synchronization
532 (access to icc_iar1_el1 is not sync'ed before and after).
534 If unsure, say Y.
536 config CAVIUM_ERRATUM_27456
537 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
538 default y
539 help
540 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
541 instructions may cause the icache to become corrupted if it
542 contains data for a non-current ASID. The fix is to
543 invalidate the icache when changing the mm context.
545 If unsure, say Y.
547 config CAVIUM_ERRATUM_30115
548 bool "Cavium erratum 30115: Guest may disable interrupts in host"
549 default y
550 help
551 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
552 1.2, and T83 Pass 1.0, KVM guest execution may disable
553 interrupts in host. Trapping both GICv3 group-0 and group-1
554 accesses sidesteps the issue.
556 If unsure, say Y.
558 config QCOM_FALKOR_ERRATUM_1003
559 bool "Falkor E1003: Incorrect translation due to ASID change"
560 default y
561 help
562 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
563 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
564 in TTBR1_EL1, this situation only occurs in the entry trampoline and
565 then only for entries in the walk cache, since the leaf translation
566 is unchanged. Work around the erratum by invalidating the walk cache
567 entries for the trampoline before entering the kernel proper.
569 config QCOM_FALKOR_ERRATUM_1009
570 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
571 default y
572 help
573 On Falkor v1, the CPU may prematurely complete a DSB following a
574 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
575 one more time to fix the issue.
577 If unsure, say Y.
579 config QCOM_QDF2400_ERRATUM_0065
580 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
581 default y
582 help
583 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
584 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
585 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
587 If unsure, say Y.
589 config SOCIONEXT_SYNQUACER_PREITS
590 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
591 default y
592 help
593 Socionext Synquacer SoCs implement a separate h/w block to generate
594 MSI doorbell writes with non-zero values for the device ID.
596 If unsure, say Y.
598 config HISILICON_ERRATUM_161600802
599 bool "Hip07 161600802: Erroneous redistributor VLPI base"
600 default y
601 help
602 The HiSilicon Hip07 SoC usees the wrong redistributor base
603 when issued ITS commands such as VMOVP and VMAPP, and requires
604 a 128kB offset to be applied to the target address in this commands.
606 If unsure, say Y.
608 config QCOM_FALKOR_ERRATUM_E1041
609 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
610 default y
611 help
612 Falkor CPU may speculatively fetch instructions from an improper
613 memory location when MMU translation is changed from SCTLR_ELn[M]=1
614 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
616 If unsure, say Y.
618 endmenu
621 choice
622 prompt "Page size"
623 default ARM64_4K_PAGES
624 help
625 Page size (translation granule) configuration.
627 config ARM64_4K_PAGES
628 bool "4KB"
629 help
630 This feature enables 4KB pages support.
632 config ARM64_16K_PAGES
633 bool "16KB"
634 help
635 The system will use 16KB pages support. AArch32 emulation
636 requires applications compiled with 16K (or a multiple of 16K)
637 aligned segments.
639 config ARM64_64K_PAGES
640 bool "64KB"
641 help
642 This feature enables 64KB pages support (4KB by default)
643 allowing only two levels of page tables and faster TLB
644 look-up. AArch32 emulation requires applications compiled
645 with 64K aligned segments.
647 endchoice
649 choice
650 prompt "Virtual address space size"
651 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
652 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
653 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
654 help
655 Allows choosing one of multiple possible virtual address
656 space sizes. The level of translation table is determined by
657 a combination of page size and virtual address space size.
659 config ARM64_VA_BITS_36
660 bool "36-bit" if EXPERT
661 depends on ARM64_16K_PAGES
663 config ARM64_VA_BITS_39
664 bool "39-bit"
665 depends on ARM64_4K_PAGES
667 config ARM64_VA_BITS_42
668 bool "42-bit"
669 depends on ARM64_64K_PAGES
671 config ARM64_VA_BITS_47
672 bool "47-bit"
673 depends on ARM64_16K_PAGES
675 config ARM64_VA_BITS_48
676 bool "48-bit"
678 endchoice
680 config ARM64_VA_BITS
681 int
682 default 36 if ARM64_VA_BITS_36
683 default 39 if ARM64_VA_BITS_39
684 default 42 if ARM64_VA_BITS_42
685 default 47 if ARM64_VA_BITS_47
686 default 48 if ARM64_VA_BITS_48
688 choice
689 prompt "Physical address space size"
690 default ARM64_PA_BITS_48
691 help
692 Choose the maximum physical address range that the kernel will
693 support.
695 config ARM64_PA_BITS_48
696 bool "48-bit"
698 config ARM64_PA_BITS_52
699 bool "52-bit (ARMv8.2)"
700 depends on ARM64_64K_PAGES
701 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
702 help
703 Enable support for a 52-bit physical address space, introduced as
704 part of the ARMv8.2-LPA extension.
706 With this enabled, the kernel will also continue to work on CPUs that
707 do not support ARMv8.2-LPA, but with some added memory overhead (and
708 minor performance overhead).
710 endchoice
712 config ARM64_PA_BITS
713 int
714 default 48 if ARM64_PA_BITS_48
715 default 52 if ARM64_PA_BITS_52
717 config CPU_BIG_ENDIAN
718 bool "Build big-endian kernel"
719 help
720 Say Y if you plan on running a kernel in big-endian mode.
722 config SCHED_MC
723 bool "Multi-core scheduler support"
724 help
725 Multi-core scheduler support improves the CPU scheduler's decision
726 making when dealing with multi-core CPU chips at a cost of slightly
727 increased overhead in some places. If unsure say N here.
729 config SCHED_SMT
730 bool "SMT scheduler support"
731 help
732 Improves the CPU scheduler's decision making when dealing with
733 MultiThreading at a cost of slightly increased overhead in some
734 places. If unsure say N here.
736 config NR_CPUS
737 int "Maximum number of CPUs (2-4096)"
738 range 2 4096
739 # These have to remain sorted largest to smallest
740 default "64"
742 config HOTPLUG_CPU
743 bool "Support for hot-pluggable CPUs"
744 select GENERIC_IRQ_MIGRATION
745 help
746 Say Y here to experiment with turning CPUs off and on. CPUs
747 can be controlled through /sys/devices/system/cpu.
749 # Common NUMA Features
750 config NUMA
751 bool "Numa Memory Allocation and Scheduler Support"
752 select ACPI_NUMA if ACPI
753 select OF_NUMA
754 help
755 Enable NUMA (Non Uniform Memory Access) support.
757 The kernel will try to allocate memory used by a CPU on the
758 local memory of the CPU and add some more
759 NUMA awareness to the kernel.
761 config NODES_SHIFT
762 int "Maximum NUMA Nodes (as a power of 2)"
763 range 1 10
764 default "2"
765 depends on NEED_MULTIPLE_NODES
766 help
767 Specify the maximum number of NUMA Nodes available on the target
768 system. Increases memory reserved to accommodate various tables.
770 config USE_PERCPU_NUMA_NODE_ID
771 def_bool y
772 depends on NUMA
774 config HAVE_SETUP_PER_CPU_AREA
775 def_bool y
776 depends on NUMA
778 config NEED_PER_CPU_EMBED_FIRST_CHUNK
779 def_bool y
780 depends on NUMA
782 config HOLES_IN_ZONE
783 def_bool y
785 source kernel/Kconfig.hz
787 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
788 def_bool y
790 config ARCH_SPARSEMEM_ENABLE
791 def_bool y
792 select SPARSEMEM_VMEMMAP_ENABLE
794 config ARCH_SPARSEMEM_DEFAULT
795 def_bool ARCH_SPARSEMEM_ENABLE
797 config ARCH_SELECT_MEMORY_MODEL
798 def_bool ARCH_SPARSEMEM_ENABLE
800 config ARCH_FLATMEM_ENABLE
801 def_bool !NUMA
803 config HAVE_ARCH_PFN_VALID
804 def_bool y
806 config HW_PERF_EVENTS
807 def_bool y
808 depends on ARM_PMU
810 config SYS_SUPPORTS_HUGETLBFS
811 def_bool y
813 config ARCH_WANT_HUGE_PMD_SHARE
814 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
816 config ARCH_HAS_CACHE_LINE_SIZE
817 def_bool y
819 config SECCOMP
820 bool "Enable seccomp to safely compute untrusted bytecode"
821 ---help---
822 This kernel feature is useful for number crunching applications
823 that may need to compute untrusted bytecode during their
824 execution. By using pipes or other transports made available to
825 the process as file descriptors supporting the read/write
826 syscalls, it's possible to isolate those applications in
827 their own address space using seccomp. Once seccomp is
828 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
829 and the task is only allowed to execute a few safe syscalls
830 defined by each seccomp mode.
832 config PARAVIRT
833 bool "Enable paravirtualization code"
834 help
835 This changes the kernel so it can modify itself when it is run
836 under a hypervisor, potentially improving performance significantly
837 over full virtualization.
839 config PARAVIRT_TIME_ACCOUNTING
840 bool "Paravirtual steal time accounting"
841 select PARAVIRT
842 default n
843 help
844 Select this option to enable fine granularity task steal time
845 accounting. Time spent executing other tasks in parallel with
846 the current vCPU is discounted from the vCPU power. To account for
847 that, there can be a small performance impact.
849 If in doubt, say N here.
851 config KEXEC
852 depends on PM_SLEEP_SMP
853 select KEXEC_CORE
854 bool "kexec system call"
855 ---help---
856 kexec is a system call that implements the ability to shutdown your
857 current kernel, and to start another kernel. It is like a reboot
858 but it is independent of the system firmware. And like a reboot
859 you can start any kernel with it, not just Linux.
861 config CRASH_DUMP
862 bool "Build kdump crash kernel"
863 help
864 Generate crash dump after being started by kexec. This should
865 be normally only set in special crash dump kernels which are
866 loaded in the main kernel with kexec-tools into a specially
867 reserved region and then later executed after a crash by
868 kdump/kexec.
870 For more details see Documentation/kdump/kdump.txt
872 config XEN_DOM0
873 def_bool y
874 depends on XEN
876 config XEN
877 bool "Xen guest support on ARM64"
878 depends on ARM64 && OF
879 select SWIOTLB_XEN
880 select PARAVIRT
881 help
882 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
884 config FORCE_MAX_ZONEORDER
885 int
886 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
887 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
888 default "11"
889 help
890 The kernel memory allocator divides physically contiguous memory
891 blocks into "zones", where each zone is a power of two number of
892 pages. This option selects the largest power of two that the kernel
893 keeps in the memory allocator. If you need to allocate very large
894 blocks of physically contiguous memory, then you may need to
895 increase this value.
897 This config option is actually maximum order plus one. For example,
898 a value of 11 means that the largest free memory block is 2^10 pages.
900 We make sure that we can allocate upto a HugePage size for each configuration.
901 Hence we have :
902 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
904 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
905 4M allocations matching the default size used by generic code.
907 config UNMAP_KERNEL_AT_EL0
908 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
909 default y
910 help
911 Speculation attacks against some high-performance processors can
912 be used to bypass MMU permission checks and leak kernel data to
913 userspace. This can be defended against by unmapping the kernel
914 when running in userspace, mapping it back in on exception entry
915 via a trampoline page in the vector table.
917 If unsure, say Y.
919 config HARDEN_BRANCH_PREDICTOR
920 bool "Harden the branch predictor against aliasing attacks" if EXPERT
921 default y
922 help
923 Speculation attacks against some high-performance processors rely on
924 being able to manipulate the branch predictor for a victim context by
925 executing aliasing branches in the attacker context. Such attacks
926 can be partially mitigated against by clearing internal branch
927 predictor state and limiting the prediction logic in some situations.
929 This config option will take CPU-specific actions to harden the
930 branch predictor against aliasing attacks and may rely on specific
931 instruction sequences or control bits being set by the system
932 firmware.
934 If unsure, say Y.
936 config HARDEN_EL2_VECTORS
937 bool "Harden EL2 vector mapping against system register leak" if EXPERT
938 default y
939 help
940 Speculation attacks against some high-performance processors can
941 be used to leak privileged information such as the vector base
942 register, resulting in a potential defeat of the EL2 layout
943 randomization.
945 This config option will map the vectors to a fixed location,
946 independent of the EL2 code mapping, so that revealing VBAR_EL2
947 to an attacker does not give away any extra information. This
948 only gets enabled on affected CPUs.
950 If unsure, say Y.
952 config ARM64_SSBD
953 bool "Speculative Store Bypass Disable" if EXPERT
954 default y
955 help
956 This enables mitigation of the bypassing of previous stores
957 by speculative loads.
959 If unsure, say Y.
961 menuconfig ARMV8_DEPRECATED
962 bool "Emulate deprecated/obsolete ARMv8 instructions"
963 depends on COMPAT
964 depends on SYSCTL
965 help
966 Legacy software support may require certain instructions
967 that have been deprecated or obsoleted in the architecture.
969 Enable this config to enable selective emulation of these
970 features.
972 If unsure, say Y
974 if ARMV8_DEPRECATED
976 config SWP_EMULATION
977 bool "Emulate SWP/SWPB instructions"
978 help
979 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
980 they are always undefined. Say Y here to enable software
981 emulation of these instructions for userspace using LDXR/STXR.
983 In some older versions of glibc [<=2.8] SWP is used during futex
984 trylock() operations with the assumption that the code will not
985 be preempted. This invalid assumption may be more likely to fail
986 with SWP emulation enabled, leading to deadlock of the user
987 application.
989 NOTE: when accessing uncached shared regions, LDXR/STXR rely
990 on an external transaction monitoring block called a global
991 monitor to maintain update atomicity. If your system does not
992 implement a global monitor, this option can cause programs that
993 perform SWP operations to uncached memory to deadlock.
995 If unsure, say Y
997 config CP15_BARRIER_EMULATION
998 bool "Emulate CP15 Barrier instructions"
999 help
1000 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1001 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1002 strongly recommended to use the ISB, DSB, and DMB
1003 instructions instead.
1005 Say Y here to enable software emulation of these
1006 instructions for AArch32 userspace code. When this option is
1007 enabled, CP15 barrier usage is traced which can help
1008 identify software that needs updating.
1010 If unsure, say Y
1012 config SETEND_EMULATION
1013 bool "Emulate SETEND instruction"
1014 help
1015 The SETEND instruction alters the data-endianness of the
1016 AArch32 EL0, and is deprecated in ARMv8.
1018 Say Y here to enable software emulation of the instruction
1019 for AArch32 userspace code.
1021 Note: All the cpus on the system must have mixed endian support at EL0
1022 for this feature to be enabled. If a new CPU - which doesn't support mixed
1023 endian - is hotplugged in after this feature has been enabled, there could
1024 be unexpected results in the applications.
1026 If unsure, say Y
1027 endif
1029 config ARM64_SW_TTBR0_PAN
1030 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1031 help
1032 Enabling this option prevents the kernel from accessing
1033 user-space memory directly by pointing TTBR0_EL1 to a reserved
1034 zeroed area and reserved ASID. The user access routines
1035 restore the valid TTBR0_EL1 temporarily.
1037 menu "ARMv8.1 architectural features"
1039 config ARM64_HW_AFDBM
1040 bool "Support for hardware updates of the Access and Dirty page flags"
1041 default y
1042 help
1043 The ARMv8.1 architecture extensions introduce support for
1044 hardware updates of the access and dirty information in page
1045 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1046 capable processors, accesses to pages with PTE_AF cleared will
1047 set this bit instead of raising an access flag fault.
1048 Similarly, writes to read-only pages with the DBM bit set will
1049 clear the read-only bit (AP[2]) instead of raising a
1050 permission fault.
1052 Kernels built with this configuration option enabled continue
1053 to work on pre-ARMv8.1 hardware and the performance impact is
1054 minimal. If unsure, say Y.
1056 config ARM64_PAN
1057 bool "Enable support for Privileged Access Never (PAN)"
1058 default y
1059 help
1060 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1061 prevents the kernel or hypervisor from accessing user-space (EL0)
1062 memory directly.
1064 Choosing this option will cause any unprotected (not using
1065 copy_to_user et al) memory access to fail with a permission fault.
1067 The feature is detected at runtime, and will remain as a 'nop'
1068 instruction if the cpu does not implement the feature.
1070 config ARM64_LSE_ATOMICS
1071 bool "Atomic instructions"
1072 default y
1073 help
1074 As part of the Large System Extensions, ARMv8.1 introduces new
1075 atomic instructions that are designed specifically to scale in
1076 very large systems.
1078 Say Y here to make use of these instructions for the in-kernel
1079 atomic routines. This incurs a small overhead on CPUs that do
1080 not support these instructions and requires the kernel to be
1081 built with binutils >= 2.25 in order for the new instructions
1082 to be used.
1084 config ARM64_VHE
1085 bool "Enable support for Virtualization Host Extensions (VHE)"
1086 default y
1087 help
1088 Virtualization Host Extensions (VHE) allow the kernel to run
1089 directly at EL2 (instead of EL1) on processors that support
1090 it. This leads to better performance for KVM, as they reduce
1091 the cost of the world switch.
1093 Selecting this option allows the VHE feature to be detected
1094 at runtime, and does not affect processors that do not
1095 implement this feature.
1097 endmenu
1099 menu "ARMv8.2 architectural features"
1101 config ARM64_UAO
1102 bool "Enable support for User Access Override (UAO)"
1103 default y
1104 help
1105 User Access Override (UAO; part of the ARMv8.2 Extensions)
1106 causes the 'unprivileged' variant of the load/store instructions to
1107 be overridden to be privileged.
1109 This option changes get_user() and friends to use the 'unprivileged'
1110 variant of the load/store instructions. This ensures that user-space
1111 really did have access to the supplied memory. When addr_limit is
1112 set to kernel memory the UAO bit will be set, allowing privileged
1113 access to kernel memory.
1115 Choosing this option will cause copy_to_user() et al to use user-space
1116 memory permissions.
1118 The feature is detected at runtime, the kernel will use the
1119 regular load/store instructions if the cpu does not implement the
1120 feature.
1122 config ARM64_PMEM
1123 bool "Enable support for persistent memory"
1124 select ARCH_HAS_PMEM_API
1125 select ARCH_HAS_UACCESS_FLUSHCACHE
1126 help
1127 Say Y to enable support for the persistent memory API based on the
1128 ARMv8.2 DCPoP feature.
1130 The feature is detected at runtime, and the kernel will use DC CVAC
1131 operations if DC CVAP is not supported (following the behaviour of
1132 DC CVAP itself if the system does not define a point of persistence).
1134 config ARM64_RAS_EXTN
1135 bool "Enable support for RAS CPU Extensions"
1136 default y
1137 help
1138 CPUs that support the Reliability, Availability and Serviceability
1139 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1140 errors, classify them and report them to software.
1142 On CPUs with these extensions system software can use additional
1143 barriers to determine if faults are pending and read the
1144 classification from a new set of registers.
1146 Selecting this feature will allow the kernel to use these barriers
1147 and access the new registers if the system supports the extension.
1148 Platform RAS features may additionally depend on firmware support.
1150 config ARM64_CNP
1151 bool "Enable support for Common Not Private (CNP) translations"
1152 default y
1153 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1154 help
1155 Common Not Private (CNP) allows translation table entries to
1156 be shared between different PEs in the same inner shareable
1157 domain, so the hardware can use this fact to optimise the
1158 caching of such entries in the TLB.
1160 Selecting this option allows the CNP feature to be detected
1161 at runtime, and does not affect PEs that do not implement
1162 this feature.
1164 endmenu
1166 config ARM64_SVE
1167 bool "ARM Scalable Vector Extension support"
1168 default y
1169 depends on !KVM || ARM64_VHE
1170 help
1171 The Scalable Vector Extension (SVE) is an extension to the AArch64
1172 execution state which complements and extends the SIMD functionality
1173 of the base architecture to support much larger vectors and to enable
1174 additional vectorisation opportunities.
1176 To enable use of this extension on CPUs that implement it, say Y.
1178 Note that for architectural reasons, firmware _must_ implement SVE
1179 support when running on SVE capable hardware. The required support
1180 is present in:
1182 * version 1.5 and later of the ARM Trusted Firmware
1183 * the AArch64 boot wrapper since commit 5e1261e08abf
1184 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1186 For other firmware implementations, consult the firmware documentation
1187 or vendor.
1189 If you need the kernel to boot on SVE-capable hardware with broken
1190 firmware, you may need to say N here until you get your firmware
1191 fixed. Otherwise, you may experience firmware panics or lockups when
1192 booting the kernel. If unsure and you are not observing these
1193 symptoms, you should assume that it is safe to say Y.
1195 CPUs that support SVE are architecturally required to support the
1196 Virtualization Host Extensions (VHE), so the kernel makes no
1197 provision for supporting SVE alongside KVM without VHE enabled.
1198 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1199 KVM in the same kernel image.
1201 config ARM64_MODULE_PLTS
1202 bool
1203 select HAVE_MOD_ARCH_SPECIFIC
1205 config RELOCATABLE
1206 bool
1207 help
1208 This builds the kernel as a Position Independent Executable (PIE),
1209 which retains all relocation metadata required to relocate the
1210 kernel binary at runtime to a different virtual address than the
1211 address it was linked at.
1212 Since AArch64 uses the RELA relocation format, this requires a
1213 relocation pass at runtime even if the kernel is loaded at the
1214 same address it was linked at.
1216 config RANDOMIZE_BASE
1217 bool "Randomize the address of the kernel image"
1218 select ARM64_MODULE_PLTS if MODULES
1219 select RELOCATABLE
1220 help
1221 Randomizes the virtual address at which the kernel image is
1222 loaded, as a security feature that deters exploit attempts
1223 relying on knowledge of the location of kernel internals.
1225 It is the bootloader's job to provide entropy, by passing a
1226 random u64 value in /chosen/kaslr-seed at kernel entry.
1228 When booting via the UEFI stub, it will invoke the firmware's
1229 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1230 to the kernel proper. In addition, it will randomise the physical
1231 location of the kernel Image as well.
1233 If unsure, say N.
1235 config RANDOMIZE_MODULE_REGION_FULL
1236 bool "Randomize the module region over a 4 GB range"
1237 depends on RANDOMIZE_BASE
1238 default y
1239 help
1240 Randomizes the location of the module region inside a 4 GB window
1241 covering the core kernel. This way, it is less likely for modules
1242 to leak information about the location of core kernel data structures
1243 but it does imply that function calls between modules and the core
1244 kernel will need to be resolved via veneers in the module PLT.
1246 When this option is not set, the module region will be randomized over
1247 a limited range that contains the [_stext, _etext] interval of the
1248 core kernel, so branch relocations are always in range.
1250 endmenu
1252 menu "Boot options"
1254 config ARM64_ACPI_PARKING_PROTOCOL
1255 bool "Enable support for the ARM64 ACPI parking protocol"
1256 depends on ACPI
1257 help
1258 Enable support for the ARM64 ACPI parking protocol. If disabled
1259 the kernel will not allow booting through the ARM64 ACPI parking
1260 protocol even if the corresponding data is present in the ACPI
1261 MADT table.
1263 config CMDLINE
1264 string "Default kernel command string"
1265 default ""
1266 help
1267 Provide a set of default command-line options at build time by
1268 entering them here. As a minimum, you should specify the the
1269 root device (e.g. root=/dev/nfs).
1271 config CMDLINE_FORCE
1272 bool "Always use the default kernel command string"
1273 help
1274 Always use the default kernel command string, even if the boot
1275 loader passes other arguments to the kernel.
1276 This is useful if you cannot or don't want to change the
1277 command-line options your boot loader passes to the kernel.
1279 config EFI_STUB
1280 bool
1282 config EFI
1283 bool "UEFI runtime support"
1284 depends on OF && !CPU_BIG_ENDIAN
1285 depends on KERNEL_MODE_NEON
1286 select ARCH_SUPPORTS_ACPI
1287 select LIBFDT
1288 select UCS2_STRING
1289 select EFI_PARAMS_FROM_FDT
1290 select EFI_RUNTIME_WRAPPERS
1291 select EFI_STUB
1292 select EFI_ARMSTUB
1293 default y
1294 help
1295 This option provides support for runtime services provided
1296 by UEFI firmware (such as non-volatile variables, realtime
1297 clock, and platform reset). A UEFI stub is also provided to
1298 allow the kernel to be booted as an EFI application. This
1299 is only useful on systems that have UEFI firmware.
1301 config DMI
1302 bool "Enable support for SMBIOS (DMI) tables"
1303 depends on EFI
1304 default y
1305 help
1306 This enables SMBIOS/DMI feature for systems.
1308 This option is only useful on systems that have UEFI firmware.
1309 However, even with this option, the resultant kernel should
1310 continue to boot on existing non-UEFI platforms.
1312 endmenu
1314 config COMPAT
1315 bool "Kernel support for 32-bit EL0"
1316 depends on ARM64_4K_PAGES || EXPERT
1317 select COMPAT_BINFMT_ELF if BINFMT_ELF
1318 select HAVE_UID16
1319 select OLD_SIGSUSPEND3
1320 select COMPAT_OLD_SIGACTION
1321 help
1322 This option enables support for a 32-bit EL0 running under a 64-bit
1323 kernel at EL1. AArch32-specific components such as system calls,
1324 the user helper functions, VFP support and the ptrace interface are
1325 handled appropriately by the kernel.
1327 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1328 that you will only be able to execute AArch32 binaries that were compiled
1329 with page size aligned segments.
1331 If you want to execute 32-bit userspace applications, say Y.
1333 config SYSVIPC_COMPAT
1334 def_bool y
1335 depends on COMPAT && SYSVIPC
1337 menu "Power management options"
1339 source "kernel/power/Kconfig"
1341 config ARCH_HIBERNATION_POSSIBLE
1342 def_bool y
1343 depends on CPU_PM
1345 config ARCH_HIBERNATION_HEADER
1346 def_bool y
1347 depends on HIBERNATION
1349 config ARCH_SUSPEND_POSSIBLE
1350 def_bool y
1352 endmenu
1354 menu "CPU Power Management"
1356 source "drivers/cpuidle/Kconfig"
1358 source "drivers/cpufreq/Kconfig"
1360 endmenu
1362 source "drivers/firmware/Kconfig"
1364 source "drivers/acpi/Kconfig"
1366 source "arch/arm64/kvm/Kconfig"
1368 if CRYPTO
1369 source "arch/arm64/crypto/Kconfig"
1370 endif