1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "TI OMAP/AM/DM/DRA Family"
3 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
7 depends on ARCH_MULTI_V6
10 select SOC_HAS_OMAP2_SDRC
14 depends on ARCH_MULTI_V7
16 select ARM_CPU_SUSPEND if PM
17 select OMAP_INTERCONNECT
20 select SOC_HAS_OMAP2_SDRC
21 select ARM_ERRATA_430973
25 depends on ARCH_MULTI_V7
27 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
28 select ARM_CPU_SUSPEND if PM
29 select ARM_ERRATA_720789
31 select HAVE_ARM_SCU if SMP
32 select HAVE_ARM_TWD if SMP
33 select OMAP_INTERCONNECT
34 select OMAP_INTERCONNECT_BARRIER
35 select PL310_ERRATA_588369 if CACHE_L2X0
36 select PL310_ERRATA_727915 if CACHE_L2X0
39 select ARM_ERRATA_754322
40 select ARM_ERRATA_775420
41 select OMAP_INTERCONNECT
45 depends on ARCH_MULTI_V7
47 select ARM_CPU_SUSPEND if PM
49 select HAVE_ARM_SCU if SMP
50 select HAVE_ARM_ARCH_TIMER
51 select ARM_ERRATA_798181 if SMP
52 select OMAP_INTERCONNECT
53 select OMAP_INTERCONNECT_BARRIER
55 select ZONE_DMA if ARM_LPAE
59 depends on ARCH_MULTI_V7
61 select ARM_CPU_SUSPEND if PM
65 depends on ARCH_MULTI_V7
68 select MACH_OMAP_GENERIC
69 select MIGHT_HAVE_CACHE_L2X0
71 select GENERIC_CLOCKEVENTS_BROADCAST
73 select ARM_ERRATA_754322
74 select ARM_ERRATA_775420
75 select OMAP_INTERCONNECT
76 select ARM_CPU_SUSPEND if PM
80 depends on ARCH_MULTI_V7
82 select ARM_CPU_SUSPEND if PM
84 select HAVE_ARM_SCU if SMP
85 select HAVE_ARM_ARCH_TIMER
87 select ARM_ERRATA_798181 if SMP
88 select OMAP_INTERCONNECT
89 select OMAP_INTERCONNECT_BARRIER
91 select ZONE_DMA if ARM_LPAE
92 select PINCTRL_TI_IODELAY if OF && PINCTRL
96 select ARCH_HAS_BANDGAP
97 select ARCH_HAS_HOLES_MEMORYMODEL
100 select GENERIC_IRQ_CHIP
102 select MACH_OMAP_GENERIC
113 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
115 config OMAP_INTERCONNECT_BARRIER
122 menu "TI OMAP2/3/4 Specific Features"
124 config ARCH_OMAP2PLUS_TYPICAL
125 bool "Typical OMAP configuration"
131 select MENELAUS if ARCH_OMAP2
132 select NEON if CPU_V7
135 select REGULATOR_FIXED_VOLTAGE
136 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
137 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
140 Compile a kernel suitable for booting most boards
142 config SOC_HAS_OMAP2_SDRC
143 bool "OMAP2 SDRAM Controller support"
145 config SOC_HAS_REALTIME_COUNTER
146 bool "Real time free running counter"
147 depends on SOC_OMAP5 || SOC_DRA7XX
150 comment "OMAP Core Type"
151 depends on ARCH_OMAP2
154 bool "OMAP2420 support"
155 depends on ARCH_OMAP2
158 select SOC_HAS_OMAP2_SDRC
161 bool "OMAP2430 support"
162 depends on ARCH_OMAP2
164 select SOC_HAS_OMAP2_SDRC
167 bool "OMAP3430 support"
168 depends on ARCH_OMAP3
170 select SOC_HAS_OMAP2_SDRC
173 bool "TI81XX support"
174 depends on ARCH_OMAP3
177 config OMAP_PACKAGE_CBC
180 config OMAP_PACKAGE_CBB
183 config OMAP_PACKAGE_CUS
186 config OMAP_PACKAGE_CBP
189 comment "OMAP Legacy Platform Data Board Type"
190 depends on ARCH_OMAP2PLUS
192 config MACH_OMAP_GENERIC
195 config MACH_OMAP2_TUSB6010
197 depends on ARCH_OMAP2 && SOC_OMAP2420
198 default y if MACH_NOKIA_N8X0
200 config MACH_OMAP3517EVM
201 bool "OMAP3517/ AM3517 EVM board"
202 depends on ARCH_OMAP3
205 config MACH_OMAP3_PANDORA
207 depends on ARCH_OMAP3
209 select OMAP_PACKAGE_CBB
211 config MACH_NOKIA_N810
214 config MACH_NOKIA_N810_WIMAX
217 config MACH_NOKIA_N8X0
218 bool "Nokia N800/N810"
219 depends on SOC_OMAP2420
221 select MACH_NOKIA_N810
222 select MACH_NOKIA_N810_WIMAX
224 config OMAP3_SDRC_AC_TIMING
225 bool "Enable SDRC AC timing register changes"
226 depends on ARCH_OMAP3
228 If you know that none of your system initiators will attempt to
229 access SDRAM during CORE DVFS, select Y here. This should boost
230 SDRAM performance at lower CORE OPPs. There are relatively few
231 users who will wish to say yes at this point - almost everyone will
232 wish to say no. Selecting yes without understanding what is
233 going on could result in system crashes;
239 config OMAP5_ERRATA_801819
240 bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
241 depends on SOC_OMAP5 || SOC_DRA7XX
243 A livelock can occur in the L2 cache arbitration that might prevent
244 a snoop from completing. Under certain conditions this can cause the