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Linux 5.2
[linux-2.6/linux-2.6-arm.git] / drivers / ata / ahci.c
blobf7652baa6337043c82ef88c361477d4d7a5ca4e3
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_ign_iferr,
52 board_ahci_mobile,
53 board_ahci_nomsi,
54 board_ahci_noncq,
55 board_ahci_nosntf,
56 board_ahci_yes_fbs,
57
58 /* board IDs for specific chipsets in alphabetical order */
59 board_ahci_avn,
60 board_ahci_mcp65,
61 board_ahci_mcp77,
62 board_ahci_mcp89,
63 board_ahci_mv,
64 board_ahci_sb600,
65 board_ahci_sb700, /* for SB700 and SB800 */
66 board_ahci_vt8251,
67
68 /* aliases */
69 board_ahci_mcp_linux = board_ahci_mcp65,
70 board_ahci_mcp67 = board_ahci_mcp65,
71 board_ahci_mcp73 = board_ahci_mcp65,
72 board_ahci_mcp79 = board_ahci_mcp77,
73 };
74
75 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
76 static void ahci_remove_one(struct pci_dev *dev);
77 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
78 unsigned long deadline);
79 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
80 unsigned long deadline);
81 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
82 static bool is_mcp89_apple(struct pci_dev *pdev);
83 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 #ifdef CONFIG_PM
86 static int ahci_pci_device_runtime_suspend(struct device *dev);
87 static int ahci_pci_device_runtime_resume(struct device *dev);
88 #ifdef CONFIG_PM_SLEEP
89 static int ahci_pci_device_suspend(struct device *dev);
90 static int ahci_pci_device_resume(struct device *dev);
91 #endif
92 #endif /* CONFIG_PM */
93
94 static struct scsi_host_template ahci_sht = {
95 AHCI_SHT("ahci"),
96 };
97
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
101 };
102
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
106 };
107
108 static struct ata_port_operations ahci_avn_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_avn_hardreset,
111 };
112
113 static const struct ata_port_info ahci_port_info[] = {
114 /* by features */
115 [board_ahci] = {
116 .flags = AHCI_FLAG_COMMON,
117 .pio_mask = ATA_PIO4,
118 .udma_mask = ATA_UDMA6,
119 .port_ops = &ahci_ops,
120 },
121 [board_ahci_ign_iferr] = {
122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_mobile] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 /* by chipsets */
164 [board_ahci_avn] = {
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
169 },
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
172 AHCI_HFLAG_YES_NCQ),
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mv] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
208 },
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
222 },
223 };
224
225 static const struct pci_device_id ahci_pci_tbl[] = {
226 /* Intel */
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
321 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
324 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
330 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
332 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
340 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
341 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
344 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
345 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
350 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
353 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
355 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
357 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
361 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
362 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
363 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
364 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
365 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
366 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
368 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
369 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
370 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
371 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
372 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
374 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
375 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
379 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
382 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
384 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
385 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
386 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
387 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
388
389 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
390 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
392 /* JMicron 362B and 362C have an AHCI function with IDE class code */
393 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
394 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
395 /* May need to update quirk_jmicron_async_suspend() for additions */
396
397 /* ATI */
398 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
399 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
405
406 /* AMD */
407 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
408 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
409 /* AMD is using RAID class only for ahci controllers */
410 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
412
413 /* VIA */
414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
416
417 /* NVIDIA */
418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
502
503 /* SiS */
504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
507
508 /* ST Microelectronics */
509 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
510
511 /* Marvell */
512 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
513 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
515 .class = PCI_CLASS_STORAGE_SATA_AHCI,
516 .class_mask = 0xffffff,
517 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
520 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
524 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
526 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532 .driver_data = board_ahci_yes_fbs },
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
534 .driver_data = board_ahci_yes_fbs },
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
536 .driver_data = board_ahci_yes_fbs },
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
540 .driver_data = board_ahci_yes_fbs },
541 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
542 .driver_data = board_ahci_yes_fbs },
543
544 /* Promise */
545 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
546 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
547
548 /* Asmedia */
549 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
550 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
551 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
552 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
553 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
554 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
555
556 /*
557 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
558 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
559 */
560 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
561 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
562
563 /* Enmotus */
564 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
565
566 /* Generic, PCI class code for AHCI */
567 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
568 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
569
570 { } /* terminate list */
571 };
572
573 static const struct dev_pm_ops ahci_pci_pm_ops = {
574 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
575 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
576 ahci_pci_device_runtime_resume, NULL)
577 };
578
579 static struct pci_driver ahci_pci_driver = {
580 .name = DRV_NAME,
581 .id_table = ahci_pci_tbl,
582 .probe = ahci_init_one,
583 .remove = ahci_remove_one,
584 .driver = {
585 .pm = &ahci_pci_pm_ops,
586 },
587 };
588
589 #if IS_ENABLED(CONFIG_PATA_MARVELL)
590 static int marvell_enable;
591 #else
592 static int marvell_enable = 1;
593 #endif
594 module_param(marvell_enable, int, 0644);
595 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
596
597 static int mobile_lpm_policy = -1;
598 module_param(mobile_lpm_policy, int, 0644);
599 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
600
601 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
602 struct ahci_host_priv *hpriv)
603 {
604 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
605 dev_info(&pdev->dev, "JMB361 has only one port\n");
606 hpriv->force_port_map = 1;
607 }
608
609 /*
610 * Temporary Marvell 6145 hack: PATA port presence
611 * is asserted through the standard AHCI port
612 * presence register, as bit 4 (counting from 0)
613 */
614 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
615 if (pdev->device == 0x6121)
616 hpriv->mask_port_map = 0x3;
617 else
618 hpriv->mask_port_map = 0xf;
619 dev_info(&pdev->dev,
620 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
621 }
622
623 ahci_save_initial_config(&pdev->dev, hpriv);
624 }
625
626 static int ahci_pci_reset_controller(struct ata_host *host)
627 {
628 struct pci_dev *pdev = to_pci_dev(host->dev);
629 int rc;
630
631 rc = ahci_reset_controller(host);
632 if (rc)
633 return rc;
634
635 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
636 struct ahci_host_priv *hpriv = host->private_data;
637 u16 tmp16;
638
639 /* configure PCS */
640 pci_read_config_word(pdev, 0x92, &tmp16);
641 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
642 tmp16 |= hpriv->port_map;
643 pci_write_config_word(pdev, 0x92, tmp16);
644 }
645 }
646
647 return 0;
648 }
649
650 static void ahci_pci_init_controller(struct ata_host *host)
651 {
652 struct ahci_host_priv *hpriv = host->private_data;
653 struct pci_dev *pdev = to_pci_dev(host->dev);
654 void __iomem *port_mmio;
655 u32 tmp;
656 int mv;
657
658 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
659 if (pdev->device == 0x6121)
660 mv = 2;
661 else
662 mv = 4;
663 port_mmio = __ahci_port_base(host, mv);
664
665 writel(0, port_mmio + PORT_IRQ_MASK);
666
667 /* clear port IRQ */
668 tmp = readl(port_mmio + PORT_IRQ_STAT);
669 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
670 if (tmp)
671 writel(tmp, port_mmio + PORT_IRQ_STAT);
672 }
673
674 ahci_init_controller(host);
675 }
676
677 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
678 unsigned long deadline)
679 {
680 struct ata_port *ap = link->ap;
681 struct ahci_host_priv *hpriv = ap->host->private_data;
682 bool online;
683 int rc;
684
685 DPRINTK("ENTER\n");
686
687 hpriv->stop_engine(ap);
688
689 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
690 deadline, &online, NULL);
691
692 hpriv->start_engine(ap);
693
694 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
695
696 /* vt8251 doesn't clear BSY on signature FIS reception,
697 * request follow-up softreset.
698 */
699 return online ? -EAGAIN : rc;
700 }
701
702 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
704 {
705 struct ata_port *ap = link->ap;
706 struct ahci_port_priv *pp = ap->private_data;
707 struct ahci_host_priv *hpriv = ap->host->private_data;
708 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
709 struct ata_taskfile tf;
710 bool online;
711 int rc;
712
713 hpriv->stop_engine(ap);
714
715 /* clear D2H reception area to properly wait for D2H FIS */
716 ata_tf_init(link->device, &tf);
717 tf.command = ATA_BUSY;
718 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
719
720 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
721 deadline, &online, NULL);
722
723 hpriv->start_engine(ap);
724
725 /* The pseudo configuration device on SIMG4726 attached to
726 * ASUS P5W-DH Deluxe doesn't send signature FIS after
727 * hardreset if no device is attached to the first downstream
728 * port && the pseudo device locks up on SRST w/ PMP==0. To
729 * work around this, wait for !BSY only briefly. If BSY isn't
730 * cleared, perform CLO and proceed to IDENTIFY (achieved by
731 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
732 *
733 * Wait for two seconds. Devices attached to downstream port
734 * which can't process the following IDENTIFY after this will
735 * have to be reset again. For most cases, this should
736 * suffice while making probing snappish enough.
737 */
738 if (online) {
739 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
740 ahci_check_ready);
741 if (rc)
742 ahci_kick_engine(ap);
743 }
744 return rc;
745 }
746
747 /*
748 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
749 *
750 * It has been observed with some SSDs that the timing of events in the
751 * link synchronization phase can leave the port in a state that can not
752 * be recovered by a SATA-hard-reset alone. The failing signature is
753 * SStatus.DET stuck at 1 ("Device presence detected but Phy
754 * communication not established"). It was found that unloading and
755 * reloading the driver when this problem occurs allows the drive
756 * connection to be recovered (DET advanced to 0x3). The critical
757 * component of reloading the driver is that the port state machines are
758 * reset by bouncing "port enable" in the AHCI PCS configuration
759 * register. So, reproduce that effect by bouncing a port whenever we
760 * see DET==1 after a reset.
761 */
762 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
763 unsigned long deadline)
764 {
765 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
766 struct ata_port *ap = link->ap;
767 struct ahci_port_priv *pp = ap->private_data;
768 struct ahci_host_priv *hpriv = ap->host->private_data;
769 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
770 unsigned long tmo = deadline - jiffies;
771 struct ata_taskfile tf;
772 bool online;
773 int rc, i;
774
775 DPRINTK("ENTER\n");
776
777 hpriv->stop_engine(ap);
778
779 for (i = 0; i < 2; i++) {
780 u16 val;
781 u32 sstatus;
782 int port = ap->port_no;
783 struct ata_host *host = ap->host;
784 struct pci_dev *pdev = to_pci_dev(host->dev);
785
786 /* clear D2H reception area to properly wait for D2H FIS */
787 ata_tf_init(link->device, &tf);
788 tf.command = ATA_BUSY;
789 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
790
791 rc = sata_link_hardreset(link, timing, deadline, &online,
792 ahci_check_ready);
793
794 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
795 (sstatus & 0xf) != 1)
796 break;
797
798 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
799 port);
800
801 pci_read_config_word(pdev, 0x92, &val);
802 val &= ~(1 << port);
803 pci_write_config_word(pdev, 0x92, val);
804 ata_msleep(ap, 1000);
805 val |= 1 << port;
806 pci_write_config_word(pdev, 0x92, val);
807 deadline += tmo;
808 }
809
810 hpriv->start_engine(ap);
811
812 if (online)
813 *class = ahci_dev_classify(ap);
814
815 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
816 return rc;
817 }
818
819
820 #ifdef CONFIG_PM
821 static void ahci_pci_disable_interrupts(struct ata_host *host)
822 {
823 struct ahci_host_priv *hpriv = host->private_data;
824 void __iomem *mmio = hpriv->mmio;
825 u32 ctl;
826
827 /* AHCI spec rev1.1 section 8.3.3:
828 * Software must disable interrupts prior to requesting a
829 * transition of the HBA to D3 state.
830 */
831 ctl = readl(mmio + HOST_CTL);
832 ctl &= ~HOST_IRQ_EN;
833 writel(ctl, mmio + HOST_CTL);
834 readl(mmio + HOST_CTL); /* flush */
835 }
836
837 static int ahci_pci_device_runtime_suspend(struct device *dev)
838 {
839 struct pci_dev *pdev = to_pci_dev(dev);
840 struct ata_host *host = pci_get_drvdata(pdev);
841
842 ahci_pci_disable_interrupts(host);
843 return 0;
844 }
845
846 static int ahci_pci_device_runtime_resume(struct device *dev)
847 {
848 struct pci_dev *pdev = to_pci_dev(dev);
849 struct ata_host *host = pci_get_drvdata(pdev);
850 int rc;
851
852 rc = ahci_pci_reset_controller(host);
853 if (rc)
854 return rc;
855 ahci_pci_init_controller(host);
856 return 0;
857 }
858
859 #ifdef CONFIG_PM_SLEEP
860 static int ahci_pci_device_suspend(struct device *dev)
861 {
862 struct pci_dev *pdev = to_pci_dev(dev);
863 struct ata_host *host = pci_get_drvdata(pdev);
864 struct ahci_host_priv *hpriv = host->private_data;
865
866 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
867 dev_err(&pdev->dev,
868 "BIOS update required for suspend/resume\n");
869 return -EIO;
870 }
871
872 ahci_pci_disable_interrupts(host);
873 return ata_host_suspend(host, PMSG_SUSPEND);
874 }
875
876 static int ahci_pci_device_resume(struct device *dev)
877 {
878 struct pci_dev *pdev = to_pci_dev(dev);
879 struct ata_host *host = pci_get_drvdata(pdev);
880 int rc;
881
882 /* Apple BIOS helpfully mangles the registers on resume */
883 if (is_mcp89_apple(pdev))
884 ahci_mcp89_apple_enable(pdev);
885
886 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
887 rc = ahci_pci_reset_controller(host);
888 if (rc)
889 return rc;
890
891 ahci_pci_init_controller(host);
892 }
893
894 ata_host_resume(host);
895
896 return 0;
897 }
898 #endif
899
900 #endif /* CONFIG_PM */
901
902 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
903 {
904 int rc;
905
906 /*
907 * If the device fixup already set the dma_mask to some non-standard
908 * value, don't extend it here. This happens on STA2X11, for example.
909 */
910 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
911 return 0;
912
913 if (using_dac &&
914 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
915 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
916 if (rc) {
917 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
918 if (rc) {
919 dev_err(&pdev->dev,
920 "64-bit DMA enable failed\n");
921 return rc;
922 }
923 }
924 } else {
925 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
926 if (rc) {
927 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
928 return rc;
929 }
930 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
931 if (rc) {
932 dev_err(&pdev->dev,
933 "32-bit consistent DMA enable failed\n");
934 return rc;
935 }
936 }
937 return 0;
938 }
939
940 static void ahci_pci_print_info(struct ata_host *host)
941 {
942 struct pci_dev *pdev = to_pci_dev(host->dev);
943 u16 cc;
944 const char *scc_s;
945
946 pci_read_config_word(pdev, 0x0a, &cc);
947 if (cc == PCI_CLASS_STORAGE_IDE)
948 scc_s = "IDE";
949 else if (cc == PCI_CLASS_STORAGE_SATA)
950 scc_s = "SATA";
951 else if (cc == PCI_CLASS_STORAGE_RAID)
952 scc_s = "RAID";
953 else
954 scc_s = "unknown";
955
956 ahci_print_info(host, scc_s);
957 }
958
959 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
960 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
961 * support PMP and the 4726 either directly exports the device
962 * attached to the first downstream port or acts as a hardware storage
963 * controller and emulate a single ATA device (can be RAID 0/1 or some
964 * other configuration).
965 *
966 * When there's no device attached to the first downstream port of the
967 * 4726, "Config Disk" appears, which is a pseudo ATA device to
968 * configure the 4726. However, ATA emulation of the device is very
969 * lame. It doesn't send signature D2H Reg FIS after the initial
970 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
971 *
972 * The following function works around the problem by always using
973 * hardreset on the port and not depending on receiving signature FIS
974 * afterward. If signature FIS isn't received soon, ATA class is
975 * assumed without follow-up softreset.
976 */
977 static void ahci_p5wdh_workaround(struct ata_host *host)
978 {
979 static const struct dmi_system_id sysids[] = {
980 {
981 .ident = "P5W DH Deluxe",
982 .matches = {
983 DMI_MATCH(DMI_SYS_VENDOR,
984 "ASUSTEK COMPUTER INC"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
986 },
987 },
988 { }
989 };
990 struct pci_dev *pdev = to_pci_dev(host->dev);
991
992 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
993 dmi_check_system(sysids)) {
994 struct ata_port *ap = host->ports[1];
995
996 dev_info(&pdev->dev,
997 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
998
999 ap->ops = &ahci_p5wdh_ops;
1000 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1001 }
1002 }
1003
1004 /*
1005 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1006 * booting in BIOS compatibility mode. We restore the registers but not ID.
1007 */
1008 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1009 {
1010 u32 val;
1011
1012 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1013
1014 pci_read_config_dword(pdev, 0xf8, &val);
1015 val |= 1 << 0x1b;
1016 /* the following changes the device ID, but appears not to affect function */
1017 /* val = (val & ~0xf0000000) | 0x80000000; */
1018 pci_write_config_dword(pdev, 0xf8, val);
1019
1020 pci_read_config_dword(pdev, 0x54c, &val);
1021 val |= 1 << 0xc;
1022 pci_write_config_dword(pdev, 0x54c, val);
1023
1024 pci_read_config_dword(pdev, 0x4a4, &val);
1025 val &= 0xff;
1026 val |= 0x01060100;
1027 pci_write_config_dword(pdev, 0x4a4, val);
1028
1029 pci_read_config_dword(pdev, 0x54c, &val);
1030 val &= ~(1 << 0xc);
1031 pci_write_config_dword(pdev, 0x54c, val);
1032
1033 pci_read_config_dword(pdev, 0xf8, &val);
1034 val &= ~(1 << 0x1b);
1035 pci_write_config_dword(pdev, 0xf8, val);
1036 }
1037
1038 static bool is_mcp89_apple(struct pci_dev *pdev)
1039 {
1040 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1041 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1042 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1043 pdev->subsystem_device == 0xcb89;
1044 }
1045
1046 /* only some SB600 ahci controllers can do 64bit DMA */
1047 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1048 {
1049 static const struct dmi_system_id sysids[] = {
1050 /*
1051 * The oldest version known to be broken is 0901 and
1052 * working is 1501 which was released on 2007-10-26.
1053 * Enable 64bit DMA on 1501 and anything newer.
1054 *
1055 * Please read bko#9412 for more info.
1056 */
1057 {
1058 .ident = "ASUS M2A-VM",
1059 .matches = {
1060 DMI_MATCH(DMI_BOARD_VENDOR,
1061 "ASUSTeK Computer INC."),
1062 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1063 },
1064 .driver_data = "20071026", /* yyyymmdd */
1065 },
1066 /*
1067 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1068 * support 64bit DMA.
1069 *
1070 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1071 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1072 * This spelling mistake was fixed in BIOS version 1.5, so
1073 * 1.5 and later have the Manufacturer as
1074 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1075 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1076 *
1077 * BIOS versions earlier than 1.9 had a Board Product Name
1078 * DMI field of "MS-7376". This was changed to be
1079 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1080 * match on DMI_BOARD_NAME of "MS-7376".
1081 */
1082 {
1083 .ident = "MSI K9A2 Platinum",
1084 .matches = {
1085 DMI_MATCH(DMI_BOARD_VENDOR,
1086 "MICRO-STAR INTER"),
1087 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1088 },
1089 },
1090 /*
1091 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1092 * 64bit DMA.
1093 *
1094 * This board also had the typo mentioned above in the
1095 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1096 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1097 */
1098 {
1099 .ident = "MSI K9AGM2",
1100 .matches = {
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "MICRO-STAR INTER"),
1103 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1104 },
1105 },
1106 /*
1107 * All BIOS versions for the Asus M3A support 64bit DMA.
1108 * (all release versions from 0301 to 1206 were tested)
1109 */
1110 {
1111 .ident = "ASUS M3A",
1112 .matches = {
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "ASUSTeK Computer INC."),
1115 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1116 },
1117 },
1118 { }
1119 };
1120 const struct dmi_system_id *match;
1121 int year, month, date;
1122 char buf[9];
1123
1124 match = dmi_first_match(sysids);
1125 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1126 !match)
1127 return false;
1128
1129 if (!match->driver_data)
1130 goto enable_64bit;
1131
1132 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1133 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1134
1135 if (strcmp(buf, match->driver_data) >= 0)
1136 goto enable_64bit;
1137 else {
1138 dev_warn(&pdev->dev,
1139 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1140 match->ident);
1141 return false;
1142 }
1143
1144 enable_64bit:
1145 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1146 return true;
1147 }
1148
1149 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1150 {
1151 static const struct dmi_system_id broken_systems[] = {
1152 {
1153 .ident = "HP Compaq nx6310",
1154 .matches = {
1155 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1156 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1157 },
1158 /* PCI slot number of the controller */
1159 .driver_data = (void *)0x1FUL,
1160 },
1161 {
1162 .ident = "HP Compaq 6720s",
1163 .matches = {
1164 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1166 },
1167 /* PCI slot number of the controller */
1168 .driver_data = (void *)0x1FUL,
1169 },
1170
1171 { } /* terminate list */
1172 };
1173 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1174
1175 if (dmi) {
1176 unsigned long slot = (unsigned long)dmi->driver_data;
1177 /* apply the quirk only to on-board controllers */
1178 return slot == PCI_SLOT(pdev->devfn);
1179 }
1180
1181 return false;
1182 }
1183
1184 static bool ahci_broken_suspend(struct pci_dev *pdev)
1185 {
1186 static const struct dmi_system_id sysids[] = {
1187 /*
1188 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1189 * to the harddisk doesn't become online after
1190 * resuming from STR. Warn and fail suspend.
1191 *
1192 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1193 *
1194 * Use dates instead of versions to match as HP is
1195 * apparently recycling both product and version
1196 * strings.
1197 *
1198 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1199 */
1200 {
1201 .ident = "dv4",
1202 .matches = {
1203 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1204 DMI_MATCH(DMI_PRODUCT_NAME,
1205 "HP Pavilion dv4 Notebook PC"),
1206 },
1207 .driver_data = "20090105", /* F.30 */
1208 },
1209 {
1210 .ident = "dv5",
1211 .matches = {
1212 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1213 DMI_MATCH(DMI_PRODUCT_NAME,
1214 "HP Pavilion dv5 Notebook PC"),
1215 },
1216 .driver_data = "20090506", /* F.16 */
1217 },
1218 {
1219 .ident = "dv6",
1220 .matches = {
1221 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1222 DMI_MATCH(DMI_PRODUCT_NAME,
1223 "HP Pavilion dv6 Notebook PC"),
1224 },
1225 .driver_data = "20090423", /* F.21 */
1226 },
1227 {
1228 .ident = "HDX18",
1229 .matches = {
1230 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1231 DMI_MATCH(DMI_PRODUCT_NAME,
1232 "HP HDX18 Notebook PC"),
1233 },
1234 .driver_data = "20090430", /* F.23 */
1235 },
1236 /*
1237 * Acer eMachines G725 has the same problem. BIOS
1238 * V1.03 is known to be broken. V3.04 is known to
1239 * work. Between, there are V1.06, V2.06 and V3.03
1240 * that we don't have much idea about. For now,
1241 * blacklist anything older than V3.04.
1242 *
1243 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1244 */
1245 {
1246 .ident = "G725",
1247 .matches = {
1248 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1249 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1250 },
1251 .driver_data = "20091216", /* V3.04 */
1252 },
1253 { } /* terminate list */
1254 };
1255 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1256 int year, month, date;
1257 char buf[9];
1258
1259 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1260 return false;
1261
1262 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1263 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1264
1265 return strcmp(buf, dmi->driver_data) < 0;
1266 }
1267
1268 static bool ahci_broken_lpm(struct pci_dev *pdev)
1269 {
1270 static const struct dmi_system_id sysids[] = {
1271 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1272 {
1273 .matches = {
1274 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1275 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1276 },
1277 .driver_data = "20180406", /* 1.31 */
1278 },
1279 {
1280 .matches = {
1281 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1282 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1283 },
1284 .driver_data = "20180420", /* 1.28 */
1285 },
1286 {
1287 .matches = {
1288 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1289 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1290 },
1291 .driver_data = "20180315", /* 1.33 */
1292 },
1293 {
1294 .matches = {
1295 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1296 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1297 },
1298 /*
1299 * Note date based on release notes, 2.35 has been
1300 * reported to be good, but I've been unable to get
1301 * a hold of the reporter to get the DMI BIOS date.
1302 * TODO: fix this.
1303 */
1304 .driver_data = "20180310", /* 2.35 */
1305 },
1306 { } /* terminate list */
1307 };
1308 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1309 int year, month, date;
1310 char buf[9];
1311
1312 if (!dmi)
1313 return false;
1314
1315 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1316 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1317
1318 return strcmp(buf, dmi->driver_data) < 0;
1319 }
1320
1321 static bool ahci_broken_online(struct pci_dev *pdev)
1322 {
1323 #define ENCODE_BUSDEVFN(bus, slot, func) \
1324 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1325 static const struct dmi_system_id sysids[] = {
1326 /*
1327 * There are several gigabyte boards which use
1328 * SIMG5723s configured as hardware RAID. Certain
1329 * 5723 firmware revisions shipped there keep the link
1330 * online but fail to answer properly to SRST or
1331 * IDENTIFY when no device is attached downstream
1332 * causing libata to retry quite a few times leading
1333 * to excessive detection delay.
1334 *
1335 * As these firmwares respond to the second reset try
1336 * with invalid device signature, considering unknown
1337 * sig as offline works around the problem acceptably.
1338 */
1339 {
1340 .ident = "EP45-DQ6",
1341 .matches = {
1342 DMI_MATCH(DMI_BOARD_VENDOR,
1343 "Gigabyte Technology Co., Ltd."),
1344 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1345 },
1346 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1347 },
1348 {
1349 .ident = "EP45-DS5",
1350 .matches = {
1351 DMI_MATCH(DMI_BOARD_VENDOR,
1352 "Gigabyte Technology Co., Ltd."),
1353 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1354 },
1355 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1356 },
1357 { } /* terminate list */
1358 };
1359 #undef ENCODE_BUSDEVFN
1360 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1361 unsigned int val;
1362
1363 if (!dmi)
1364 return false;
1365
1366 val = (unsigned long)dmi->driver_data;
1367
1368 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1369 }
1370
1371 static bool ahci_broken_devslp(struct pci_dev *pdev)
1372 {
1373 /* device with broken DEVSLP but still showing SDS capability */
1374 static const struct pci_device_id ids[] = {
1375 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1376 {}
1377 };
1378
1379 return pci_match_id(ids, pdev);
1380 }
1381
1382 #ifdef CONFIG_ATA_ACPI
1383 static void ahci_gtf_filter_workaround(struct ata_host *host)
1384 {
1385 static const struct dmi_system_id sysids[] = {
1386 /*
1387 * Aspire 3810T issues a bunch of SATA enable commands
1388 * via _GTF including an invalid one and one which is
1389 * rejected by the device. Among the successful ones
1390 * is FPDMA non-zero offset enable which when enabled
1391 * only on the drive side leads to NCQ command
1392 * failures. Filter it out.
1393 */
1394 {
1395 .ident = "Aspire 3810T",
1396 .matches = {
1397 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1398 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1399 },
1400 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1401 },
1402 { }
1403 };
1404 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1405 unsigned int filter;
1406 int i;
1407
1408 if (!dmi)
1409 return;
1410
1411 filter = (unsigned long)dmi->driver_data;
1412 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1413 filter, dmi->ident);
1414
1415 for (i = 0; i < host->n_ports; i++) {
1416 struct ata_port *ap = host->ports[i];
1417 struct ata_link *link;
1418 struct ata_device *dev;
1419
1420 ata_for_each_link(link, ap, EDGE)
1421 ata_for_each_dev(dev, link, ALL)
1422 dev->gtf_filter |= filter;
1423 }
1424 }
1425 #else
1426 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1427 {}
1428 #endif
1429
1430 /*
1431 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1432 * as DUMMY, or detected but eventually get a "link down" and never get up
1433 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1434 * port_map may hold a value of 0x00.
1435 *
1436 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1437 * and can significantly reduce the occurrence of the problem.
1438 *
1439 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1440 */
1441 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1442 struct pci_dev *pdev)
1443 {
1444 static const struct dmi_system_id sysids[] = {
1445 {
1446 .ident = "Acer Switch Alpha 12",
1447 .matches = {
1448 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1449 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1450 },
1451 },
1452 { }
1453 };
1454
1455 if (dmi_check_system(sysids)) {
1456 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1457 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1458 hpriv->port_map = 0x7;
1459 hpriv->cap = 0xC734FF02;
1460 }
1461 }
1462 }
1463
1464 #ifdef CONFIG_ARM64
1465 /*
1466 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1467 * Workaround is to make sure all pending IRQs are served before leaving
1468 * handler.
1469 */
1470 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1471 {
1472 struct ata_host *host = dev_instance;
1473 struct ahci_host_priv *hpriv;
1474 unsigned int rc = 0;
1475 void __iomem *mmio;
1476 u32 irq_stat, irq_masked;
1477 unsigned int handled = 1;
1478
1479 VPRINTK("ENTER\n");
1480 hpriv = host->private_data;
1481 mmio = hpriv->mmio;
1482 irq_stat = readl(mmio + HOST_IRQ_STAT);
1483 if (!irq_stat)
1484 return IRQ_NONE;
1485
1486 do {
1487 irq_masked = irq_stat & hpriv->port_map;
1488 spin_lock(&host->lock);
1489 rc = ahci_handle_port_intr(host, irq_masked);
1490 if (!rc)
1491 handled = 0;
1492 writel(irq_stat, mmio + HOST_IRQ_STAT);
1493 irq_stat = readl(mmio + HOST_IRQ_STAT);
1494 spin_unlock(&host->lock);
1495 } while (irq_stat);
1496 VPRINTK("EXIT\n");
1497
1498 return IRQ_RETVAL(handled);
1499 }
1500 #endif
1501
1502 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1503 struct ahci_host_priv *hpriv)
1504 {
1505 int i, count = 0;
1506 u32 cap;
1507
1508 /*
1509 * Check if this device might have remapped nvme devices.
1510 */
1511 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1512 pci_resource_len(pdev, bar) < SZ_512K ||
1513 bar != AHCI_PCI_BAR_STANDARD ||
1514 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1515 return;
1516
1517 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1518 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1519 if ((cap & (1 << i)) == 0)
1520 continue;
1521 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1522 != PCI_CLASS_STORAGE_EXPRESS)
1523 continue;
1524
1525 /* We've found a remapped device */
1526 count++;
1527 }
1528
1529 if (!count)
1530 return;
1531
1532 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1533 dev_warn(&pdev->dev,
1534 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1535
1536 /*
1537 * Don't rely on the msi-x capability in the remap case,
1538 * share the legacy interrupt across ahci and remapped devices.
1539 */
1540 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1541 }
1542
1543 static int ahci_get_irq_vector(struct ata_host *host, int port)
1544 {
1545 return pci_irq_vector(to_pci_dev(host->dev), port);
1546 }
1547
1548 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1549 struct ahci_host_priv *hpriv)
1550 {
1551 int nvec;
1552
1553 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1554 return -ENODEV;
1555
1556 /*
1557 * If number of MSIs is less than number of ports then Sharing Last
1558 * Message mode could be enforced. In this case assume that advantage
1559 * of multipe MSIs is negated and use single MSI mode instead.
1560 */
1561 if (n_ports > 1) {
1562 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1563 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1564 if (nvec > 0) {
1565 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1566 hpriv->get_irq_vector = ahci_get_irq_vector;
1567 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1568 return nvec;
1569 }
1570
1571 /*
1572 * Fallback to single MSI mode if the controller
1573 * enforced MRSM mode.
1574 */
1575 printk(KERN_INFO
1576 "ahci: MRSM is on, fallback to single MSI\n");
1577 pci_free_irq_vectors(pdev);
1578 }
1579 }
1580
1581 /*
1582 * If the host is not capable of supporting per-port vectors, fall
1583 * back to single MSI before finally attempting single MSI-X.
1584 */
1585 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1586 if (nvec == 1)
1587 return nvec;
1588 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1589 }
1590
1591 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1592 struct ahci_host_priv *hpriv)
1593 {
1594 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1595
1596
1597 /* Ignore processing for non mobile platforms */
1598 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1599 return;
1600
1601 /* user modified policy via module param */
1602 if (mobile_lpm_policy != -1) {
1603 policy = mobile_lpm_policy;
1604 goto update_policy;
1605 }
1606
1607 #ifdef CONFIG_ACPI
1608 if (policy > ATA_LPM_MED_POWER &&
1609 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1610 if (hpriv->cap & HOST_CAP_PART)
1611 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1612 else if (hpriv->cap & HOST_CAP_SSC)
1613 policy = ATA_LPM_MIN_POWER;
1614 }
1615 #endif
1616
1617 update_policy:
1618 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1619 ap->target_lpm_policy = policy;
1620 }
1621
1622 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1623 {
1624 unsigned int board_id = ent->driver_data;
1625 struct ata_port_info pi = ahci_port_info[board_id];
1626 const struct ata_port_info *ppi[] = { &pi, NULL };
1627 struct device *dev = &pdev->dev;
1628 struct ahci_host_priv *hpriv;
1629 struct ata_host *host;
1630 int n_ports, i, rc;
1631 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1632
1633 VPRINTK("ENTER\n");
1634
1635 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1636
1637 ata_print_version_once(&pdev->dev, DRV_VERSION);
1638
1639 /* The AHCI driver can only drive the SATA ports, the PATA driver
1640 can drive them all so if both drivers are selected make sure
1641 AHCI stays out of the way */
1642 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1643 return -ENODEV;
1644
1645 /* Apple BIOS on MCP89 prevents us using AHCI */
1646 if (is_mcp89_apple(pdev))
1647 ahci_mcp89_apple_enable(pdev);
1648
1649 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1650 * At the moment, we can only use the AHCI mode. Let the users know
1651 * that for SAS drives they're out of luck.
1652 */
1653 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1654 dev_info(&pdev->dev,
1655 "PDC42819 can only drive SATA devices with this driver\n");
1656
1657 /* Some devices use non-standard BARs */
1658 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1659 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1660 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1661 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1662 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1663 if (pdev->device == 0xa01c)
1664 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1665 if (pdev->device == 0xa084)
1666 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1667 }
1668
1669 /* acquire resources */
1670 rc = pcim_enable_device(pdev);
1671 if (rc)
1672 return rc;
1673
1674 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1675 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1676 u8 map;
1677
1678 /* ICH6s share the same PCI ID for both piix and ahci
1679 * modes. Enabling ahci mode while MAP indicates
1680 * combined mode is a bad idea. Yield to ata_piix.
1681 */
1682 pci_read_config_byte(pdev, ICH_MAP, &map);
1683 if (map & 0x3) {
1684 dev_info(&pdev->dev,
1685 "controller is in combined mode, can't enable AHCI mode\n");
1686 return -ENODEV;
1687 }
1688 }
1689
1690 /* AHCI controllers often implement SFF compatible interface.
1691 * Grab all PCI BARs just in case.
1692 */
1693 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1694 if (rc == -EBUSY)
1695 pcim_pin_device(pdev);
1696 if (rc)
1697 return rc;
1698
1699 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1700 if (!hpriv)
1701 return -ENOMEM;
1702 hpriv->flags |= (unsigned long)pi.private_data;
1703
1704 /* MCP65 revision A1 and A2 can't do MSI */
1705 if (board_id == board_ahci_mcp65 &&
1706 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1707 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1708
1709 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1710 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1711 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1712
1713 /* only some SB600s can do 64bit DMA */
1714 if (ahci_sb600_enable_64bit(pdev))
1715 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1716
1717 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1718
1719 /* detect remapped nvme devices */
1720 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1721
1722 /* must set flag prior to save config in order to take effect */
1723 if (ahci_broken_devslp(pdev))
1724 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1725
1726 #ifdef CONFIG_ARM64
1727 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1728 hpriv->irq_handler = ahci_thunderx_irq_handler;
1729 #endif
1730
1731 /* save initial config */
1732 ahci_pci_save_initial_config(pdev, hpriv);
1733
1734 /* prepare host */
1735 if (hpriv->cap & HOST_CAP_NCQ) {
1736 pi.flags |= ATA_FLAG_NCQ;
1737 /*
1738 * Auto-activate optimization is supposed to be
1739 * supported on all AHCI controllers indicating NCQ
1740 * capability, but it seems to be broken on some
1741 * chipsets including NVIDIAs.
1742 */
1743 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1744 pi.flags |= ATA_FLAG_FPDMA_AA;
1745
1746 /*
1747 * All AHCI controllers should be forward-compatible
1748 * with the new auxiliary field. This code should be
1749 * conditionalized if any buggy AHCI controllers are
1750 * encountered.
1751 */
1752 pi.flags |= ATA_FLAG_FPDMA_AUX;
1753 }
1754
1755 if (hpriv->cap & HOST_CAP_PMP)
1756 pi.flags |= ATA_FLAG_PMP;
1757
1758 ahci_set_em_messages(hpriv, &pi);
1759
1760 if (ahci_broken_system_poweroff(pdev)) {
1761 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1762 dev_info(&pdev->dev,
1763 "quirky BIOS, skipping spindown on poweroff\n");
1764 }
1765
1766 if (ahci_broken_lpm(pdev)) {
1767 pi.flags |= ATA_FLAG_NO_LPM;
1768 dev_warn(&pdev->dev,
1769 "BIOS update required for Link Power Management support\n");
1770 }
1771
1772 if (ahci_broken_suspend(pdev)) {
1773 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1774 dev_warn(&pdev->dev,
1775 "BIOS update required for suspend/resume\n");
1776 }
1777
1778 if (ahci_broken_online(pdev)) {
1779 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1780 dev_info(&pdev->dev,
1781 "online status unreliable, applying workaround\n");
1782 }
1783
1784
1785 /* Acer SA5-271 workaround modifies private_data */
1786 acer_sa5_271_workaround(hpriv, pdev);
1787
1788 /* CAP.NP sometimes indicate the index of the last enabled
1789 * port, at other times, that of the last possible port, so
1790 * determining the maximum port number requires looking at
1791 * both CAP.NP and port_map.
1792 */
1793 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1794
1795 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1796 if (!host)
1797 return -ENOMEM;
1798 host->private_data = hpriv;
1799
1800 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1801 /* legacy intx interrupts */
1802 pci_intx(pdev, 1);
1803 }
1804 hpriv->irq = pci_irq_vector(pdev, 0);
1805
1806 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1807 host->flags |= ATA_HOST_PARALLEL_SCAN;
1808 else
1809 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1810
1811 if (pi.flags & ATA_FLAG_EM)
1812 ahci_reset_em(host);
1813
1814 for (i = 0; i < host->n_ports; i++) {
1815 struct ata_port *ap = host->ports[i];
1816
1817 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1818 ata_port_pbar_desc(ap, ahci_pci_bar,
1819 0x100 + ap->port_no * 0x80, "port");
1820
1821 /* set enclosure management message type */
1822 if (ap->flags & ATA_FLAG_EM)
1823 ap->em_message_type = hpriv->em_msg_type;
1824
1825 ahci_update_initial_lpm_policy(ap, hpriv);
1826
1827 /* disabled/not-implemented port */
1828 if (!(hpriv->port_map & (1 << i)))
1829 ap->ops = &ata_dummy_port_ops;
1830 }
1831
1832 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1833 ahci_p5wdh_workaround(host);
1834
1835 /* apply gtf filter quirk */
1836 ahci_gtf_filter_workaround(host);
1837
1838 /* initialize adapter */
1839 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1840 if (rc)
1841 return rc;
1842
1843 rc = ahci_pci_reset_controller(host);
1844 if (rc)
1845 return rc;
1846
1847 ahci_pci_init_controller(host);
1848 ahci_pci_print_info(host);
1849
1850 pci_set_master(pdev);
1851
1852 rc = ahci_host_activate(host, &ahci_sht);
1853 if (rc)
1854 return rc;
1855
1856 pm_runtime_put_noidle(&pdev->dev);
1857 return 0;
1858 }
1859
1860 static void ahci_remove_one(struct pci_dev *pdev)
1861 {
1862 pm_runtime_get_noresume(&pdev->dev);
1863 ata_pci_remove_one(pdev);
1864 }
1865
1866 module_pci_driver(ahci_pci_driver);
1867
1868 MODULE_AUTHOR("Jeff Garzik");
1869 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1870 MODULE_LICENSE("GPL");
1871 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1872 MODULE_VERSION(DRV_VERSION);
Mirror of linux-2.6-arm at arm.linux.org.uk