drivers/gpio/gpio-gpio-mm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPIO driver for the Diamond Systems GPIO-MM
   4  * Copyright (C) 2016 William Breathitt Gray
   5  *
   6  * This driver supports the following Diamond Systems devices: GPIO-MM and
   7  * GPIO-MM-12.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/bitops.h>
  11 #include <linux/device.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/io.h>
  15 #include <linux/ioport.h>
  16 #include <linux/isa.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/spinlock.h>
  21
  22 #define GPIOMM_EXTENT 8
  23 #define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
  24
  25 static unsigned int base[MAX_NUM_GPIOMM];
  26 static unsigned int num_gpiomm;
  27 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
  28 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
  29
  30 /**
  31  * struct gpiomm_gpio - GPIO device private data structure
  32  * @chip:       instance of the gpio_chip
  33  * @io_state:   bit I/O state (whether bit is set to input or output)
  34  * @out_state:  output bits state
  35  * @control:    Control registers state
  36  * @lock:       synchronization lock to prevent I/O race conditions
  37  * @base:       base port address of the GPIO device
  38  */
  39 struct gpiomm_gpio {
  40         struct gpio_chip chip;
  41         unsigned char io_state[6];
  42         unsigned char out_state[6];
  43         unsigned char control[2];
  44         spinlock_t lock;
  45         unsigned int base;
  46 };
  47
  48 static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
  49         unsigned int offset)
  50 {
  51         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
  52         const unsigned int port = offset / 8;
  53         const unsigned int mask = BIT(offset % 8);
  54
  55         return !!(gpiommgpio->io_state[port] & mask);
  56 }
  57
  58 static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
  59         unsigned int offset)
  60 {
  61         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
  62         const unsigned int io_port = offset / 8;
  63         const unsigned int control_port = io_port / 3;
  64         const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
  65         unsigned long flags;
  66         unsigned int control;
  67
  68         spin_lock_irqsave(&gpiommgpio->lock, flags);
  69
  70         /* Check if configuring Port C */
  71         if (io_port == 2 || io_port == 5) {
  72                 /* Port C can be configured by nibble */
  73                 if (offset % 8 > 3) {
  74                         gpiommgpio->io_state[io_port] |= 0xF0;
  75                         gpiommgpio->control[control_port] |= BIT(3);
  76                 } else {
  77                         gpiommgpio->io_state[io_port] |= 0x0F;
  78                         gpiommgpio->control[control_port] |= BIT(0);
  79                 }
  80         } else {
  81                 gpiommgpio->io_state[io_port] |= 0xFF;
  82                 if (io_port == 0 || io_port == 3)
  83                         gpiommgpio->control[control_port] |= BIT(4);
  84                 else
  85                         gpiommgpio->control[control_port] |= BIT(1);
  86         }
  87
  88         control = BIT(7) | gpiommgpio->control[control_port];
  89         outb(control, control_addr);
  90
  91         spin_unlock_irqrestore(&gpiommgpio->lock, flags);
  92
  93         return 0;
  94 }
  95
  96 static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
  97         unsigned int offset, int value)
  98 {
  99         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
 100         const unsigned int io_port = offset / 8;
 101         const unsigned int control_port = io_port / 3;
 102         const unsigned int mask = BIT(offset % 8);
 103         const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
 104         const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
 105         unsigned long flags;
 106         unsigned int control;
 107
 108         spin_lock_irqsave(&gpiommgpio->lock, flags);
 109
 110         /* Check if configuring Port C */
 111         if (io_port == 2 || io_port == 5) {
 112                 /* Port C can be configured by nibble */
 113                 if (offset % 8 > 3) {
 114                         gpiommgpio->io_state[io_port] &= 0x0F;
 115                         gpiommgpio->control[control_port] &= ~BIT(3);
 116                 } else {
 117                         gpiommgpio->io_state[io_port] &= 0xF0;
 118                         gpiommgpio->control[control_port] &= ~BIT(0);
 119                 }
 120         } else {
 121                 gpiommgpio->io_state[io_port] &= 0x00;
 122                 if (io_port == 0 || io_port == 3)
 123                         gpiommgpio->control[control_port] &= ~BIT(4);
 124                 else
 125                         gpiommgpio->control[control_port] &= ~BIT(1);
 126         }
 127
 128         if (value)
 129                 gpiommgpio->out_state[io_port] |= mask;
 130         else
 131                 gpiommgpio->out_state[io_port] &= ~mask;
 132
 133         control = BIT(7) | gpiommgpio->control[control_port];
 134         outb(control, control_addr);
 135
 136         outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
 137
 138         spin_unlock_irqrestore(&gpiommgpio->lock, flags);
 139
 140         return 0;
 141 }
 142
 143 static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
 144 {
 145         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
 146         const unsigned int port = offset / 8;
 147         const unsigned int mask = BIT(offset % 8);
 148         const unsigned int in_port = (port > 2) ? port + 1 : port;
 149         unsigned long flags;
 150         unsigned int port_state;
 151
 152         spin_lock_irqsave(&gpiommgpio->lock, flags);
 153
 154         /* ensure that GPIO is set for input */
 155         if (!(gpiommgpio->io_state[port] & mask)) {
 156                 spin_unlock_irqrestore(&gpiommgpio->lock, flags);
 157                 return -EINVAL;
 158         }
 159
 160         port_state = inb(gpiommgpio->base + in_port);
 161
 162         spin_unlock_irqrestore(&gpiommgpio->lock, flags);
 163
 164         return !!(port_state & mask);
 165 }
 166
 167 static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
 168         unsigned long *bits)
 169 {
 170         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
 171         size_t i;
 172         static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
 173         const unsigned int gpio_reg_size = 8;
 174         unsigned int bits_offset;
 175         size_t word_index;
 176         unsigned int word_offset;
 177         unsigned long word_mask;
 178         const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
 179         unsigned long port_state;
 180
 181         /* clear bits array to a clean slate */
 182         bitmap_zero(bits, chip->ngpio);
 183
 184         /* get bits are evaluated a gpio port register at a time */
 185         for (i = 0; i < ARRAY_SIZE(ports); i++) {
 186                 /* gpio offset in bits array */
 187                 bits_offset = i * gpio_reg_size;
 188
 189                 /* word index for bits array */
 190                 word_index = BIT_WORD(bits_offset);
 191
 192                 /* gpio offset within current word of bits array */
 193                 word_offset = bits_offset % BITS_PER_LONG;
 194
 195                 /* mask of get bits for current gpio within current word */
 196                 word_mask = mask[word_index] & (port_mask << word_offset);
 197                 if (!word_mask) {
 198                         /* no get bits in this port so skip to next one */
 199                         continue;
 200                 }
 201
 202                 /* read bits from current gpio port */
 203                 port_state = inb(gpiommgpio->base + ports[i]);
 204
 205                 /* store acquired bits at respective bits array offset */
 206                 bits[word_index] |= (port_state << word_offset) & word_mask;
 207         }
 208
 209         return 0;
 210 }
 211
 212 static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
 213         int value)
 214 {
 215         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
 216         const unsigned int port = offset / 8;
 217         const unsigned int mask = BIT(offset % 8);
 218         const unsigned int out_port = (port > 2) ? port + 1 : port;
 219         unsigned long flags;
 220
 221         spin_lock_irqsave(&gpiommgpio->lock, flags);
 222
 223         if (value)
 224                 gpiommgpio->out_state[port] |= mask;
 225         else
 226                 gpiommgpio->out_state[port] &= ~mask;
 227
 228         outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
 229
 230         spin_unlock_irqrestore(&gpiommgpio->lock, flags);
 231 }
 232
 233 static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
 234         unsigned long *mask, unsigned long *bits)
 235 {
 236         struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
 237         unsigned int i;
 238         const unsigned int gpio_reg_size = 8;
 239         unsigned int port;
 240         unsigned int out_port;
 241         unsigned int bitmask;
 242         unsigned long flags;
 243
 244         /* set bits are evaluated a gpio register size at a time */
 245         for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
 246                 /* no more set bits in this mask word; skip to the next word */
 247                 if (!mask[BIT_WORD(i)]) {
 248                         i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
 249                         continue;
 250                 }
 251
 252                 port = i / gpio_reg_size;
 253                 out_port = (port > 2) ? port + 1 : port;
 254                 bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
 255
 256                 spin_lock_irqsave(&gpiommgpio->lock, flags);
 257
 258                 /* update output state data and set device gpio register */
 259                 gpiommgpio->out_state[port] &= ~mask[BIT_WORD(i)];
 260                 gpiommgpio->out_state[port] |= bitmask;
 261                 outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
 262
 263                 spin_unlock_irqrestore(&gpiommgpio->lock, flags);
 264
 265                 /* prepare for next gpio register set */
 266                 mask[BIT_WORD(i)] >>= gpio_reg_size;
 267                 bits[BIT_WORD(i)] >>= gpio_reg_size;
 268         }
 269 }
 270
 271 #define GPIOMM_NGPIO 48
 272 static const char *gpiomm_names[GPIOMM_NGPIO] = {
 273         "Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
 274         "Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
 275         "Port 1B4", "Port 1B5", "Port 1B6", "Port 1B7", "Port 1C0", "Port 1C1",
 276         "Port 1C2", "Port 1C3", "Port 1C4", "Port 1C5", "Port 1C6", "Port 1C7",
 277         "Port 2A0", "Port 2A1", "Port 2A2", "Port 2A3", "Port 2A4", "Port 2A5",
 278         "Port 2A6", "Port 2A7", "Port 2B0", "Port 2B1", "Port 2B2", "Port 2B3",
 279         "Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
 280         "Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
 281 };
 282
 283 static int gpiomm_probe(struct device *dev, unsigned int id)
 284 {
 285         struct gpiomm_gpio *gpiommgpio;
 286         const char *const name = dev_name(dev);
 287         int err;
 288
 289         gpiommgpio = devm_kzalloc(dev, sizeof(*gpiommgpio), GFP_KERNEL);
 290         if (!gpiommgpio)
 291                 return -ENOMEM;
 292
 293         if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) {
 294                 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
 295                         base[id], base[id] + GPIOMM_EXTENT);
 296                 return -EBUSY;
 297         }
 298
 299         gpiommgpio->chip.label = name;
 300         gpiommgpio->chip.parent = dev;
 301         gpiommgpio->chip.owner = THIS_MODULE;
 302         gpiommgpio->chip.base = -1;
 303         gpiommgpio->chip.ngpio = GPIOMM_NGPIO;
 304         gpiommgpio->chip.names = gpiomm_names;
 305         gpiommgpio->chip.get_direction = gpiomm_gpio_get_direction;
 306         gpiommgpio->chip.direction_input = gpiomm_gpio_direction_input;
 307         gpiommgpio->chip.direction_output = gpiomm_gpio_direction_output;
 308         gpiommgpio->chip.get = gpiomm_gpio_get;
 309         gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple;
 310         gpiommgpio->chip.set = gpiomm_gpio_set;
 311         gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
 312         gpiommgpio->base = base[id];
 313
 314         spin_lock_init(&gpiommgpio->lock);
 315
 316         err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
 317         if (err) {
 318                 dev_err(dev, "GPIO registering failed (%d)\n", err);
 319                 return err;
 320         }
 321
 322         /* initialize all GPIO as output */
 323         outb(0x80, base[id] + 3);
 324         outb(0x00, base[id]);
 325         outb(0x00, base[id] + 1);
 326         outb(0x00, base[id] + 2);
 327         outb(0x80, base[id] + 7);
 328         outb(0x00, base[id] + 4);
 329         outb(0x00, base[id] + 5);
 330         outb(0x00, base[id] + 6);
 331
 332         return 0;
 333 }
 334
 335 static struct isa_driver gpiomm_driver = {
 336         .probe = gpiomm_probe,
 337         .driver = {
 338                 .name = "gpio-mm"
 339         },
 340 };
 341
 342 module_isa_driver(gpiomm_driver, num_gpiomm);
 343
 344 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
 345 MODULE_DESCRIPTION("Diamond Systems GPIO-MM GPIO driver");
 346 MODULE_LICENSE("GPL v2");