eeepc-laptop: Register as a pci-hotplug device
[linux-2.6/linux-acpi-2.6.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c
blob77f90b35635681f818e448645fcfa9a174dd4e67
1 /*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
4 * Author: Andy Fleming <afleming@freescale.com>
6 * Based on 83xx/mpc8360e_pb.c by:
7 * Li Yang <LeoLi@freescale.com>
8 * Yin Olivia <Hong-hua.Yin@freescale.com>
10 * Description:
11 * MPC85xx MDS board specific routines.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35 #include <linux/phy.h>
36 #include <linux/lmb.h>
38 #include <asm/system.h>
39 #include <asm/atomic.h>
40 #include <asm/time.h>
41 #include <asm/io.h>
42 #include <asm/machdep.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/irq.h>
45 #include <mm/mmu_decl.h>
46 #include <asm/prom.h>
47 #include <asm/udbg.h>
48 #include <sysdev/fsl_soc.h>
49 #include <sysdev/fsl_pci.h>
50 #include <asm/qe.h>
51 #include <asm/qe_ic.h>
52 #include <asm/mpic.h>
53 #include <asm/swiotlb.h>
55 #undef DEBUG
56 #ifdef DEBUG
57 #define DBG(fmt...) udbg_printf(fmt)
58 #else
59 #define DBG(fmt...)
60 #endif
62 #define MV88E1111_SCR 0x10
63 #define MV88E1111_SCR_125CLK 0x0010
64 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
66 int scr;
67 int err;
69 /* Workaround for the 125 CLK Toggle */
70 scr = phy_read(phydev, MV88E1111_SCR);
72 if (scr < 0)
73 return scr;
75 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
77 if (err)
78 return err;
80 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
82 if (err)
83 return err;
85 scr = phy_read(phydev, MV88E1111_SCR);
87 if (scr < 0)
88 return err;
90 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
92 return err;
95 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
97 int temp;
98 int err;
100 /* Errata */
101 err = phy_write(phydev,29, 0x0006);
103 if (err)
104 return err;
106 temp = phy_read(phydev, 30);
108 if (temp < 0)
109 return temp;
111 temp = (temp & (~0x8000)) | 0x4000;
112 err = phy_write(phydev,30, temp);
114 if (err)
115 return err;
117 err = phy_write(phydev,29, 0x000a);
119 if (err)
120 return err;
122 temp = phy_read(phydev, 30);
124 if (temp < 0)
125 return temp;
127 temp = phy_read(phydev, 30);
129 if (temp < 0)
130 return temp;
132 temp &= ~0x0020;
134 err = phy_write(phydev,30,temp);
136 if (err)
137 return err;
139 /* Disable automatic MDI/MDIX selection */
140 temp = phy_read(phydev, 16);
142 if (temp < 0)
143 return temp;
145 temp &= ~0x0060;
146 err = phy_write(phydev,16,temp);
148 return err;
151 /* ************************************************************************
153 * Setup the architecture
156 static void __init mpc85xx_mds_setup_arch(void)
158 struct device_node *np;
159 static u8 __iomem *bcsr_regs = NULL;
160 #ifdef CONFIG_PCI
161 struct pci_controller *hose;
162 #endif
163 dma_addr_t max = 0xffffffff;
165 if (ppc_md.progress)
166 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
168 /* Map BCSR area */
169 np = of_find_node_by_name(NULL, "bcsr");
170 if (np != NULL) {
171 struct resource res;
173 of_address_to_resource(np, 0, &res);
174 bcsr_regs = ioremap(res.start, res.end - res.start +1);
175 of_node_put(np);
178 #ifdef CONFIG_PCI
179 for_each_node_by_type(np, "pci") {
180 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
181 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
182 struct resource rsrc;
183 of_address_to_resource(np, 0, &rsrc);
184 if ((rsrc.start & 0xfffff) == 0x8000)
185 fsl_add_bridge(np, 1);
186 else
187 fsl_add_bridge(np, 0);
189 hose = pci_find_hose_for_OF_device(np);
190 max = min(max, hose->dma_window_base_cur +
191 hose->dma_window_size);
194 #endif
196 #ifdef CONFIG_QUICC_ENGINE
197 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
198 if (!np) {
199 np = of_find_node_by_name(NULL, "qe");
200 if (!np)
201 return;
204 qe_reset();
205 of_node_put(np);
207 np = of_find_node_by_name(NULL, "par_io");
208 if (np) {
209 struct device_node *ucc;
211 par_io_init(np);
212 of_node_put(np);
214 for_each_node_by_name(ucc, "ucc")
215 par_io_of_config(ucc);
218 if (bcsr_regs) {
219 if (machine_is(mpc8568_mds)) {
220 #define BCSR_UCC1_GETH_EN (0x1 << 7)
221 #define BCSR_UCC2_GETH_EN (0x1 << 7)
222 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
223 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
225 /* Turn off UCC1 & UCC2 */
226 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
227 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
229 /* Mode is RGMII, all bits clear */
230 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
231 BCSR_UCC2_MODE_MSK);
233 /* Turn UCC1 & UCC2 on */
234 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
235 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
237 iounmap(bcsr_regs);
239 #endif /* CONFIG_QUICC_ENGINE */
241 #ifdef CONFIG_SWIOTLB
242 if (lmb_end_of_DRAM() > max) {
243 ppc_swiotlb_enable = 1;
244 set_pci_dma_ops(&swiotlb_pci_dma_ops);
246 #endif
250 static int __init board_fixups(void)
252 char phy_id[20];
253 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
254 struct device_node *mdio;
255 struct resource res;
256 int i;
258 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
259 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
261 of_address_to_resource(mdio, 0, &res);
262 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
263 (unsigned long long)res.start, 1);
265 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
266 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
268 /* Register a workaround for errata */
269 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
270 (unsigned long long)res.start, 7);
271 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
273 of_node_put(mdio);
276 return 0;
278 machine_arch_initcall(mpc8568_mds, board_fixups);
279 machine_arch_initcall(mpc8569_mds, board_fixups);
281 static struct of_device_id mpc85xx_ids[] = {
282 { .type = "soc", },
283 { .compatible = "soc", },
284 { .compatible = "simple-bus", },
285 { .type = "qe", },
286 { .compatible = "fsl,qe", },
287 { .compatible = "gianfar", },
291 static int __init mpc85xx_publish_devices(void)
293 /* Publish the QE devices */
294 of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
296 return 0;
298 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
299 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
301 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
302 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
304 static void __init mpc85xx_mds_pic_init(void)
306 struct mpic *mpic;
307 struct resource r;
308 struct device_node *np = NULL;
310 np = of_find_node_by_type(NULL, "open-pic");
311 if (!np)
312 return;
314 if (of_address_to_resource(np, 0, &r)) {
315 printk(KERN_ERR "Failed to map mpic register space\n");
316 of_node_put(np);
317 return;
320 mpic = mpic_alloc(np, r.start,
321 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
322 0, 256, " OpenPIC ");
323 BUG_ON(mpic == NULL);
324 of_node_put(np);
326 mpic_init(mpic);
328 #ifdef CONFIG_QUICC_ENGINE
329 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
330 if (!np) {
331 np = of_find_node_by_type(NULL, "qeic");
332 if (!np)
333 return;
335 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
336 of_node_put(np);
337 #endif /* CONFIG_QUICC_ENGINE */
340 static int __init mpc85xx_mds_probe(void)
342 unsigned long root = of_get_flat_dt_root();
344 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
347 define_machine(mpc8568_mds) {
348 .name = "MPC8568 MDS",
349 .probe = mpc85xx_mds_probe,
350 .setup_arch = mpc85xx_mds_setup_arch,
351 .init_IRQ = mpc85xx_mds_pic_init,
352 .get_irq = mpic_get_irq,
353 .restart = fsl_rstcr_restart,
354 .calibrate_decr = generic_calibrate_decr,
355 .progress = udbg_progress,
356 #ifdef CONFIG_PCI
357 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
358 #endif
361 static int __init mpc8569_mds_probe(void)
363 unsigned long root = of_get_flat_dt_root();
365 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
368 define_machine(mpc8569_mds) {
369 .name = "MPC8569 MDS",
370 .probe = mpc8569_mds_probe,
371 .setup_arch = mpc85xx_mds_setup_arch,
372 .init_IRQ = mpc85xx_mds_pic_init,
373 .get_irq = mpic_get_irq,
374 .restart = fsl_rstcr_restart,
375 .calibrate_decr = generic_calibrate_decr,
376 .progress = udbg_progress,
377 #ifdef CONFIG_PCI
378 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
379 #endif