arch/powerpc/sysdev/tsi108_pci.c

   1 /*
   2  * Common routines for Tundra Semiconductor TSI108 host bridge.
   3  *
   4  * 2004-2005 (c) Tundra Semiconductor Corp.
   5  * Author: Alex Bounine (alexandreb@tundra.com)
   6  * Author: Roy Zang (tie-fei.zang@freescale.com)
   7  *         Add pci interrupt router host
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the Free
  11  * Software Foundation; either version 2 of the License, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc., 59
  21  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/pci.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30
  31 #include <asm/byteorder.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/machdep.h>
  36 #include <asm/pci-bridge.h>
  37 #include <asm/tsi108.h>
  38 #include <asm/tsi108_pci.h>
  39 #include <asm/tsi108_irq.h>
  40 #include <asm/prom.h>
  41
  42 #undef DEBUG
  43 #ifdef DEBUG
  44 #define DBG(x...) printk(x)
  45 #else
  46 #define DBG(x...)
  47 #endif
  48
  49 #define tsi_mk_config_addr(bus, devfunc, offset) \
  50         ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
  51
  52 u32 tsi108_pci_cfg_base;
  53 static u32 tsi108_pci_cfg_phys;
  54 u32 tsi108_csr_vir_base;
  55 static struct irq_host *pci_irq_host;
  56
  57 extern u32 get_vir_csrbase(void);
  58 extern u32 tsi108_read_reg(u32 reg_offset);
  59 extern void tsi108_write_reg(u32 reg_offset, u32 val);
  60
  61 int
  62 tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
  63                            int offset, int len, u32 val)
  64 {
  65         volatile unsigned char *cfg_addr;
  66         struct pci_controller *hose = pci_bus_to_host(bus);
  67
  68         if (ppc_md.pci_exclude_device)
  69                 if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
  70                         return PCIBIOS_DEVICE_NOT_FOUND;
  71
  72         cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
  73                                                         devfunc, offset) |
  74                                                         (offset & 0x03));
  75
  76 #ifdef DEBUG
  77         printk("PCI CFG write : ");
  78         printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
  79         printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
  80         printk("data = 0x%08x\n", val);
  81 #endif
  82
  83         switch (len) {
  84         case 1:
  85                 out_8((u8 *) cfg_addr, val);
  86                 break;
  87         case 2:
  88                 out_le16((u16 *) cfg_addr, val);
  89                 break;
  90         default:
  91                 out_le32((u32 *) cfg_addr, val);
  92                 break;
  93         }
  94
  95         return PCIBIOS_SUCCESSFUL;
  96 }
  97
  98 void tsi108_clear_pci_error(u32 pci_cfg_base)
  99 {
 100         u32 err_stat, err_addr, pci_stat;
 101
 102         /*
 103          * Quietly clear PB and PCI error flags set as result
 104          * of PCI/X configuration read requests.
 105          */
 106
 107         /* Read PB Error Log Registers */
 108
 109         err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
 110         err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
 111
 112         if (err_stat & TSI108_PB_ERRCS_ES) {
 113                 /* Clear error flag */
 114                 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
 115                                  TSI108_PB_ERRCS_ES);
 116
 117                 /* Clear read error reported in PB_ISR */
 118                 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
 119                                  TSI108_PB_ISR_PBS_RD_ERR);
 120
 121                 /* Clear PCI/X bus cfg errors if applicable */
 122                 if ((err_addr & 0xFF000000) == pci_cfg_base) {
 123                         pci_stat =
 124                             tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
 125                         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
 126                                          pci_stat);
 127                 }
 128         }
 129
 130         return;
 131 }
 132
 133 #define __tsi108_read_pci_config(x, addr, op)           \
 134         __asm__ __volatile__(                           \
 135                 "       "op" %0,0,%1\n"         \
 136                 "1:     eieio\n"                        \
 137                 "2:\n"                                  \
 138                 ".section .fixup,\"ax\"\n"              \
 139                 "3:     li %0,-1\n"                     \
 140                 "       b 2b\n"                         \
 141                 ".section __ex_table,\"a\"\n"           \
 142                 "       .align 2\n"                     \
 143                 "       .long 1b,3b\n"                  \
 144                 ".text"                                 \
 145                 : "=r"(x) : "r"(addr))
 146
 147 int
 148 tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
 149                           int len, u32 * val)
 150 {
 151         volatile unsigned char *cfg_addr;
 152         struct pci_controller *hose = pci_bus_to_host(bus);
 153         u32 temp;
 154
 155         if (ppc_md.pci_exclude_device)
 156                 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
 157                         return PCIBIOS_DEVICE_NOT_FOUND;
 158
 159         cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
 160                                                         devfn,
 161                                                         offset) | (offset &
 162                                                                    0x03));
 163
 164         switch (len) {
 165         case 1:
 166                 __tsi108_read_pci_config(temp, cfg_addr, "lbzx");
 167                 break;
 168         case 2:
 169                 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
 170                 break;
 171         default:
 172                 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
 173                 break;
 174         }
 175
 176         *val = temp;
 177
 178 #ifdef DEBUG
 179         if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
 180                 printk("PCI CFG read : ");
 181                 printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
 182                 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
 183                 printk("data = 0x%x\n", *val);
 184         }
 185 #endif
 186         return PCIBIOS_SUCCESSFUL;
 187 }
 188
 189 void tsi108_clear_pci_cfg_error(void)
 190 {
 191         tsi108_clear_pci_error(tsi108_pci_cfg_phys);
 192 }
 193
 194 static struct pci_ops tsi108_direct_pci_ops = {
 195         .read = tsi108_direct_read_config,
 196         .write = tsi108_direct_write_config,
 197 };
 198
 199 int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
 200 {
 201         int len;
 202         struct pci_controller *hose;
 203         struct resource rsrc;
 204         const int *bus_range;
 205         int has_address = 0;
 206
 207         /* PCI Config mapping */
 208         tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
 209         tsi108_pci_cfg_phys = cfg_phys;
 210         DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
 211             tsi108_pci_cfg_base);
 212
 213         /* Fetch host bridge registers address */
 214         has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
 215
 216         /* Get bus range if any */
 217         bus_range = of_get_property(dev, "bus-range", &len);
 218         if (bus_range == NULL || len < 2 * sizeof(int)) {
 219                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 220                        " bus 0\n", dev->full_name);
 221         }
 222
 223         hose = pcibios_alloc_controller(dev);
 224
 225         if (!hose) {
 226                 printk("PCI Host bridge init failed\n");
 227                 return -ENOMEM;
 228         }
 229
 230         hose->first_busno = bus_range ? bus_range[0] : 0;
 231         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 232
 233         (hose)->ops = &tsi108_direct_pci_ops;
 234
 235         printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
 236                "Firmware bus number: %d->%d\n",
 237                rsrc.start, hose->first_busno, hose->last_busno);
 238
 239         /* Interpret the "ranges" property */
 240         /* This also maps the I/O region and sets isa_io/mem_base */
 241         pci_process_bridge_OF_ranges(hose, dev, primary);
 242         return 0;
 243 }
 244
 245 /*
 246  * Low level utility functions
 247  */
 248
 249 static void tsi108_pci_int_mask(u_int irq)
 250 {
 251         u_int irp_cfg;
 252         int int_line = (irq - IRQ_PCI_INTAD_BASE);
 253
 254         irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
 255         mb();
 256         irp_cfg |= (1 << int_line);     /* INTx_DIR = output */
 257         irp_cfg &= ~(3 << (8 + (int_line * 2)));        /* INTx_TYPE = unused */
 258         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
 259         mb();
 260         irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
 261 }
 262
 263 static void tsi108_pci_int_unmask(u_int irq)
 264 {
 265         u_int irp_cfg;
 266         int int_line = (irq - IRQ_PCI_INTAD_BASE);
 267
 268         irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
 269         mb();
 270         irp_cfg &= ~(1 << int_line);
 271         irp_cfg |= (3 << (8 + (int_line * 2)));
 272         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
 273         mb();
 274 }
 275
 276 static void init_pci_source(void)
 277 {
 278         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
 279                         0x0000ff00);
 280         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
 281                         TSI108_PCI_IRP_ENABLE_P_INT);
 282         mb();
 283 }
 284
 285 static inline unsigned int get_pci_source(void)
 286 {
 287         u_int temp = 0;
 288         int irq = -1;
 289         int i;
 290         u_int pci_irp_stat;
 291         static int mask = 0;
 292
 293         /* Read PCI/X block interrupt status register */
 294         pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
 295         mb();
 296
 297         if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
 298                 /* Process Interrupt from PCI bus INTA# - INTD# lines */
 299                 temp =
 300                     tsi108_read_reg(TSI108_PCI_OFFSET +
 301                                     TSI108_PCI_IRP_INTAD) & 0xf;
 302                 mb();
 303                 for (i = 0; i < 4; i++, mask++) {
 304                         if (temp & (1 << mask % 4)) {
 305                                 irq = IRQ_PCI_INTA + mask % 4;
 306                                 mask++;
 307                                 break;
 308                         }
 309                 }
 310
 311                 /* Disable interrupts from PCI block */
 312                 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
 313                 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
 314                                 temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
 315                 mb();
 316                 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
 317                 mb();
 318         }
 319 #ifdef DEBUG
 320         else {
 321                 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
 322                 pci_irp_stat =
 323                     tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
 324                 temp =
 325                     tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
 326                 mb();
 327                 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
 328                 temp =
 329                     tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
 330                 mb();
 331                 printk("cfg_ctl=0x%08x ", temp);
 332                 temp =
 333                     tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
 334                 mb();
 335                 printk("irp_enable=0x%08x\n", temp);
 336         }
 337 #endif  /* end of DEBUG */
 338
 339         return irq;
 340 }
 341
 342
 343 /*
 344  * Linux descriptor level callbacks
 345  */
 346
 347 static void tsi108_pci_irq_enable(u_int irq)
 348 {
 349         tsi108_pci_int_unmask(irq);
 350 }
 351
 352 static void tsi108_pci_irq_disable(u_int irq)
 353 {
 354         tsi108_pci_int_mask(irq);
 355 }
 356
 357 static void tsi108_pci_irq_ack(u_int irq)
 358 {
 359         tsi108_pci_int_mask(irq);
 360 }
 361
 362 static void tsi108_pci_irq_end(u_int irq)
 363 {
 364         tsi108_pci_int_unmask(irq);
 365
 366         /* Enable interrupts from PCI block */
 367         tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
 368                          tsi108_read_reg(TSI108_PCI_OFFSET +
 369                                          TSI108_PCI_IRP_ENABLE) |
 370                          TSI108_PCI_IRP_ENABLE_P_INT);
 371         mb();
 372 }
 373
 374 /*
 375  * Interrupt controller descriptor for cascaded PCI interrupt controller.
 376  */
 377
 378 static struct irq_chip tsi108_pci_irq = {
 379         .typename = "tsi108_PCI_int",
 380         .mask = tsi108_pci_irq_disable,
 381         .ack = tsi108_pci_irq_ack,
 382         .end = tsi108_pci_irq_end,
 383         .unmask = tsi108_pci_irq_enable,
 384 };
 385
 386 static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
 387                             u32 *intspec, unsigned int intsize,
 388                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 389 {
 390         *out_hwirq = intspec[0];
 391         *out_flags = IRQ_TYPE_LEVEL_HIGH;
 392         return 0;
 393 }
 394
 395 static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
 396                           irq_hw_number_t hw)
 397 {       unsigned int irq;
 398         DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
 399         if ((virq >= 1) && (virq <= 4)){
 400                 irq = virq + IRQ_PCI_INTAD_BASE - 1;
 401                 get_irq_desc(irq)->status |= IRQ_LEVEL;
 402                 set_irq_chip(irq, &tsi108_pci_irq);
 403         }
 404         return 0;
 405 }
 406
 407 static struct irq_host_ops pci_irq_host_ops = {
 408         .map = pci_irq_host_map,
 409         .xlate = pci_irq_host_xlate,
 410 };
 411
 412 /*
 413  * Exported functions
 414  */
 415
 416 /*
 417  * The Tsi108 PCI interrupts initialization routine.
 418  *
 419  * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
 420  * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
 421  * PCI block has to be treated as a cascaded interrupt controller connected
 422  * to the MPIC.
 423  */
 424
 425 void __init tsi108_pci_int_init(struct device_node *node)
 426 {
 427         DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
 428
 429         pci_irq_host = irq_alloc_host(node, IRQ_HOST_MAP_LEGACY,
 430                                       0, &pci_irq_host_ops, 0);
 431         if (pci_irq_host == NULL) {
 432                 printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n");
 433                 return;
 434         }
 435
 436         init_pci_source();
 437 }
 438
 439 void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
 440 {
 441         unsigned int cascade_irq = get_pci_source();
 442         if (cascade_irq != NO_IRQ)
 443                 generic_handle_irq(cascade_irq);
 444         desc->chip->eoi(irq);
 445 }