drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  45 #else                           /* PAGE_SHIFT > 20 */
  46 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  47 #endif
  48
  49 #define edac_printk(level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix ": " fmt, ##arg)
  51
  52 #define edac_printk_verbose(level, prefix, fmt, arg...) \
  53         printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt,     \
  54                __FILE__, __LINE__, ##arg)
  55
  56 #define edac_mc_printk(mci, level, fmt, arg...) \
  57         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  60         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  61
  62 /* edac_device printk */
  63 #define edac_device_printk(ctl, level, fmt, arg...) \
  64         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  65
  66 /* edac_pci printk */
  67 #define edac_pci_printk(ctl, level, fmt, arg...) \
  68         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  69
  70 /* prefixes for edac_printk() and edac_mc_printk() */
  71 #define EDAC_MC "MC"
  72 #define EDAC_PCI "PCI"
  73 #define EDAC_DEBUG "DEBUG"
  74
  75 #ifdef CONFIG_EDAC_DEBUG
  76 extern int edac_debug_level;
  77
  78 #ifndef CONFIG_EDAC_DEBUG_VERBOSE
  79 #define edac_debug_printk(level, fmt, arg...)                           \
  80         do {                                                            \
  81                 if (level <= edac_debug_level)                          \
  82                         edac_printk(KERN_DEBUG, EDAC_DEBUG,             \
  83                                     "%s: " fmt, __func__, ##arg);       \
  84         } while (0)
  85 #else  /* CONFIG_EDAC_DEBUG_VERBOSE */
  86 #define edac_debug_printk(level, fmt, arg...)                            \
  87         do {                                                             \
  88                 if (level <= edac_debug_level)                           \
  89                         edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
  90                                             ##arg);                     \
  91         } while (0)
  92 #endif
  93
  94 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  95 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  96 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  97 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  98 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  99
 100 #else                           /* !CONFIG_EDAC_DEBUG */
 101
 102 #define debugf0( ... )
 103 #define debugf1( ... )
 104 #define debugf2( ... )
 105 #define debugf3( ... )
 106 #define debugf4( ... )
 107
 108 #endif                          /* !CONFIG_EDAC_DEBUG */
 109
 110 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 111         PCI_DEVICE_ID_ ## vend ## _ ## dev
 112
 113 #define edac_dev_name(dev) (dev)->dev_name
 114
 115 /* memory devices */
 116 enum dev_type {
 117         DEV_UNKNOWN = 0,
 118         DEV_X1,
 119         DEV_X2,
 120         DEV_X4,
 121         DEV_X8,
 122         DEV_X16,
 123         DEV_X32,                /* Do these parts exist? */
 124         DEV_X64                 /* Do these parts exist? */
 125 };
 126
 127 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 128 #define DEV_FLAG_X1             BIT(DEV_X1)
 129 #define DEV_FLAG_X2             BIT(DEV_X2)
 130 #define DEV_FLAG_X4             BIT(DEV_X4)
 131 #define DEV_FLAG_X8             BIT(DEV_X8)
 132 #define DEV_FLAG_X16            BIT(DEV_X16)
 133 #define DEV_FLAG_X32            BIT(DEV_X32)
 134 #define DEV_FLAG_X64            BIT(DEV_X64)
 135
 136 /* memory types */
 137 enum mem_type {
 138         MEM_EMPTY = 0,          /* Empty csrow */
 139         MEM_RESERVED,           /* Reserved csrow type */
 140         MEM_UNKNOWN,            /* Unknown csrow type */
 141         MEM_FPM,                /* Fast page mode */
 142         MEM_EDO,                /* Extended data out */
 143         MEM_BEDO,               /* Burst Extended data out */
 144         MEM_SDR,                /* Single data rate SDRAM */
 145         MEM_RDR,                /* Registered single data rate SDRAM */
 146         MEM_DDR,                /* Double data rate SDRAM */
 147         MEM_RDDR,               /* Registered Double data rate SDRAM */
 148         MEM_RMBS,               /* Rambus DRAM */
 149         MEM_DDR2,               /* DDR2 RAM */
 150         MEM_FB_DDR2,            /* fully buffered DDR2 */
 151         MEM_RDDR2,              /* Registered DDR2 RAM */
 152         MEM_XDR,                /* Rambus XDR */
 153         MEM_DDR3,               /* DDR3 RAM */
 154         MEM_RDDR3,              /* Registered DDR3 RAM */
 155 };
 156
 157 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 158 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 159 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 160 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 161 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 162 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 163 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 164 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 165 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 166 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 167 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 168 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 169 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 170 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 171 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 172 #define MEM_FLAG_DDR3            BIT(MEM_DDR3)
 173 #define MEM_FLAG_RDDR3           BIT(MEM_RDDR3)
 174
 175 /* chipset Error Detection and Correction capabilities and mode */
 176 enum edac_type {
 177         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 178         EDAC_NONE,              /* Doesnt support ECC */
 179         EDAC_RESERVED,          /* Reserved ECC type */
 180         EDAC_PARITY,            /* Detects parity errors */
 181         EDAC_EC,                /* Error Checking - no correction */
 182         EDAC_SECDED,            /* Single bit error correction, Double detection */
 183         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 184         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 185         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 186         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 187 };
 188
 189 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 190 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 191 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 192 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 193 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 194 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 195 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 196 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 197 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 198
 199 /* scrubbing capabilities */
 200 enum scrub_type {
 201         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 202         SCRUB_NONE,             /* No scrubber */
 203         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 204         SCRUB_SW_SRC,           /* Software scrub only errors */
 205         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 206         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 207         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 208         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 209         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 210         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 211 };
 212
 213 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 214 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 215 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 216 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 217 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 218 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 219 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 220 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 221
 222 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 223
 224 /* EDAC internal operation states */
 225 #define OP_ALLOC                0x100
 226 #define OP_RUNNING_POLL         0x201
 227 #define OP_RUNNING_INTERRUPT    0x202
 228 #define OP_RUNNING_POLL_INTR    0x203
 229 #define OP_OFFLINE              0x300
 230
 231 /*
 232  * There are several things to be aware of that aren't at all obvious:
 233  *
 234  *
 235  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 236  *
 237  * These are some of the many terms that are thrown about that don't always
 238  * mean what people think they mean (Inconceivable!).  In the interest of
 239  * creating a common ground for discussion, terms and their definitions
 240  * will be established.
 241  *
 242  * Memory devices:      The individual chip on a memory stick.  These devices
 243  *                      commonly output 4 and 8 bits each.  Grouping several
 244  *                      of these in parallel provides 64 bits which is common
 245  *                      for a memory stick.
 246  *
 247  * Memory Stick:        A printed circuit board that agregates multiple
 248  *                      memory devices in parallel.  This is the atomic
 249  *                      memory component that is purchaseable by Joe consumer
 250  *                      and loaded into a memory socket.
 251  *
 252  * Socket:              A physical connector on the motherboard that accepts
 253  *                      a single memory stick.
 254  *
 255  * Channel:             Set of memory devices on a memory stick that must be
 256  *                      grouped in parallel with one or more additional
 257  *                      channels from other memory sticks.  This parallel
 258  *                      grouping of the output from multiple channels are
 259  *                      necessary for the smallest granularity of memory access.
 260  *                      Some memory controllers are capable of single channel -
 261  *                      which means that memory sticks can be loaded
 262  *                      individually.  Other memory controllers are only
 263  *                      capable of dual channel - which means that memory
 264  *                      sticks must be loaded as pairs (see "socket set").
 265  *
 266  * Chip-select row:     All of the memory devices that are selected together.
 267  *                      for a single, minimum grain of memory access.
 268  *                      This selects all of the parallel memory devices across
 269  *                      all of the parallel channels.  Common chip-select rows
 270  *                      for single channel are 64 bits, for dual channel 128
 271  *                      bits.
 272  *
 273  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 274  *                      Motherboards commonly drive two chip-select pins to
 275  *                      a memory stick. A single-ranked stick, will occupy
 276  *                      only one of those rows. The other will be unused.
 277  *
 278  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 279  *                      access different sets of memory devices.  The two
 280  *                      rows cannot be accessed concurrently.
 281  *
 282  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 283  *                      A double-sided stick has two chip-select rows which
 284  *                      access different sets of memory devices.  The two
 285  *                      rows cannot be accessed concurrently.  "Double-sided"
 286  *                      is irrespective of the memory devices being mounted
 287  *                      on both sides of the memory stick.
 288  *
 289  * Socket set:          All of the memory sticks that are required for for
 290  *                      a single memory access or all of the memory sticks
 291  *                      spanned by a chip-select row.  A single socket set
 292  *                      has two chip-select rows and if double-sided sticks
 293  *                      are used these will occupy those chip-select rows.
 294  *
 295  * Bank:                This term is avoided because it is unclear when
 296  *                      needing to distinguish between chip-select rows and
 297  *                      socket sets.
 298  *
 299  * Controller pages:
 300  *
 301  * Physical pages:
 302  *
 303  * Virtual pages:
 304  *
 305  *
 306  * STRUCTURE ORGANIZATION AND CHOICES
 307  *
 308  *
 309  *
 310  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 311  */
 312
 313 struct channel_info {
 314         int chan_idx;           /* channel index */
 315         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 316         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 317         struct csrow_info *csrow;       /* the parent */
 318 };
 319
 320 struct csrow_info {
 321         unsigned long first_page;       /* first page number in dimm */
 322         unsigned long last_page;        /* last page number in dimm */
 323         unsigned long page_mask;        /* used for interleaving -
 324                                          * 0UL for non intlv
 325                                          */
 326         u32 nr_pages;           /* number of pages in csrow */
 327         u32 grain;              /* granularity of reported error in bytes */
 328         int csrow_idx;          /* the chip-select row */
 329         enum dev_type dtype;    /* memory device type */
 330         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 331         u32 ce_count;           /* Correctable Errors for this csrow */
 332         enum mem_type mtype;    /* memory csrow type */
 333         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 334         struct mem_ctl_info *mci;       /* the parent */
 335
 336         struct kobject kobj;    /* sysfs kobject for this csrow */
 337
 338         /* channel information for this csrow */
 339         u32 nr_channels;
 340         struct channel_info *channels;
 341 };
 342
 343 /* mcidev_sysfs_attribute structure
 344  *      used for driver sysfs attributes and in mem_ctl_info
 345  *      sysfs top level entries
 346  */
 347 struct mcidev_sysfs_attribute {
 348         struct attribute attr;
 349         ssize_t (*show)(struct mem_ctl_info *,char *);
 350         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 351 };
 352
 353 /* MEMORY controller information structure
 354  */
 355 struct mem_ctl_info {
 356         struct list_head link;  /* for global list of mem_ctl_info structs */
 357
 358         struct module *owner;   /* Module owner of this control struct */
 359
 360         unsigned long mtype_cap;        /* memory types supported by mc */
 361         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 362         unsigned long edac_cap; /* configuration capabilities - this is
 363                                  * closely related to edac_ctl_cap.  The
 364                                  * difference is that the controller may be
 365                                  * capable of s4ecd4ed which would be listed
 366                                  * in edac_ctl_cap, but if channels aren't
 367                                  * capable of s4ecd4ed then the edac_cap would
 368                                  * not have that capability.
 369                                  */
 370         unsigned long scrub_cap;        /* chipset scrub capabilities */
 371         enum scrub_type scrub_mode;     /* current scrub mode */
 372
 373         /* Translates sdram memory scrub rate given in bytes/sec to the
 374            internal representation and configures whatever else needs
 375            to be configured.
 376          */
 377         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 378
 379         /* Get the current sdram memory scrub rate from the internal
 380            representation and converts it to the closest matching
 381            bandwith in bytes/sec.
 382          */
 383         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 384
 385
 386         /* pointer to edac checking routine */
 387         void (*edac_check) (struct mem_ctl_info * mci);
 388
 389         /*
 390          * Remaps memory pages: controller pages to physical pages.
 391          * For most MC's, this will be NULL.
 392          */
 393         /* FIXME - why not send the phys page to begin with? */
 394         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 395                                            unsigned long page);
 396         int mc_idx;
 397         int nr_csrows;
 398         struct csrow_info *csrows;
 399         /*
 400          * FIXME - what about controllers on other busses? - IDs must be
 401          * unique.  dev pointer should be sufficiently unique, but
 402          * BUS:SLOT.FUNC numbers may not be unique.
 403          */
 404         struct device *dev;
 405         const char *mod_name;
 406         const char *mod_ver;
 407         const char *ctl_name;
 408         const char *dev_name;
 409         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 410         void *pvt_info;
 411         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 412         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 413         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 414         u32 ce_count;           /* Total Correctable Errors for this MC */
 415         unsigned long start_time;       /* mci load start time (in jiffies) */
 416
 417         /* this stuff is for safe removal of mc devices from global list while
 418          * NMI handlers may be traversing list
 419          */
 420         struct rcu_head rcu;
 421         struct completion complete;
 422
 423         /* edac sysfs device control */
 424         struct kobject edac_mci_kobj;
 425
 426         /* Additional top controller level attributes, but specified
 427          * by the low level driver.
 428          *
 429          * Set by the low level driver to provide attributes at the
 430          * controller level, same level as 'ue_count' and 'ce_count' above.
 431          * An array of structures, NULL terminated
 432          *
 433          * If attributes are desired, then set to array of attributes
 434          * If no attributes are desired, leave NULL
 435          */
 436         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 437
 438         /* work struct for this MC */
 439         struct delayed_work work;
 440
 441         /* the internal state of this controller instance */
 442         int op_state;
 443 };
 444
 445 /*
 446  * The following are the structures to provide for a generic
 447  * or abstract 'edac_device'. This set of structures and the
 448  * code that implements the APIs for the same, provide for
 449  * registering EDAC type devices which are NOT standard memory.
 450  *
 451  * CPU caches (L1 and L2)
 452  * DMA engines
 453  * Core CPU swithces
 454  * Fabric switch units
 455  * PCIe interface controllers
 456  * other EDAC/ECC type devices that can be monitored for
 457  * errors, etc.
 458  *
 459  * It allows for a 2 level set of hiearchry. For example:
 460  *
 461  * cache could be composed of L1, L2 and L3 levels of cache.
 462  * Each CPU core would have its own L1 cache, while sharing
 463  * L2 and maybe L3 caches.
 464  *
 465  * View them arranged, via the sysfs presentation:
 466  * /sys/devices/system/edac/..
 467  *
 468  *      mc/             <existing memory device directory>
 469  *      cpu/cpu0/..     <L1 and L2 block directory>
 470  *              /L1-cache/ce_count
 471  *                       /ue_count
 472  *              /L2-cache/ce_count
 473  *                       /ue_count
 474  *      cpu/cpu1/..     <L1 and L2 block directory>
 475  *              /L1-cache/ce_count
 476  *                       /ue_count
 477  *              /L2-cache/ce_count
 478  *                       /ue_count
 479  *      ...
 480  *
 481  *      the L1 and L2 directories would be "edac_device_block's"
 482  */
 483
 484 struct edac_device_counter {
 485         u32 ue_count;
 486         u32 ce_count;
 487 };
 488
 489 /* forward reference */
 490 struct edac_device_ctl_info;
 491 struct edac_device_block;
 492
 493 /* edac_dev_sysfs_attribute structure
 494  *      used for driver sysfs attributes in mem_ctl_info
 495  *      for extra controls and attributes:
 496  *              like high level error Injection controls
 497  */
 498 struct edac_dev_sysfs_attribute {
 499         struct attribute attr;
 500         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 501         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 502 };
 503
 504 /* edac_dev_sysfs_block_attribute structure
 505  *
 506  *      used in leaf 'block' nodes for adding controls/attributes
 507  *
 508  *      each block in each instance of the containing control structure
 509  *      can have an array of the following. The show and store functions
 510  *      will be filled in with the show/store function in the
 511  *      low level driver.
 512  *
 513  *      The 'value' field will be the actual value field used for
 514  *      counting
 515  */
 516 struct edac_dev_sysfs_block_attribute {
 517         struct attribute attr;
 518         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 519         ssize_t (*store)(struct kobject *, struct attribute *,
 520                         const char *, size_t);
 521         struct edac_device_block *block;
 522
 523         unsigned int value;
 524 };
 525
 526 /* device block control structure */
 527 struct edac_device_block {
 528         struct edac_device_instance *instance;  /* Up Pointer */
 529         char name[EDAC_DEVICE_NAME_LEN + 1];
 530
 531         struct edac_device_counter counters;    /* basic UE and CE counters */
 532
 533         int nr_attribs;         /* how many attributes */
 534
 535         /* this block's attributes, could be NULL */
 536         struct edac_dev_sysfs_block_attribute *block_attributes;
 537
 538         /* edac sysfs device control */
 539         struct kobject kobj;
 540 };
 541
 542 /* device instance control structure */
 543 struct edac_device_instance {
 544         struct edac_device_ctl_info *ctl;       /* Up pointer */
 545         char name[EDAC_DEVICE_NAME_LEN + 4];
 546
 547         struct edac_device_counter counters;    /* instance counters */
 548
 549         u32 nr_blocks;          /* how many blocks */
 550         struct edac_device_block *blocks;       /* block array */
 551
 552         /* edac sysfs device control */
 553         struct kobject kobj;
 554 };
 555
 556
 557 /*
 558  * Abstract edac_device control info structure
 559  *
 560  */
 561 struct edac_device_ctl_info {
 562         /* for global list of edac_device_ctl_info structs */
 563         struct list_head link;
 564
 565         struct module *owner;   /* Module owner of this control struct */
 566
 567         int dev_idx;
 568
 569         /* Per instance controls for this edac_device */
 570         int log_ue;             /* boolean for logging UEs */
 571         int log_ce;             /* boolean for logging CEs */
 572         int panic_on_ue;        /* boolean for panic'ing on an UE */
 573         unsigned poll_msec;     /* number of milliseconds to poll interval */
 574         unsigned long delay;    /* number of jiffies for poll_msec */
 575
 576         /* Additional top controller level attributes, but specified
 577          * by the low level driver.
 578          *
 579          * Set by the low level driver to provide attributes at the
 580          * controller level, same level as 'ue_count' and 'ce_count' above.
 581          * An array of structures, NULL terminated
 582          *
 583          * If attributes are desired, then set to array of attributes
 584          * If no attributes are desired, leave NULL
 585          */
 586         struct edac_dev_sysfs_attribute *sysfs_attributes;
 587
 588         /* pointer to main 'edac' class in sysfs */
 589         struct sysdev_class *edac_class;
 590
 591         /* the internal state of this controller instance */
 592         int op_state;
 593         /* work struct for this instance */
 594         struct delayed_work work;
 595
 596         /* pointer to edac polling checking routine:
 597          *      If NOT NULL: points to polling check routine
 598          *      If NULL: Then assumes INTERRUPT operation, where
 599          *              MC driver will receive events
 600          */
 601         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 602
 603         struct device *dev;     /* pointer to device structure */
 604
 605         const char *mod_name;   /* module name */
 606         const char *ctl_name;   /* edac controller  name */
 607         const char *dev_name;   /* pci/platform/etc... name */
 608
 609         void *pvt_info;         /* pointer to 'private driver' info */
 610
 611         unsigned long start_time;       /* edac_device load start time (jiffies) */
 612
 613         /* these are for safe removal of mc devices from global list while
 614          * NMI handlers may be traversing list
 615          */
 616         struct rcu_head rcu;
 617         struct completion removal_complete;
 618
 619         /* sysfs top name under 'edac' directory
 620          * and instance name:
 621          *      cpu/cpu0/...
 622          *      cpu/cpu1/...
 623          *      cpu/cpu2/...
 624          *      ...
 625          */
 626         char name[EDAC_DEVICE_NAME_LEN + 1];
 627
 628         /* Number of instances supported on this control structure
 629          * and the array of those instances
 630          */
 631         u32 nr_instances;
 632         struct edac_device_instance *instances;
 633
 634         /* Event counters for the this whole EDAC Device */
 635         struct edac_device_counter counters;
 636
 637         /* edac sysfs device control for the 'name'
 638          * device this structure controls
 639          */
 640         struct kobject kobj;
 641 };
 642
 643 /* To get from the instance's wq to the beginning of the ctl structure */
 644 #define to_edac_mem_ctl_work(w) \
 645                 container_of(w, struct mem_ctl_info, work)
 646
 647 #define to_edac_device_ctl_work(w) \
 648                 container_of(w,struct edac_device_ctl_info,work)
 649
 650 /*
 651  * The alloc() and free() functions for the 'edac_device' control info
 652  * structure. A MC driver will allocate one of these for each edac_device
 653  * it is going to control/register with the EDAC CORE.
 654  */
 655 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 656                 unsigned sizeof_private,
 657                 char *edac_device_name, unsigned nr_instances,
 658                 char *edac_block_name, unsigned nr_blocks,
 659                 unsigned offset_value,
 660                 struct edac_dev_sysfs_block_attribute *block_attributes,
 661                 unsigned nr_attribs,
 662                 int device_index);
 663
 664 /* The offset value can be:
 665  *      -1 indicating no offset value
 666  *      0 for zero-based block numbers
 667  *      1 for 1-based block number
 668  *      other for other-based block number
 669  */
 670 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 671
 672 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 673
 674 #ifdef CONFIG_PCI
 675
 676 struct edac_pci_counter {
 677         atomic_t pe_count;
 678         atomic_t npe_count;
 679 };
 680
 681 /*
 682  * Abstract edac_pci control info structure
 683  *
 684  */
 685 struct edac_pci_ctl_info {
 686         /* for global list of edac_pci_ctl_info structs */
 687         struct list_head link;
 688
 689         int pci_idx;
 690
 691         struct sysdev_class *edac_class;        /* pointer to class */
 692
 693         /* the internal state of this controller instance */
 694         int op_state;
 695         /* work struct for this instance */
 696         struct delayed_work work;
 697
 698         /* pointer to edac polling checking routine:
 699          *      If NOT NULL: points to polling check routine
 700          *      If NULL: Then assumes INTERRUPT operation, where
 701          *              MC driver will receive events
 702          */
 703         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 704
 705         struct device *dev;     /* pointer to device structure */
 706
 707         const char *mod_name;   /* module name */
 708         const char *ctl_name;   /* edac controller  name */
 709         const char *dev_name;   /* pci/platform/etc... name */
 710
 711         void *pvt_info;         /* pointer to 'private driver' info */
 712
 713         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 714
 715         /* these are for safe removal of devices from global list while
 716          * NMI handlers may be traversing list
 717          */
 718         struct rcu_head rcu;
 719         struct completion complete;
 720
 721         /* sysfs top name under 'edac' directory
 722          * and instance name:
 723          *      cpu/cpu0/...
 724          *      cpu/cpu1/...
 725          *      cpu/cpu2/...
 726          *      ...
 727          */
 728         char name[EDAC_DEVICE_NAME_LEN + 1];
 729
 730         /* Event counters for the this whole EDAC Device */
 731         struct edac_pci_counter counters;
 732
 733         /* edac sysfs device control for the 'name'
 734          * device this structure controls
 735          */
 736         struct kobject kobj;
 737         struct completion kobj_complete;
 738 };
 739
 740 #define to_edac_pci_ctl_work(w) \
 741                 container_of(w, struct edac_pci_ctl_info,work)
 742
 743 /* write all or some bits in a byte-register*/
 744 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 745                                    u8 mask)
 746 {
 747         if (mask != 0xff) {
 748                 u8 buf;
 749
 750                 pci_read_config_byte(pdev, offset, &buf);
 751                 value &= mask;
 752                 buf &= ~mask;
 753                 value |= buf;
 754         }
 755
 756         pci_write_config_byte(pdev, offset, value);
 757 }
 758
 759 /* write all or some bits in a word-register*/
 760 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 761                                     u16 value, u16 mask)
 762 {
 763         if (mask != 0xffff) {
 764                 u16 buf;
 765
 766                 pci_read_config_word(pdev, offset, &buf);
 767                 value &= mask;
 768                 buf &= ~mask;
 769                 value |= buf;
 770         }
 771
 772         pci_write_config_word(pdev, offset, value);
 773 }
 774
 775 /*
 776  * pci_write_bits32
 777  *
 778  * edac local routine to do pci_write_config_dword, but adds
 779  * a mask parameter. If mask is all ones, ignore the mask.
 780  * Otherwise utilize the mask to isolate specified bits
 781  *
 782  * write all or some bits in a dword-register
 783  */
 784 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 785                                     u32 value, u32 mask)
 786 {
 787         if (mask != 0xffffffff) {
 788                 u32 buf;
 789
 790                 pci_read_config_dword(pdev, offset, &buf);
 791                 value &= mask;
 792                 buf &= ~mask;
 793                 value |= buf;
 794         }
 795
 796         pci_write_config_dword(pdev, offset, value);
 797 }
 798
 799 #endif                          /* CONFIG_PCI */
 800
 801 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 802                                           unsigned nr_chans, int edac_index);
 803 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 804 extern void edac_mc_free(struct mem_ctl_info *mci);
 805 extern struct mem_ctl_info *edac_mc_find(int idx);
 806 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 807 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 808                                       unsigned long page);
 809
 810 /*
 811  * The no info errors are used when error overflows are reported.
 812  * There are a limited number of error logging registers that can
 813  * be exausted.  When all registers are exhausted and an additional
 814  * error occurs then an error overflow register records that an
 815  * error occured and the type of error, but doesn't have any
 816  * further information.  The ce/ue versions make for cleaner
 817  * reporting logic and function interface - reduces conditional
 818  * statement clutter and extra function arguments.
 819  */
 820 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 821                               unsigned long page_frame_number,
 822                               unsigned long offset_in_page,
 823                               unsigned long syndrome, int row, int channel,
 824                               const char *msg);
 825 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 826                                       const char *msg);
 827 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 828                               unsigned long page_frame_number,
 829                               unsigned long offset_in_page, int row,
 830                               const char *msg);
 831 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 832                                       const char *msg);
 833 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 834                                   unsigned int channel0, unsigned int channel1,
 835                                   char *msg);
 836 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 837                                   unsigned int channel, char *msg);
 838
 839 /*
 840  * edac_device APIs
 841  */
 842 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 843 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 844 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 845                                 int inst_nr, int block_nr, const char *msg);
 846 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 847                                 int inst_nr, int block_nr, const char *msg);
 848 extern int edac_device_alloc_index(void);
 849
 850 /*
 851  * edac_pci APIs
 852  */
 853 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 854                                 const char *edac_pci_name);
 855
 856 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 857
 858 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 859                                 unsigned long value);
 860
 861 extern int edac_pci_alloc_index(void);
 862 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 863 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 864
 865 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 866                                 struct device *dev,
 867                                 const char *mod_name);
 868
 869 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 870 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 871 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 872
 873 /*
 874  * edac misc APIs
 875  */
 876 extern char *edac_op_state_to_string(int op_state);
 877
 878 #endif                          /* _EDAC_CORE_H_ */