drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/sched.h>
  16 #include <linux/mtd/mtd.h>
  17 #include <linux/mtd/nand.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/dma.h>
  22
  23 #include <mach/gpmc.h>
  24 #include <mach/nand.h>
  25
  26 #define GPMC_IRQ_STATUS         0x18
  27 #define GPMC_ECC_CONFIG         0x1F4
  28 #define GPMC_ECC_CONTROL        0x1F8
  29 #define GPMC_ECC_SIZE_CONFIG    0x1FC
  30 #define GPMC_ECC1_RESULT        0x200
  31
  32 #define DRIVER_NAME     "omap2-nand"
  33
  34 /* size (4 KiB) for IO mapping */
  35 #define NAND_IO_SIZE    SZ_4K
  36
  37 #define NAND_WP_OFF     0
  38 #define NAND_WP_BIT     0x00000010
  39 #define WR_RD_PIN_MONITORING    0x00600000
  40
  41 #define GPMC_BUF_FULL   0x00000001
  42 #define GPMC_BUF_EMPTY  0x00000000
  43
  44 #define NAND_Ecc_P1e            (1 << 0)
  45 #define NAND_Ecc_P2e            (1 << 1)
  46 #define NAND_Ecc_P4e            (1 << 2)
  47 #define NAND_Ecc_P8e            (1 << 3)
  48 #define NAND_Ecc_P16e           (1 << 4)
  49 #define NAND_Ecc_P32e           (1 << 5)
  50 #define NAND_Ecc_P64e           (1 << 6)
  51 #define NAND_Ecc_P128e          (1 << 7)
  52 #define NAND_Ecc_P256e          (1 << 8)
  53 #define NAND_Ecc_P512e          (1 << 9)
  54 #define NAND_Ecc_P1024e         (1 << 10)
  55 #define NAND_Ecc_P2048e         (1 << 11)
  56
  57 #define NAND_Ecc_P1o            (1 << 16)
  58 #define NAND_Ecc_P2o            (1 << 17)
  59 #define NAND_Ecc_P4o            (1 << 18)
  60 #define NAND_Ecc_P8o            (1 << 19)
  61 #define NAND_Ecc_P16o           (1 << 20)
  62 #define NAND_Ecc_P32o           (1 << 21)
  63 #define NAND_Ecc_P64o           (1 << 22)
  64 #define NAND_Ecc_P128o          (1 << 23)
  65 #define NAND_Ecc_P256o          (1 << 24)
  66 #define NAND_Ecc_P512o          (1 << 25)
  67 #define NAND_Ecc_P1024o         (1 << 26)
  68 #define NAND_Ecc_P2048o         (1 << 27)
  69
  70 #define TF(value)       (value ? 1 : 0)
  71
  72 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  73 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  74 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  75 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  76 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  77 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  78 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  79 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  80
  81 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  82 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  83 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  84 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  85 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  86 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  87 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  88 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  89
  90 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  91 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  92 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  93 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  94 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  95 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  96 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  97 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  98
  99 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
 100 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
 101 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
 102 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
 103 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
 104 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
 105 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
 106 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
 107
 108 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 109 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 110
 111 #ifdef CONFIG_MTD_PARTITIONS
 112 static const char *part_probes[] = { "cmdlinepart", NULL };
 113 #endif
 114
 115 struct omap_nand_info {
 116         struct nand_hw_control          controller;
 117         struct omap_nand_platform_data  *pdata;
 118         struct mtd_info                 mtd;
 119         struct mtd_partition            *parts;
 120         struct nand_chip                nand;
 121         struct platform_device          *pdev;
 122
 123         int                             gpmc_cs;
 124         unsigned long                   phys_base;
 125         void __iomem                    *gpmc_cs_baseaddr;
 126         void __iomem                    *gpmc_baseaddr;
 127 };
 128
 129 /**
 130  * omap_nand_wp - This function enable or disable the Write Protect feature
 131  * @mtd: MTD device structure
 132  * @mode: WP ON/OFF
 133  */
 134 static void omap_nand_wp(struct mtd_info *mtd, int mode)
 135 {
 136         struct omap_nand_info *info = container_of(mtd,
 137                                                 struct omap_nand_info, mtd);
 138
 139         unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
 140
 141         if (mode)
 142                 config &= ~(NAND_WP_BIT);       /* WP is ON */
 143         else
 144                 config |= (NAND_WP_BIT);        /* WP is OFF */
 145
 146         __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
 147 }
 148
 149 /**
 150  * omap_hwcontrol - hardware specific access to control-lines
 151  * @mtd: MTD device structure
 152  * @cmd: command to device
 153  * @ctrl:
 154  * NAND_NCE: bit 0 -> don't care
 155  * NAND_CLE: bit 1 -> Command Latch
 156  * NAND_ALE: bit 2 -> Address Latch
 157  *
 158  * NOTE: boards may use different bits for these!!
 159  */
 160 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 161 {
 162         struct omap_nand_info *info = container_of(mtd,
 163                                         struct omap_nand_info, mtd);
 164         switch (ctrl) {
 165         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
 166                 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
 167                                                 GPMC_CS_NAND_COMMAND;
 168                 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
 169                                                 GPMC_CS_NAND_DATA;
 170                 break;
 171
 172         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
 173                 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
 174                                                 GPMC_CS_NAND_ADDRESS;
 175                 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
 176                                                 GPMC_CS_NAND_DATA;
 177                 break;
 178
 179         case NAND_CTRL_CHANGE | NAND_NCE:
 180                 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
 181                                                 GPMC_CS_NAND_DATA;
 182                 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
 183                                                 GPMC_CS_NAND_DATA;
 184                 break;
 185         }
 186
 187         if (cmd != NAND_CMD_NONE)
 188                 __raw_writeb(cmd, info->nand.IO_ADDR_W);
 189 }
 190
 191 /**
 192  * omap_read_buf16 - read data from NAND controller into buffer
 193  * @mtd: MTD device structure
 194  * @buf: buffer to store date
 195  * @len: number of bytes to read
 196  */
 197 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 198 {
 199         struct nand_chip *nand = mtd->priv;
 200
 201         __raw_readsw(nand->IO_ADDR_R, buf, len / 2);
 202 }
 203
 204 /**
 205  * omap_write_buf16 - write buffer to NAND controller
 206  * @mtd: MTD device structure
 207  * @buf: data buffer
 208  * @len: number of bytes to write
 209  */
 210 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 211 {
 212         struct omap_nand_info *info = container_of(mtd,
 213                                                 struct omap_nand_info, mtd);
 214         u16 *p = (u16 *) buf;
 215
 216         /* FIXME try bursts of writesw() or DMA ... */
 217         len >>= 1;
 218
 219         while (len--) {
 220                 writew(*p++, info->nand.IO_ADDR_W);
 221
 222                 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
 223                                                 GPMC_STATUS) & GPMC_BUF_FULL))
 224                         ;
 225         }
 226 }
 227 /**
 228  * omap_verify_buf - Verify chip data against buffer
 229  * @mtd: MTD device structure
 230  * @buf: buffer containing the data to compare
 231  * @len: number of bytes to compare
 232  */
 233 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 234 {
 235         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 236                                                         mtd);
 237         u16 *p = (u16 *) buf;
 238
 239         len >>= 1;
 240         while (len--) {
 241                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 242                         return -EFAULT;
 243         }
 244
 245         return 0;
 246 }
 247
 248 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
 249 /**
 250  * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller
 251  * @mtd: MTD device structure
 252  */
 253 static void omap_hwecc_init(struct mtd_info *mtd)
 254 {
 255         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 256                                                         mtd);
 257         struct nand_chip *chip = mtd->priv;
 258         unsigned long val = 0x0;
 259
 260         /* Read from ECC Control Register */
 261         val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
 262         /* Clear all ECC | Enable Reg1 */
 263         val = ((0x00000001<<8) | 0x00000001);
 264         __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
 265
 266         /* Read from ECC Size Config Register */
 267         val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
 268         /* ECCSIZE1=512 | Select eccResultsize[0-3] */
 269         val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
 270         __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
 271 }
 272
 273 /**
 274  * gen_true_ecc - This function will generate true ECC value
 275  * @ecc_buf: buffer to store ecc code
 276  *
 277  * This generated true ECC value can be used when correcting
 278  * data read from NAND flash memory core
 279  */
 280 static void gen_true_ecc(u8 *ecc_buf)
 281 {
 282         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 283                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 284
 285         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 286                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 287         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 288                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 289         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 290                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 291 }
 292
 293 /**
 294  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 295  * @ecc_data1:  ecc code from nand spare area
 296  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 297  * @page_data:  page data
 298  *
 299  * This function compares two ECC's and indicates if there is an error.
 300  * If the error can be corrected it will be corrected to the buffer.
 301  */
 302 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 303                             u8 *ecc_data2,      /* read from register */
 304                             u8 *page_data)
 305 {
 306         uint    i;
 307         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 308         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 309         u8      ecc_bit[24];
 310         u8      ecc_sum = 0;
 311         u8      find_bit = 0;
 312         uint    find_byte = 0;
 313         int     isEccFF;
 314
 315         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 316
 317         gen_true_ecc(ecc_data1);
 318         gen_true_ecc(ecc_data2);
 319
 320         for (i = 0; i <= 2; i++) {
 321                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 322                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 323         }
 324
 325         for (i = 0; i < 8; i++) {
 326                 tmp0_bit[i]     = *ecc_data1 % 2;
 327                 *ecc_data1      = *ecc_data1 / 2;
 328         }
 329
 330         for (i = 0; i < 8; i++) {
 331                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 332                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 333         }
 334
 335         for (i = 0; i < 8; i++) {
 336                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 337                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 338         }
 339
 340         for (i = 0; i < 8; i++) {
 341                 comp0_bit[i]     = *ecc_data2 % 2;
 342                 *ecc_data2       = *ecc_data2 / 2;
 343         }
 344
 345         for (i = 0; i < 8; i++) {
 346                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 347                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 348         }
 349
 350         for (i = 0; i < 8; i++) {
 351                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 352                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 353         }
 354
 355         for (i = 0; i < 6; i++)
 356                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 357
 358         for (i = 0; i < 8; i++)
 359                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 360
 361         for (i = 0; i < 8; i++)
 362                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 363
 364         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 365         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 366
 367         for (i = 0; i < 24; i++)
 368                 ecc_sum += ecc_bit[i];
 369
 370         switch (ecc_sum) {
 371         case 0:
 372                 /* Not reached because this function is not called if
 373                  *  ECC values are equal
 374                  */
 375                 return 0;
 376
 377         case 1:
 378                 /* Uncorrectable error */
 379                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 380                 return -1;
 381
 382         case 11:
 383                 /* UN-Correctable error */
 384                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
 385                 return -1;
 386
 387         case 12:
 388                 /* Correctable error */
 389                 find_byte = (ecc_bit[23] << 8) +
 390                             (ecc_bit[21] << 7) +
 391                             (ecc_bit[19] << 6) +
 392                             (ecc_bit[17] << 5) +
 393                             (ecc_bit[15] << 4) +
 394                             (ecc_bit[13] << 3) +
 395                             (ecc_bit[11] << 2) +
 396                             (ecc_bit[9]  << 1) +
 397                             ecc_bit[7];
 398
 399                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 400
 401                 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
 402                                 "offset: %d, bit: %d\n", find_byte, find_bit);
 403
 404                 page_data[find_byte] ^= (1 << find_bit);
 405
 406                 return 0;
 407         default:
 408                 if (isEccFF) {
 409                         if (ecc_data2[0] == 0 &&
 410                             ecc_data2[1] == 0 &&
 411                             ecc_data2[2] == 0)
 412                                 return 0;
 413                 }
 414                 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 415                 return -1;
 416         }
 417 }
 418
 419 /**
 420  * omap_correct_data - Compares the ECC read with HW generated ECC
 421  * @mtd: MTD device structure
 422  * @dat: page data
 423  * @read_ecc: ecc read from nand flash
 424  * @calc_ecc: ecc read from HW ECC registers
 425  *
 426  * Compares the ecc read from nand spare area with ECC registers values
 427  * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
 428  * and correction.
 429  */
 430 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 431                                 u_char *read_ecc, u_char *calc_ecc)
 432 {
 433         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 434                                                         mtd);
 435         int blockCnt = 0, i = 0, ret = 0;
 436
 437         /* Ex NAND_ECC_HW12_2048 */
 438         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 439                         (info->nand.ecc.size  == 2048))
 440                 blockCnt = 4;
 441         else
 442                 blockCnt = 1;
 443
 444         for (i = 0; i < blockCnt; i++) {
 445                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 446                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 447                         if (ret < 0)
 448                                 return ret;
 449                 }
 450                 read_ecc += 3;
 451                 calc_ecc += 3;
 452                 dat      += 512;
 453         }
 454         return 0;
 455 }
 456
 457 /**
 458  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 459  * @mtd: MTD device structure
 460  * @dat: The pointer to data on which ecc is computed
 461  * @ecc_code: The ecc_code buffer
 462  *
 463  * Using noninverted ECC can be considered ugly since writing a blank
 464  * page ie. padding will clear the ECC bytes. This is no problem as long
 465  * nobody is trying to write data on the seemingly unused page. Reading
 466  * an erased page will produce an ECC mismatch between generated and read
 467  * ECC bytes that has to be dealt with separately.
 468  */
 469 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 470                                 u_char *ecc_code)
 471 {
 472         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 473                                                         mtd);
 474         unsigned long val = 0x0;
 475         unsigned long reg;
 476
 477         /* Start Reading from HW ECC1_Result = 0x200 */
 478         reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
 479         val = __raw_readl(reg);
 480         *ecc_code++ = val;          /* P128e, ..., P1e */
 481         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 482         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 483         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 484         reg += 4;
 485
 486         return 0;
 487 }
 488
 489 /**
 490  * omap_enable_hwecc - This function enables the hardware ecc functionality
 491  * @mtd: MTD device structure
 492  * @mode: Read/Write mode
 493  */
 494 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 495 {
 496         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 497                                                         mtd);
 498         struct nand_chip *chip = mtd->priv;
 499         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 500         unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
 501
 502         switch (mode) {
 503         case NAND_ECC_READ:
 504                 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
 505                 /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 506                 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 507                 break;
 508         case NAND_ECC_READSYN:
 509                  __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
 510                 /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 511                 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 512                 break;
 513         case NAND_ECC_WRITE:
 514                 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
 515                 /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 516                 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 517                 break;
 518         default:
 519                 DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
 520                                         mode);
 521                 break;
 522         }
 523
 524         __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
 525 }
 526 #endif
 527
 528 /**
 529  * omap_wait - wait until the command is done
 530  * @mtd: MTD device structure
 531  * @chip: NAND Chip structure
 532  *
 533  * Wait function is called during Program and erase operations and
 534  * the way it is called from MTD layer, we should wait till the NAND
 535  * chip is ready after the programming/erase operation has completed.
 536  *
 537  * Erase can take up to 400ms and program up to 20ms according to
 538  * general NAND and SmartMedia specs
 539  */
 540 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 541 {
 542         struct nand_chip *this = mtd->priv;
 543         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 544                                                         mtd);
 545         unsigned long timeo = jiffies;
 546         int status = NAND_STATUS_FAIL, state = this->state;
 547
 548         if (state == FL_ERASING)
 549                 timeo += (HZ * 400) / 1000;
 550         else
 551                 timeo += (HZ * 20) / 1000;
 552
 553         this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
 554                                                 GPMC_CS_NAND_COMMAND;
 555         this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
 556
 557         __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
 558
 559         while (time_before(jiffies, timeo)) {
 560                 status = __raw_readb(this->IO_ADDR_R);
 561                 if (status & NAND_STATUS_READY)
 562                         break;
 563                 cond_resched();
 564         }
 565         return status;
 566 }
 567
 568 /**
 569  * omap_dev_ready - calls the platform specific dev_ready function
 570  * @mtd: MTD device structure
 571  */
 572 static int omap_dev_ready(struct mtd_info *mtd)
 573 {
 574         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 575                                                         mtd);
 576         unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
 577
 578         if ((val & 0x100) == 0x100) {
 579                 /* Clear IRQ Interrupt */
 580                 val |= 0x100;
 581                 val &= ~(0x0);
 582                 __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
 583         } else {
 584                 unsigned int cnt = 0;
 585                 while (cnt++ < 0x1FF) {
 586                         if  ((val & 0x100) == 0x100)
 587                                 return 0;
 588                         val = __raw_readl(info->gpmc_baseaddr +
 589                                                         GPMC_IRQ_STATUS);
 590                 }
 591         }
 592
 593         return 1;
 594 }
 595
 596 static int __devinit omap_nand_probe(struct platform_device *pdev)
 597 {
 598         struct omap_nand_info           *info;
 599         struct omap_nand_platform_data  *pdata;
 600         int                             err;
 601         unsigned long                   val;
 602
 603
 604         pdata = pdev->dev.platform_data;
 605         if (pdata == NULL) {
 606                 dev_err(&pdev->dev, "platform data missing\n");
 607                 return -ENODEV;
 608         }
 609
 610         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 611         if (!info)
 612                 return -ENOMEM;
 613
 614         platform_set_drvdata(pdev, info);
 615
 616         spin_lock_init(&info->controller.lock);
 617         init_waitqueue_head(&info->controller.wq);
 618
 619         info->pdev = pdev;
 620
 621         info->gpmc_cs           = pdata->cs;
 622         info->gpmc_baseaddr     = pdata->gpmc_baseaddr;
 623         info->gpmc_cs_baseaddr  = pdata->gpmc_cs_baseaddr;
 624
 625         info->mtd.priv          = &info->nand;
 626         info->mtd.name          = dev_name(&pdev->dev);
 627         info->mtd.owner         = THIS_MODULE;
 628
 629         err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
 630         if (err < 0) {
 631                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 632                 goto out_free_info;
 633         }
 634
 635         /* Enable RD PIN Monitoring Reg */
 636         if (pdata->dev_ready) {
 637                 val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
 638                 val |= WR_RD_PIN_MONITORING;
 639                 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
 640         }
 641
 642         val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
 643         val &= ~(0xf << 8);
 644         val |=  (0xc & 0xf) << 8;
 645         gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
 646
 647         /* NAND write protect off */
 648         omap_nand_wp(&info->mtd, NAND_WP_OFF);
 649
 650         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 651                                 pdev->dev.driver->name)) {
 652                 err = -EBUSY;
 653                 goto out_free_cs;
 654         }
 655
 656         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 657         if (!info->nand.IO_ADDR_R) {
 658                 err = -ENOMEM;
 659                 goto out_release_mem_region;
 660         }
 661         info->nand.controller = &info->controller;
 662
 663         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 664         info->nand.cmd_ctrl  = omap_hwcontrol;
 665
 666         /* REVISIT:  only supports 16-bit NAND flash */
 667
 668         info->nand.read_buf   = omap_read_buf16;
 669         info->nand.write_buf  = omap_write_buf16;
 670         info->nand.verify_buf = omap_verify_buf;
 671
 672         /*
 673          * If RDY/BSY line is connected to OMAP then use the omap ready
 674          * funcrtion and the generic nand_wait function which reads the status
 675          * register after monitoring the RDY/BSY line.Otherwise use a standard
 676          * chip delay which is slightly more than tR (AC Timing) of the NAND
 677          * device and read status register until you get a failure or success
 678          */
 679         if (pdata->dev_ready) {
 680                 info->nand.dev_ready = omap_dev_ready;
 681                 info->nand.chip_delay = 0;
 682         } else {
 683                 info->nand.waitfunc = omap_wait;
 684                 info->nand.chip_delay = 50;
 685         }
 686
 687         info->nand.options  |= NAND_SKIP_BBTSCAN;
 688         if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
 689                                                                 == 0x1000)
 690                 info->nand.options  |= NAND_BUSWIDTH_16;
 691
 692 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
 693         info->nand.ecc.bytes            = 3;
 694         info->nand.ecc.size             = 512;
 695         info->nand.ecc.calculate        = omap_calculate_ecc;
 696         info->nand.ecc.hwctl            = omap_enable_hwecc;
 697         info->nand.ecc.correct          = omap_correct_data;
 698         info->nand.ecc.mode             = NAND_ECC_HW;
 699
 700         /* init HW ECC */
 701         omap_hwecc_init(&info->mtd);
 702 #else
 703         info->nand.ecc.mode = NAND_ECC_SOFT;
 704 #endif
 705
 706         /* DIP switches on some boards change between 8 and 16 bit
 707          * bus widths for flash.  Try the other width if the first try fails.
 708          */
 709         if (nand_scan(&info->mtd, 1)) {
 710                 info->nand.options ^= NAND_BUSWIDTH_16;
 711                 if (nand_scan(&info->mtd, 1)) {
 712                         err = -ENXIO;
 713                         goto out_release_mem_region;
 714                 }
 715         }
 716
 717 #ifdef CONFIG_MTD_PARTITIONS
 718         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
 719         if (err > 0)
 720                 add_mtd_partitions(&info->mtd, info->parts, err);
 721         else if (pdata->parts)
 722                 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 723         else
 724 #endif
 725                 add_mtd_device(&info->mtd);
 726
 727         platform_set_drvdata(pdev, &info->mtd);
 728
 729         return 0;
 730
 731 out_release_mem_region:
 732         release_mem_region(info->phys_base, NAND_IO_SIZE);
 733 out_free_cs:
 734         gpmc_cs_free(info->gpmc_cs);
 735 out_free_info:
 736         kfree(info);
 737
 738         return err;
 739 }
 740
 741 static int omap_nand_remove(struct platform_device *pdev)
 742 {
 743         struct mtd_info *mtd = platform_get_drvdata(pdev);
 744         struct omap_nand_info *info = mtd->priv;
 745
 746         platform_set_drvdata(pdev, NULL);
 747         /* Release NAND device, its internal structures and partitions */
 748         nand_release(&info->mtd);
 749         iounmap(info->nand.IO_ADDR_R);
 750         kfree(&info->mtd);
 751         return 0;
 752 }
 753
 754 static struct platform_driver omap_nand_driver = {
 755         .probe          = omap_nand_probe,
 756         .remove         = omap_nand_remove,
 757         .driver         = {
 758                 .name   = DRIVER_NAME,
 759                 .owner  = THIS_MODULE,
 760         },
 761 };
 762
 763 static int __init omap_nand_init(void)
 764 {
 765         printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
 766         return platform_driver_register(&omap_nand_driver);
 767 }
 768
 769 static void __exit omap_nand_exit(void)
 770 {
 771         platform_driver_unregister(&omap_nand_driver);
 772 }
 773
 774 module_init(omap_nand_init);
 775 module_exit(omap_nand_exit);
 776
 777 MODULE_ALIAS(DRIVER_NAME);
 778 MODULE_LICENSE("GPL");
 779 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");