2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 const char *pci_power_names
[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names
);
32 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
34 #ifdef CONFIG_PCI_DOMAINS
35 int pci_domains_supported
= 1;
38 #define DEFAULT_CARDBUS_IO_SIZE (256)
39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
41 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
42 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
45 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
46 * @bus: pointer to PCI bus structure to search
48 * Given a PCI bus, returns the highest PCI bus number present in the set
49 * including the given PCI bus and its list of child PCI buses.
51 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
53 struct list_head
*tmp
;
56 max
= bus
->subordinate
;
57 list_for_each(tmp
, &bus
->children
) {
58 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
64 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
66 #ifdef CONFIG_HAS_IOMEM
67 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
70 * Make sure the BAR is actually a memory resource, not an IO resource
72 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
76 return ioremap_nocache(pci_resource_start(pdev
, bar
),
77 pci_resource_len(pdev
, bar
));
79 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
84 * pci_max_busnr - returns maximum PCI bus number
86 * Returns the highest PCI bus number present in the system global list of
89 unsigned char __devinit
92 struct pci_bus
*bus
= NULL
;
96 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
97 n
= pci_bus_max_busnr(bus
);
106 #define PCI_FIND_CAP_TTL 48
108 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
109 u8 pos
, int cap
, int *ttl
)
114 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
118 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
124 pos
+= PCI_CAP_LIST_NEXT
;
129 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
132 int ttl
= PCI_FIND_CAP_TTL
;
134 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
137 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
139 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
140 pos
+ PCI_CAP_LIST_NEXT
, cap
);
142 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
144 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
145 unsigned int devfn
, u8 hdr_type
)
149 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
150 if (!(status
& PCI_STATUS_CAP_LIST
))
154 case PCI_HEADER_TYPE_NORMAL
:
155 case PCI_HEADER_TYPE_BRIDGE
:
156 return PCI_CAPABILITY_LIST
;
157 case PCI_HEADER_TYPE_CARDBUS
:
158 return PCI_CB_CAPABILITY_LIST
;
167 * pci_find_capability - query for devices' capabilities
168 * @dev: PCI device to query
169 * @cap: capability code
171 * Tell if a device supports a given PCI capability.
172 * Returns the address of the requested capability structure within the
173 * device's PCI configuration space or 0 in case the device does not
174 * support it. Possible values for @cap:
176 * %PCI_CAP_ID_PM Power Management
177 * %PCI_CAP_ID_AGP Accelerated Graphics Port
178 * %PCI_CAP_ID_VPD Vital Product Data
179 * %PCI_CAP_ID_SLOTID Slot Identification
180 * %PCI_CAP_ID_MSI Message Signalled Interrupts
181 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
182 * %PCI_CAP_ID_PCIX PCI-X
183 * %PCI_CAP_ID_EXP PCI Express
185 int pci_find_capability(struct pci_dev
*dev
, int cap
)
189 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
191 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
197 * pci_bus_find_capability - query for devices' capabilities
198 * @bus: the PCI bus to query
199 * @devfn: PCI device to query
200 * @cap: capability code
202 * Like pci_find_capability() but works for pci devices that do not have a
203 * pci_dev structure set up yet.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
209 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
214 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
216 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
218 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
224 * pci_find_ext_capability - Find an extended capability
225 * @dev: PCI device to query
226 * @cap: capability code
228 * Returns the address of the requested extended capability structure
229 * within the device's PCI configuration space or 0 if the device does
230 * not support it. Possible values for @cap:
232 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
233 * %PCI_EXT_CAP_ID_VC Virtual Channel
234 * %PCI_EXT_CAP_ID_DSN Device Serial Number
235 * %PCI_EXT_CAP_ID_PWR Power Budgeting
237 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
241 int pos
= PCI_CFG_SPACE_SIZE
;
243 /* minimum 8 bytes per capability */
244 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
246 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
249 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
253 * If we have no capabilities, this is indicated by cap ID,
254 * cap version and next pointer all being 0.
260 if (PCI_EXT_CAP_ID(header
) == cap
)
263 pos
= PCI_EXT_CAP_NEXT(header
);
264 if (pos
< PCI_CFG_SPACE_SIZE
)
267 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
273 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
275 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
277 int rc
, ttl
= PCI_FIND_CAP_TTL
;
280 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
281 mask
= HT_3BIT_CAP_MASK
;
283 mask
= HT_5BIT_CAP_MASK
;
285 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
286 PCI_CAP_ID_HT
, &ttl
);
288 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
289 if (rc
!= PCIBIOS_SUCCESSFUL
)
292 if ((cap
& mask
) == ht_cap
)
295 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
296 pos
+ PCI_CAP_LIST_NEXT
,
297 PCI_CAP_ID_HT
, &ttl
);
303 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
304 * @dev: PCI device to query
305 * @pos: Position from which to continue searching
306 * @ht_cap: Hypertransport capability code
308 * To be used in conjunction with pci_find_ht_capability() to search for
309 * all capabilities matching @ht_cap. @pos should always be a value returned
310 * from pci_find_ht_capability().
312 * NB. To be 100% safe against broken PCI devices, the caller should take
313 * steps to avoid an infinite loop.
315 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
317 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
319 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
322 * pci_find_ht_capability - query a device's Hypertransport capabilities
323 * @dev: PCI device to query
324 * @ht_cap: Hypertransport capability code
326 * Tell if a device supports a given Hypertransport capability.
327 * Returns an address within the device's PCI configuration space
328 * or 0 in case the device does not support the request capability.
329 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
330 * which has a Hypertransport capability matching @ht_cap.
332 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
336 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
338 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
342 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
345 * pci_find_parent_resource - return resource region of parent bus of given region
346 * @dev: PCI device structure contains resources to be searched
347 * @res: child resource record for which parent is sought
349 * For given resource region of given device, return the resource
350 * region of parent bus the given region is contained in or where
351 * it should be allocated from.
354 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
356 const struct pci_bus
*bus
= dev
->bus
;
358 struct resource
*best
= NULL
;
360 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
361 struct resource
*r
= bus
->resource
[i
];
364 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
365 continue; /* Not contained */
366 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
367 continue; /* Wrong type */
368 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
369 return r
; /* Exact match */
370 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
371 best
= r
; /* Approximating prefetchable by non-prefetchable */
377 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
378 * @dev: PCI device to have its BARs restored
380 * Restore the BAR values for a given device, so as to make it
381 * accessible by its driver.
384 pci_restore_bars(struct pci_dev
*dev
)
388 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
389 pci_update_resource(dev
, i
);
392 static struct pci_platform_pm_ops
*pci_platform_pm
;
394 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
396 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
397 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
399 pci_platform_pm
= ops
;
403 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
405 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
408 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
411 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
414 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
416 return pci_platform_pm
?
417 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
420 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
422 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
425 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
427 return pci_platform_pm
?
428 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
432 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
434 * @dev: PCI device to handle.
435 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
438 * -EINVAL if the requested state is invalid.
439 * -EIO if device does not support PCI PM or its PM capabilities register has a
440 * wrong version, or device doesn't support the requested state.
441 * 0 if device already is in the requested state.
442 * 0 if device's power state has been successfully changed.
444 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
447 bool need_restore
= false;
449 /* Check if we're already there */
450 if (dev
->current_state
== state
)
456 if (state
< PCI_D0
|| state
> PCI_D3hot
)
459 /* Validate current state:
460 * Can enter D0 from any state, but if we can only go deeper
461 * to sleep if we're already in a low power state
463 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
464 && dev
->current_state
> state
) {
465 dev_err(&dev
->dev
, "invalid power transition "
466 "(from state %d to %d)\n", dev
->current_state
, state
);
470 /* check if this device supports the desired state */
471 if ((state
== PCI_D1
&& !dev
->d1_support
)
472 || (state
== PCI_D2
&& !dev
->d2_support
))
475 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
477 /* If we're (effectively) in D3, force entire word to 0.
478 * This doesn't affect PME_Status, disables PME_En, and
479 * sets PowerState to 0.
481 switch (dev
->current_state
) {
485 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
490 case PCI_UNKNOWN
: /* Boot-up */
491 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
492 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
494 /* Fall-through: force to D0 */
500 /* enter specified state */
501 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
503 /* Mandatory power management transition delays */
504 /* see PCI PM 1.1 5.6.1 table 18 */
505 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
506 msleep(pci_pm_d3_delay
);
507 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
508 udelay(PCI_PM_D2_DELAY
);
510 dev
->current_state
= state
;
512 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
513 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
514 * from D3hot to D0 _may_ perform an internal reset, thereby
515 * going to "D0 Uninitialized" rather than "D0 Initialized".
516 * For example, at least some versions of the 3c905B and the
517 * 3c556B exhibit this behaviour.
519 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
520 * devices in a D3hot state at boot. Consequently, we need to
521 * restore at least the BARs so that the device will be
522 * accessible to its driver.
525 pci_restore_bars(dev
);
528 pcie_aspm_pm_state_change(dev
->bus
->self
);
534 * pci_update_current_state - Read PCI power state of given device from its
535 * PCI PM registers and cache it
536 * @dev: PCI device to handle.
537 * @state: State to cache in case the device doesn't have the PM capability
539 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
544 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
545 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
547 dev
->current_state
= state
;
552 * pci_platform_power_transition - Use platform to change device power state
553 * @dev: PCI device to handle.
554 * @state: State to put the device into.
556 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
560 if (platform_pci_power_manageable(dev
)) {
561 error
= platform_pci_set_power_state(dev
, state
);
563 pci_update_current_state(dev
, state
);
566 /* Fall back to PCI_D0 if native PM is not supported */
568 dev
->current_state
= PCI_D0
;
575 * __pci_start_power_transition - Start power transition of a PCI device
576 * @dev: PCI device to handle.
577 * @state: State to put the device into.
579 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
582 pci_platform_power_transition(dev
, PCI_D0
);
586 * __pci_complete_power_transition - Complete power transition of a PCI device
587 * @dev: PCI device to handle.
588 * @state: State to put the device into.
590 * This function should not be called directly by device drivers.
592 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
594 return state
> PCI_D0
?
595 pci_platform_power_transition(dev
, state
) : -EINVAL
;
597 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
600 * pci_set_power_state - Set the power state of a PCI device
601 * @dev: PCI device to handle.
602 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
604 * Transition a device to a new power state, using the platform firmware and/or
605 * the device's PCI PM registers.
608 * -EINVAL if the requested state is invalid.
609 * -EIO if device does not support PCI PM or its PM capabilities register has a
610 * wrong version, or device doesn't support the requested state.
611 * 0 if device already is in the requested state.
612 * 0 if device's power state has been successfully changed.
614 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
618 /* bound the state we're entering */
619 if (state
> PCI_D3hot
)
621 else if (state
< PCI_D0
)
623 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
625 * If the device or the parent bridge do not support PCI PM,
626 * ignore the request if we're doing anything other than putting
627 * it into D0 (which would only happen on boot).
631 /* Check if we're already there */
632 if (dev
->current_state
== state
)
635 __pci_start_power_transition(dev
, state
);
637 /* This device is quirked not to be put into D3, so
638 don't put it in D3 */
639 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
642 error
= pci_raw_set_power_state(dev
, state
);
644 if (!__pci_complete_power_transition(dev
, state
))
651 * pci_choose_state - Choose the power state of a PCI device
652 * @dev: PCI device to be suspended
653 * @state: target sleep state for the whole system. This is the value
654 * that is passed to suspend() function.
656 * Returns PCI power state suitable for given device and given system
660 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
664 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
667 ret
= platform_pci_choose_state(dev
);
668 if (ret
!= PCI_POWER_ERROR
)
671 switch (state
.event
) {
674 case PM_EVENT_FREEZE
:
675 case PM_EVENT_PRETHAW
:
676 /* REVISIT both freeze and pre-thaw "should" use D0 */
677 case PM_EVENT_SUSPEND
:
678 case PM_EVENT_HIBERNATE
:
681 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
688 EXPORT_SYMBOL(pci_choose_state
);
690 #define PCI_EXP_SAVE_REGS 7
692 #define pcie_cap_has_devctl(type, flags) 1
693 #define pcie_cap_has_lnkctl(type, flags) \
694 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
695 (type == PCI_EXP_TYPE_ROOT_PORT || \
696 type == PCI_EXP_TYPE_ENDPOINT || \
697 type == PCI_EXP_TYPE_LEG_END))
698 #define pcie_cap_has_sltctl(type, flags) \
699 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
700 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
701 (type == PCI_EXP_TYPE_DOWNSTREAM && \
702 (flags & PCI_EXP_FLAGS_SLOT))))
703 #define pcie_cap_has_rtctl(type, flags) \
704 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
705 (type == PCI_EXP_TYPE_ROOT_PORT || \
706 type == PCI_EXP_TYPE_RC_EC))
707 #define pcie_cap_has_devctl2(type, flags) \
708 ((flags & PCI_EXP_FLAGS_VERS) > 1)
709 #define pcie_cap_has_lnkctl2(type, flags) \
710 ((flags & PCI_EXP_FLAGS_VERS) > 1)
711 #define pcie_cap_has_sltctl2(type, flags) \
712 ((flags & PCI_EXP_FLAGS_VERS) > 1)
714 static int pci_save_pcie_state(struct pci_dev
*dev
)
717 struct pci_cap_saved_state
*save_state
;
721 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
725 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
727 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
730 cap
= (u16
*)&save_state
->data
[0];
732 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
734 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
735 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
736 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
737 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
738 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
739 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
740 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
741 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
742 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
743 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
744 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
745 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
746 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
747 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
752 static void pci_restore_pcie_state(struct pci_dev
*dev
)
755 struct pci_cap_saved_state
*save_state
;
759 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
760 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
761 if (!save_state
|| pos
<= 0)
763 cap
= (u16
*)&save_state
->data
[0];
765 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
767 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
768 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
769 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
770 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
771 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
772 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
773 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
774 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
775 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
776 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
777 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
778 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
779 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
780 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
784 static int pci_save_pcix_state(struct pci_dev
*dev
)
787 struct pci_cap_saved_state
*save_state
;
789 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
793 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
795 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
799 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
804 static void pci_restore_pcix_state(struct pci_dev
*dev
)
807 struct pci_cap_saved_state
*save_state
;
810 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
811 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
812 if (!save_state
|| pos
<= 0)
814 cap
= (u16
*)&save_state
->data
[0];
816 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
821 * pci_save_state - save the PCI configuration space of a device before suspending
822 * @dev: - PCI device that we're dealing with
825 pci_save_state(struct pci_dev
*dev
)
828 /* XXX: 100% dword access ok here? */
829 for (i
= 0; i
< 16; i
++)
830 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
831 dev
->state_saved
= true;
832 if ((i
= pci_save_pcie_state(dev
)) != 0)
834 if ((i
= pci_save_pcix_state(dev
)) != 0)
840 * pci_restore_state - Restore the saved state of a PCI device
841 * @dev: - PCI device that we're dealing with
844 pci_restore_state(struct pci_dev
*dev
)
849 /* PCI Express register must be restored first */
850 pci_restore_pcie_state(dev
);
853 * The Base Address register should be programmed before the command
856 for (i
= 15; i
>= 0; i
--) {
857 pci_read_config_dword(dev
, i
* 4, &val
);
858 if (val
!= dev
->saved_config_space
[i
]) {
859 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
860 "space at offset %#x (was %#x, writing %#x)\n",
861 i
, val
, (int)dev
->saved_config_space
[i
]);
862 pci_write_config_dword(dev
,i
* 4,
863 dev
->saved_config_space
[i
]);
866 pci_restore_pcix_state(dev
);
867 pci_restore_msi_state(dev
);
868 pci_restore_iov_state(dev
);
873 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
877 err
= pci_set_power_state(dev
, PCI_D0
);
878 if (err
< 0 && err
!= -EIO
)
880 err
= pcibios_enable_device(dev
, bars
);
883 pci_fixup_device(pci_fixup_enable
, dev
);
889 * pci_reenable_device - Resume abandoned device
890 * @dev: PCI device to be resumed
892 * Note this function is a backend of pci_default_resume and is not supposed
893 * to be called by normal code, write proper resume handler and use it instead.
895 int pci_reenable_device(struct pci_dev
*dev
)
897 if (pci_is_enabled(dev
))
898 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
902 static int __pci_enable_device_flags(struct pci_dev
*dev
,
903 resource_size_t flags
)
908 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
909 return 0; /* already enabled */
911 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
912 if (dev
->resource
[i
].flags
& flags
)
915 err
= do_pci_enable_device(dev
, bars
);
917 atomic_dec(&dev
->enable_cnt
);
922 * pci_enable_device_io - Initialize a device for use with IO space
923 * @dev: PCI device to be initialized
925 * Initialize device before it's used by a driver. Ask low-level code
926 * to enable I/O resources. Wake up the device if it was suspended.
927 * Beware, this function can fail.
929 int pci_enable_device_io(struct pci_dev
*dev
)
931 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
935 * pci_enable_device_mem - Initialize a device for use with Memory space
936 * @dev: PCI device to be initialized
938 * Initialize device before it's used by a driver. Ask low-level code
939 * to enable Memory resources. Wake up the device if it was suspended.
940 * Beware, this function can fail.
942 int pci_enable_device_mem(struct pci_dev
*dev
)
944 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
948 * pci_enable_device - Initialize device before it's used by a driver.
949 * @dev: PCI device to be initialized
951 * Initialize device before it's used by a driver. Ask low-level code
952 * to enable I/O and memory. Wake up the device if it was suspended.
953 * Beware, this function can fail.
955 * Note we don't actually enable the device many times if we call
956 * this function repeatedly (we just increment the count).
958 int pci_enable_device(struct pci_dev
*dev
)
960 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
964 * Managed PCI resources. This manages device on/off, intx/msi/msix
965 * on/off and BAR regions. pci_dev itself records msi/msix status, so
966 * there's no need to track it separately. pci_devres is initialized
967 * when a device is enabled using managed PCI device enable interface.
970 unsigned int enabled
:1;
971 unsigned int pinned
:1;
972 unsigned int orig_intx
:1;
973 unsigned int restore_intx
:1;
977 static void pcim_release(struct device
*gendev
, void *res
)
979 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
980 struct pci_devres
*this = res
;
983 if (dev
->msi_enabled
)
984 pci_disable_msi(dev
);
985 if (dev
->msix_enabled
)
986 pci_disable_msix(dev
);
988 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
989 if (this->region_mask
& (1 << i
))
990 pci_release_region(dev
, i
);
992 if (this->restore_intx
)
993 pci_intx(dev
, this->orig_intx
);
995 if (this->enabled
&& !this->pinned
)
996 pci_disable_device(dev
);
999 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1001 struct pci_devres
*dr
, *new_dr
;
1003 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1007 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1010 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1013 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1015 if (pci_is_managed(pdev
))
1016 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1021 * pcim_enable_device - Managed pci_enable_device()
1022 * @pdev: PCI device to be initialized
1024 * Managed pci_enable_device().
1026 int pcim_enable_device(struct pci_dev
*pdev
)
1028 struct pci_devres
*dr
;
1031 dr
= get_pci_dr(pdev
);
1037 rc
= pci_enable_device(pdev
);
1039 pdev
->is_managed
= 1;
1046 * pcim_pin_device - Pin managed PCI device
1047 * @pdev: PCI device to pin
1049 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1050 * driver detach. @pdev must have been enabled with
1051 * pcim_enable_device().
1053 void pcim_pin_device(struct pci_dev
*pdev
)
1055 struct pci_devres
*dr
;
1057 dr
= find_pci_dr(pdev
);
1058 WARN_ON(!dr
|| !dr
->enabled
);
1064 * pcibios_disable_device - disable arch specific PCI resources for device dev
1065 * @dev: the PCI device to disable
1067 * Disables architecture specific PCI resources for the device. This
1068 * is the default implementation. Architecture implementations can
1071 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1073 static void do_pci_disable_device(struct pci_dev
*dev
)
1077 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1078 if (pci_command
& PCI_COMMAND_MASTER
) {
1079 pci_command
&= ~PCI_COMMAND_MASTER
;
1080 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1083 pcibios_disable_device(dev
);
1087 * pci_disable_enabled_device - Disable device without updating enable_cnt
1088 * @dev: PCI device to disable
1090 * NOTE: This function is a backend of PCI power management routines and is
1091 * not supposed to be called drivers.
1093 void pci_disable_enabled_device(struct pci_dev
*dev
)
1095 if (pci_is_enabled(dev
))
1096 do_pci_disable_device(dev
);
1100 * pci_disable_device - Disable PCI device after use
1101 * @dev: PCI device to be disabled
1103 * Signal to the system that the PCI device is not in use by the system
1104 * anymore. This only involves disabling PCI bus-mastering, if active.
1106 * Note we don't actually disable the device until all callers of
1107 * pci_device_enable() have called pci_device_disable().
1110 pci_disable_device(struct pci_dev
*dev
)
1112 struct pci_devres
*dr
;
1114 dr
= find_pci_dr(dev
);
1118 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1121 do_pci_disable_device(dev
);
1123 dev
->is_busmaster
= 0;
1127 * pcibios_set_pcie_reset_state - set reset state for device dev
1128 * @dev: the PCI-E device reset
1129 * @state: Reset state to enter into
1132 * Sets the PCI-E reset state for the device. This is the default
1133 * implementation. Architecture implementations can override this.
1135 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1136 enum pcie_reset_state state
)
1142 * pci_set_pcie_reset_state - set reset state for device dev
1143 * @dev: the PCI-E device reset
1144 * @state: Reset state to enter into
1147 * Sets the PCI reset state for the device.
1149 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1151 return pcibios_set_pcie_reset_state(dev
, state
);
1155 * pci_pme_capable - check the capability of PCI device to generate PME#
1156 * @dev: PCI device to handle.
1157 * @state: PCI state from which device will issue PME#.
1159 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1164 return !!(dev
->pme_support
& (1 << state
));
1168 * pci_pme_active - enable or disable PCI device's PME# function
1169 * @dev: PCI device to handle.
1170 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1172 * The caller must verify that the device is capable of generating PME# before
1173 * calling this function with @enable equal to 'true'.
1175 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1182 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1183 /* Clear PME_Status by writing 1 to it and enable PME# */
1184 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1186 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1188 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1190 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1191 enable
? "enabled" : "disabled");
1195 * pci_enable_wake - enable PCI device as wakeup event source
1196 * @dev: PCI device affected
1197 * @state: PCI state from which device will issue wakeup events
1198 * @enable: True to enable event generation; false to disable
1200 * This enables the device as a wakeup event source, or disables it.
1201 * When such events involves platform-specific hooks, those hooks are
1202 * called automatically by this routine.
1204 * Devices with legacy power management (no standard PCI PM capabilities)
1205 * always require such platform hooks.
1208 * 0 is returned on success
1209 * -EINVAL is returned if device is not supposed to wake up the system
1210 * Error code depending on the platform is returned if both the platform and
1211 * the native mechanism fail to enable the generation of wake-up events
1213 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
1216 bool pme_done
= false;
1218 if (enable
&& !device_may_wakeup(&dev
->dev
))
1222 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1223 * Anderson we should be doing PME# wake enable followed by ACPI wake
1224 * enable. To disable wake-up we call the platform first, for symmetry.
1227 if (!enable
&& platform_pci_can_wakeup(dev
))
1228 error
= platform_pci_sleep_wake(dev
, false);
1230 if (!enable
|| pci_pme_capable(dev
, state
)) {
1231 pci_pme_active(dev
, enable
);
1235 if (enable
&& platform_pci_can_wakeup(dev
))
1236 error
= platform_pci_sleep_wake(dev
, true);
1238 return pme_done
? 0 : error
;
1242 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1243 * @dev: PCI device to prepare
1244 * @enable: True to enable wake-up event generation; false to disable
1246 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1247 * and this function allows them to set that up cleanly - pci_enable_wake()
1248 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1249 * ordering constraints.
1251 * This function only returns error code if the device is not capable of
1252 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1253 * enable wake-up power for it.
1255 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1257 return pci_pme_capable(dev
, PCI_D3cold
) ?
1258 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1259 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1263 * pci_target_state - find an appropriate low power state for a given PCI dev
1266 * Use underlying platform code to find a supported low power state for @dev.
1267 * If the platform can't manage @dev, return the deepest state from which it
1268 * can generate wake events, based on any available PME info.
1270 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1272 pci_power_t target_state
= PCI_D3hot
;
1274 if (platform_pci_power_manageable(dev
)) {
1276 * Call the platform to choose the target state of the device
1277 * and enable wake-up from this state if supported.
1279 pci_power_t state
= platform_pci_choose_state(dev
);
1282 case PCI_POWER_ERROR
:
1287 if (pci_no_d1d2(dev
))
1290 target_state
= state
;
1292 } else if (!dev
->pm_cap
) {
1293 target_state
= PCI_D0
;
1294 } else if (device_may_wakeup(&dev
->dev
)) {
1296 * Find the deepest state from which the device can generate
1297 * wake-up events, make it the target state and enable device
1300 if (dev
->pme_support
) {
1302 && !(dev
->pme_support
& (1 << target_state
)))
1307 return target_state
;
1311 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1312 * @dev: Device to handle.
1314 * Choose the power state appropriate for the device depending on whether
1315 * it can wake up the system and/or is power manageable by the platform
1316 * (PCI_D3hot is the default) and put the device into that state.
1318 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1320 pci_power_t target_state
= pci_target_state(dev
);
1323 if (target_state
== PCI_POWER_ERROR
)
1326 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1328 error
= pci_set_power_state(dev
, target_state
);
1331 pci_enable_wake(dev
, target_state
, false);
1337 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1338 * @dev: Device to handle.
1340 * Disable device's sytem wake-up capability and put it into D0.
1342 int pci_back_from_sleep(struct pci_dev
*dev
)
1344 pci_enable_wake(dev
, PCI_D0
, false);
1345 return pci_set_power_state(dev
, PCI_D0
);
1349 * pci_pm_init - Initialize PM functions of given PCI device
1350 * @dev: PCI device to handle.
1352 void pci_pm_init(struct pci_dev
*dev
)
1359 /* find PCI PM capability in list */
1360 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1363 /* Check device's ability to generate PME# */
1364 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1366 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1367 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1368 pmc
& PCI_PM_CAP_VER_MASK
);
1374 dev
->d1_support
= false;
1375 dev
->d2_support
= false;
1376 if (!pci_no_d1d2(dev
)) {
1377 if (pmc
& PCI_PM_CAP_D1
)
1378 dev
->d1_support
= true;
1379 if (pmc
& PCI_PM_CAP_D2
)
1380 dev
->d2_support
= true;
1382 if (dev
->d1_support
|| dev
->d2_support
)
1383 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1384 dev
->d1_support
? " D1" : "",
1385 dev
->d2_support
? " D2" : "");
1388 pmc
&= PCI_PM_CAP_PME_MASK
;
1390 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1391 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1392 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1393 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1394 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1395 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1396 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1398 * Make device's PM flags reflect the wake-up capability, but
1399 * let the user space enable it to wake up the system as needed.
1401 device_set_wakeup_capable(&dev
->dev
, true);
1402 device_set_wakeup_enable(&dev
->dev
, false);
1403 /* Disable the PME# generation functionality */
1404 pci_pme_active(dev
, false);
1406 dev
->pme_support
= 0;
1411 * platform_pci_wakeup_init - init platform wakeup if present
1414 * Some devices don't have PCI PM caps but can still generate wakeup
1415 * events through platform methods (like ACPI events). If @dev supports
1416 * platform wakeup events, set the device flag to indicate as much. This
1417 * may be redundant if the device also supports PCI PM caps, but double
1418 * initialization should be safe in that case.
1420 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1422 if (!platform_pci_can_wakeup(dev
))
1425 device_set_wakeup_capable(&dev
->dev
, true);
1426 device_set_wakeup_enable(&dev
->dev
, false);
1427 platform_pci_sleep_wake(dev
, false);
1431 * pci_add_save_buffer - allocate buffer for saving given capability registers
1432 * @dev: the PCI device
1433 * @cap: the capability to allocate the buffer for
1434 * @size: requested size of the buffer
1436 static int pci_add_cap_save_buffer(
1437 struct pci_dev
*dev
, char cap
, unsigned int size
)
1440 struct pci_cap_saved_state
*save_state
;
1442 pos
= pci_find_capability(dev
, cap
);
1446 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1450 save_state
->cap_nr
= cap
;
1451 pci_add_saved_cap(dev
, save_state
);
1457 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1458 * @dev: the PCI device
1460 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1464 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1465 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1468 "unable to preallocate PCI Express save buffer\n");
1470 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1473 "unable to preallocate PCI-X save buffer\n");
1477 * pci_enable_ari - enable ARI forwarding if hardware support it
1478 * @dev: the PCI device
1480 void pci_enable_ari(struct pci_dev
*dev
)
1485 struct pci_dev
*bridge
;
1487 if (!dev
->is_pcie
|| dev
->devfn
)
1490 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1494 bridge
= dev
->bus
->self
;
1495 if (!bridge
|| !bridge
->is_pcie
)
1498 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1502 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1503 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1506 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1507 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1508 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1510 bridge
->ari_enabled
= 1;
1514 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1515 * @dev: the PCI device
1516 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1518 * Perform INTx swizzling for a device behind one level of bridge. This is
1519 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1520 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1521 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1522 * the PCI Express Base Specification, Revision 2.1)
1524 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1528 if (pci_ari_enabled(dev
->bus
))
1531 slot
= PCI_SLOT(dev
->devfn
);
1533 return (((pin
- 1) + slot
) % 4) + 1;
1537 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1545 while (!pci_is_root_bus(dev
->bus
)) {
1546 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1547 dev
= dev
->bus
->self
;
1554 * pci_common_swizzle - swizzle INTx all the way to root bridge
1555 * @dev: the PCI device
1556 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1558 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1559 * bridges all the way up to a PCI root bus.
1561 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1565 while (!pci_is_root_bus(dev
->bus
)) {
1566 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1567 dev
= dev
->bus
->self
;
1570 return PCI_SLOT(dev
->devfn
);
1574 * pci_release_region - Release a PCI bar
1575 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1576 * @bar: BAR to release
1578 * Releases the PCI I/O and memory resources previously reserved by a
1579 * successful call to pci_request_region. Call this function only
1580 * after all use of the PCI regions has ceased.
1582 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1584 struct pci_devres
*dr
;
1586 if (pci_resource_len(pdev
, bar
) == 0)
1588 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1589 release_region(pci_resource_start(pdev
, bar
),
1590 pci_resource_len(pdev
, bar
));
1591 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1592 release_mem_region(pci_resource_start(pdev
, bar
),
1593 pci_resource_len(pdev
, bar
));
1595 dr
= find_pci_dr(pdev
);
1597 dr
->region_mask
&= ~(1 << bar
);
1601 * __pci_request_region - Reserved PCI I/O and memory resource
1602 * @pdev: PCI device whose resources are to be reserved
1603 * @bar: BAR to be reserved
1604 * @res_name: Name to be associated with resource.
1605 * @exclusive: whether the region access is exclusive or not
1607 * Mark the PCI region associated with PCI device @pdev BR @bar as
1608 * being reserved by owner @res_name. Do not access any
1609 * address inside the PCI regions unless this call returns
1612 * If @exclusive is set, then the region is marked so that userspace
1613 * is explicitly not allowed to map the resource via /dev/mem or
1614 * sysfs MMIO access.
1616 * Returns 0 on success, or %EBUSY on error. A warning
1617 * message is also printed on failure.
1619 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1622 struct pci_devres
*dr
;
1624 if (pci_resource_len(pdev
, bar
) == 0)
1627 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1628 if (!request_region(pci_resource_start(pdev
, bar
),
1629 pci_resource_len(pdev
, bar
), res_name
))
1632 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1633 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1634 pci_resource_len(pdev
, bar
), res_name
,
1639 dr
= find_pci_dr(pdev
);
1641 dr
->region_mask
|= 1 << bar
;
1646 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1648 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1649 &pdev
->resource
[bar
]);
1654 * pci_request_region - Reserve PCI I/O and memory resource
1655 * @pdev: PCI device whose resources are to be reserved
1656 * @bar: BAR to be reserved
1657 * @res_name: Name to be associated with resource
1659 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1660 * being reserved by owner @res_name. Do not access any
1661 * address inside the PCI regions unless this call returns
1664 * Returns 0 on success, or %EBUSY on error. A warning
1665 * message is also printed on failure.
1667 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1669 return __pci_request_region(pdev
, bar
, res_name
, 0);
1673 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1674 * @pdev: PCI device whose resources are to be reserved
1675 * @bar: BAR to be reserved
1676 * @res_name: Name to be associated with resource.
1678 * Mark the PCI region associated with PCI device @pdev BR @bar as
1679 * being reserved by owner @res_name. Do not access any
1680 * address inside the PCI regions unless this call returns
1683 * Returns 0 on success, or %EBUSY on error. A warning
1684 * message is also printed on failure.
1686 * The key difference that _exclusive makes it that userspace is
1687 * explicitly not allowed to map the resource via /dev/mem or
1690 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1692 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1695 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1696 * @pdev: PCI device whose resources were previously reserved
1697 * @bars: Bitmask of BARs to be released
1699 * Release selected PCI I/O and memory resources previously reserved.
1700 * Call this function only after all use of the PCI regions has ceased.
1702 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1706 for (i
= 0; i
< 6; i
++)
1707 if (bars
& (1 << i
))
1708 pci_release_region(pdev
, i
);
1711 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1712 const char *res_name
, int excl
)
1716 for (i
= 0; i
< 6; i
++)
1717 if (bars
& (1 << i
))
1718 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1724 if (bars
& (1 << i
))
1725 pci_release_region(pdev
, i
);
1732 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1733 * @pdev: PCI device whose resources are to be reserved
1734 * @bars: Bitmask of BARs to be requested
1735 * @res_name: Name to be associated with resource
1737 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1738 const char *res_name
)
1740 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1743 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1744 int bars
, const char *res_name
)
1746 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1747 IORESOURCE_EXCLUSIVE
);
1751 * pci_release_regions - Release reserved PCI I/O and memory resources
1752 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1754 * Releases all PCI I/O and memory resources previously reserved by a
1755 * successful call to pci_request_regions. Call this function only
1756 * after all use of the PCI regions has ceased.
1759 void pci_release_regions(struct pci_dev
*pdev
)
1761 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1765 * pci_request_regions - Reserved PCI I/O and memory resources
1766 * @pdev: PCI device whose resources are to be reserved
1767 * @res_name: Name to be associated with resource.
1769 * Mark all PCI regions associated with PCI device @pdev as
1770 * being reserved by owner @res_name. Do not access any
1771 * address inside the PCI regions unless this call returns
1774 * Returns 0 on success, or %EBUSY on error. A warning
1775 * message is also printed on failure.
1777 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1779 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1783 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1784 * @pdev: PCI device whose resources are to be reserved
1785 * @res_name: Name to be associated with resource.
1787 * Mark all PCI regions associated with PCI device @pdev as
1788 * being reserved by owner @res_name. Do not access any
1789 * address inside the PCI regions unless this call returns
1792 * pci_request_regions_exclusive() will mark the region so that
1793 * /dev/mem and the sysfs MMIO access will not be allowed.
1795 * Returns 0 on success, or %EBUSY on error. A warning
1796 * message is also printed on failure.
1798 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1800 return pci_request_selected_regions_exclusive(pdev
,
1801 ((1 << 6) - 1), res_name
);
1804 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1808 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1810 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1812 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1813 if (cmd
!= old_cmd
) {
1814 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1815 enable
? "enabling" : "disabling");
1816 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1818 dev
->is_busmaster
= enable
;
1822 * pci_set_master - enables bus-mastering for device dev
1823 * @dev: the PCI device to enable
1825 * Enables bus-mastering on the device and calls pcibios_set_master()
1826 * to do the needed arch specific settings.
1828 void pci_set_master(struct pci_dev
*dev
)
1830 __pci_set_master(dev
, true);
1831 pcibios_set_master(dev
);
1835 * pci_clear_master - disables bus-mastering for device dev
1836 * @dev: the PCI device to disable
1838 void pci_clear_master(struct pci_dev
*dev
)
1840 __pci_set_master(dev
, false);
1843 #ifdef PCI_DISABLE_MWI
1844 int pci_set_mwi(struct pci_dev
*dev
)
1849 int pci_try_set_mwi(struct pci_dev
*dev
)
1854 void pci_clear_mwi(struct pci_dev
*dev
)
1860 #ifndef PCI_CACHE_LINE_BYTES
1861 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1864 /* This can be overridden by arch code. */
1865 /* Don't forget this is measured in 32-bit words, not bytes */
1866 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1869 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1870 * @dev: the PCI device for which MWI is to be enabled
1872 * Helper function for pci_set_mwi.
1873 * Originally copied from drivers/net/acenic.c.
1874 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1876 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1879 pci_set_cacheline_size(struct pci_dev
*dev
)
1883 if (!pci_cache_line_size
)
1884 return -EINVAL
; /* The system doesn't support MWI. */
1886 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1887 equal to or multiple of the right value. */
1888 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1889 if (cacheline_size
>= pci_cache_line_size
&&
1890 (cacheline_size
% pci_cache_line_size
) == 0)
1893 /* Write the correct value. */
1894 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1896 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1897 if (cacheline_size
== pci_cache_line_size
)
1900 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1901 "supported\n", pci_cache_line_size
<< 2);
1907 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1908 * @dev: the PCI device for which MWI is enabled
1910 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1912 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1915 pci_set_mwi(struct pci_dev
*dev
)
1920 rc
= pci_set_cacheline_size(dev
);
1924 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1925 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1926 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1927 cmd
|= PCI_COMMAND_INVALIDATE
;
1928 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1935 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1936 * @dev: the PCI device for which MWI is enabled
1938 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1939 * Callers are not required to check the return value.
1941 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1943 int pci_try_set_mwi(struct pci_dev
*dev
)
1945 int rc
= pci_set_mwi(dev
);
1950 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1951 * @dev: the PCI device to disable
1953 * Disables PCI Memory-Write-Invalidate transaction on the device
1956 pci_clear_mwi(struct pci_dev
*dev
)
1960 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1961 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1962 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1963 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1966 #endif /* ! PCI_DISABLE_MWI */
1969 * pci_intx - enables/disables PCI INTx for device dev
1970 * @pdev: the PCI device to operate on
1971 * @enable: boolean: whether to enable or disable PCI INTx
1973 * Enables/disables PCI INTx for device dev
1976 pci_intx(struct pci_dev
*pdev
, int enable
)
1978 u16 pci_command
, new;
1980 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1983 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1985 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1988 if (new != pci_command
) {
1989 struct pci_devres
*dr
;
1991 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1993 dr
= find_pci_dr(pdev
);
1994 if (dr
&& !dr
->restore_intx
) {
1995 dr
->restore_intx
= 1;
1996 dr
->orig_intx
= !enable
;
2002 * pci_msi_off - disables any msi or msix capabilities
2003 * @dev: the PCI device to operate on
2005 * If you want to use msi see pci_enable_msi and friends.
2006 * This is a lower level primitive that allows us to disable
2007 * msi operation at the device level.
2009 void pci_msi_off(struct pci_dev
*dev
)
2014 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2016 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2017 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2018 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2020 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2022 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2023 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2024 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2028 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2030 * These can be overridden by arch-specific implementations
2033 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
2035 if (!pci_dma_supported(dev
, mask
))
2038 dev
->dma_mask
= mask
;
2044 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
2046 if (!pci_dma_supported(dev
, mask
))
2049 dev
->dev
.coherent_dma_mask
= mask
;
2055 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2056 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2058 return dma_set_max_seg_size(&dev
->dev
, size
);
2060 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2063 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2064 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2066 return dma_set_seg_boundary(&dev
->dev
, mask
);
2068 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2071 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2078 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2082 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2083 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2089 /* Wait for Transaction Pending bit clean */
2090 for (i
= 0; i
< 4; i
++) {
2092 msleep((1 << (i
- 1)) * 100);
2094 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
2095 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2099 dev_err(&dev
->dev
, "transaction is not cleared; "
2100 "proceeding with reset anyway\n");
2103 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
,
2104 PCI_EXP_DEVCTL_BCR_FLR
);
2110 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
2117 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2121 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
2122 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2128 /* Wait for Transaction Pending bit clean */
2129 for (i
= 0; i
< 4; i
++) {
2131 msleep((1 << (i
- 1)) * 100);
2133 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
2134 if (!(status
& PCI_AF_STATUS_TP
))
2138 dev_err(&dev
->dev
, "transaction is not cleared; "
2139 "proceeding with reset anyway\n");
2142 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2148 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
2155 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
2156 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
2162 if (dev
->current_state
!= PCI_D0
)
2165 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2167 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2168 msleep(pci_pm_d3_delay
);
2170 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2172 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2173 msleep(pci_pm_d3_delay
);
2178 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
2181 struct pci_dev
*pdev
;
2183 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
2186 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
2193 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
2194 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
2195 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2198 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
2199 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2205 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
2212 pci_block_user_cfg_access(dev
);
2213 /* block PM suspend, driver probe, etc. */
2214 down(&dev
->dev
.sem
);
2217 rc
= pcie_flr(dev
, probe
);
2221 rc
= pci_af_flr(dev
, probe
);
2225 rc
= pci_pm_reset(dev
, probe
);
2229 rc
= pci_parent_bus_reset(dev
, probe
);
2233 pci_unblock_user_cfg_access(dev
);
2240 * __pci_reset_function - reset a PCI device function
2241 * @dev: PCI device to reset
2243 * Some devices allow an individual function to be reset without affecting
2244 * other functions in the same device. The PCI device must be responsive
2245 * to PCI config space in order to use this function.
2247 * The device function is presumed to be unused when this function is called.
2248 * Resetting the device will make the contents of PCI configuration space
2249 * random, so any caller of this must be prepared to reinitialise the
2250 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2253 * Returns 0 if the device function was successfully reset or negative if the
2254 * device doesn't support resetting a single function.
2256 int __pci_reset_function(struct pci_dev
*dev
)
2258 return pci_dev_reset(dev
, 0);
2260 EXPORT_SYMBOL_GPL(__pci_reset_function
);
2263 * pci_reset_function - quiesce and reset a PCI device function
2264 * @dev: PCI device to reset
2266 * Some devices allow an individual function to be reset without affecting
2267 * other functions in the same device. The PCI device must be responsive
2268 * to PCI config space in order to use this function.
2270 * This function does not just reset the PCI portion of a device, but
2271 * clears all the state associated with the device. This function differs
2272 * from __pci_reset_function in that it saves and restores device state
2275 * Returns 0 if the device function was successfully reset or negative if the
2276 * device doesn't support resetting a single function.
2278 int pci_reset_function(struct pci_dev
*dev
)
2282 rc
= pci_dev_reset(dev
, 1);
2286 pci_save_state(dev
);
2289 * both INTx and MSI are disabled after the Interrupt Disable bit
2290 * is set and the Bus Master bit is cleared.
2292 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2294 rc
= pci_dev_reset(dev
, 0);
2296 pci_restore_state(dev
);
2300 EXPORT_SYMBOL_GPL(pci_reset_function
);
2303 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2304 * @dev: PCI device to query
2306 * Returns mmrbc: maximum designed memory read count in bytes
2307 * or appropriate error value.
2309 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2314 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2318 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2322 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2324 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2327 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2328 * @dev: PCI device to query
2330 * Returns mmrbc: maximum memory read count in bytes
2331 * or appropriate error value.
2333 int pcix_get_mmrbc(struct pci_dev
*dev
)
2338 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2342 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2344 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2348 EXPORT_SYMBOL(pcix_get_mmrbc
);
2351 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2352 * @dev: PCI device to query
2353 * @mmrbc: maximum memory read count in bytes
2354 * valid values are 512, 1024, 2048, 4096
2356 * If possible sets maximum memory read byte count, some bridges have erratas
2357 * that prevent this.
2359 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2361 int cap
, err
= -EINVAL
;
2362 u32 stat
, cmd
, v
, o
;
2364 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2367 v
= ffs(mmrbc
) - 10;
2369 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2373 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2377 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2380 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2384 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2386 if (v
> o
&& dev
->bus
&&
2387 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2390 cmd
&= ~PCI_X_CMD_MAX_READ
;
2392 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2397 EXPORT_SYMBOL(pcix_set_mmrbc
);
2400 * pcie_get_readrq - get PCI Express read request size
2401 * @dev: PCI device to query
2403 * Returns maximum memory read request in bytes
2404 * or appropriate error value.
2406 int pcie_get_readrq(struct pci_dev
*dev
)
2411 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2415 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2417 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2421 EXPORT_SYMBOL(pcie_get_readrq
);
2424 * pcie_set_readrq - set PCI Express maximum memory read request
2425 * @dev: PCI device to query
2426 * @rq: maximum memory read count in bytes
2427 * valid values are 128, 256, 512, 1024, 2048, 4096
2429 * If possible sets maximum read byte count
2431 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2433 int cap
, err
= -EINVAL
;
2436 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2439 v
= (ffs(rq
) - 8) << 12;
2441 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2445 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2449 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2450 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2452 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2458 EXPORT_SYMBOL(pcie_set_readrq
);
2461 * pci_select_bars - Make BAR mask from the type of resource
2462 * @dev: the PCI device for which BAR mask is made
2463 * @flags: resource type mask to be selected
2465 * This helper routine makes bar mask from the type of resource.
2467 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2470 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2471 if (pci_resource_flags(dev
, i
) & flags
)
2477 * pci_resource_bar - get position of the BAR associated with a resource
2478 * @dev: the PCI device
2479 * @resno: the resource number
2480 * @type: the BAR type to be filled in
2482 * Returns BAR position in config space, or 0 if the BAR is invalid.
2484 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2488 if (resno
< PCI_ROM_RESOURCE
) {
2489 *type
= pci_bar_unknown
;
2490 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2491 } else if (resno
== PCI_ROM_RESOURCE
) {
2492 *type
= pci_bar_mem32
;
2493 return dev
->rom_base_reg
;
2494 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2495 /* device specific resource */
2496 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2501 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2505 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2506 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2507 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2510 * pci_specified_resource_alignment - get resource alignment specified by user.
2511 * @dev: the PCI device to get
2513 * RETURNS: Resource alignment if it is specified.
2514 * Zero if it is not specified.
2516 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2518 int seg
, bus
, slot
, func
, align_order
, count
;
2519 resource_size_t align
= 0;
2522 spin_lock(&resource_alignment_lock
);
2523 p
= resource_alignment_param
;
2526 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2532 if (sscanf(p
, "%x:%x:%x.%x%n",
2533 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2535 if (sscanf(p
, "%x:%x.%x%n",
2536 &bus
, &slot
, &func
, &count
) != 3) {
2537 /* Invalid format */
2538 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2544 if (seg
== pci_domain_nr(dev
->bus
) &&
2545 bus
== dev
->bus
->number
&&
2546 slot
== PCI_SLOT(dev
->devfn
) &&
2547 func
== PCI_FUNC(dev
->devfn
)) {
2548 if (align_order
== -1) {
2551 align
= 1 << align_order
;
2556 if (*p
!= ';' && *p
!= ',') {
2557 /* End of param or invalid format */
2562 spin_unlock(&resource_alignment_lock
);
2567 * pci_is_reassigndev - check if specified PCI is target device to reassign
2568 * @dev: the PCI device to check
2570 * RETURNS: non-zero for PCI device is a target device to reassign,
2573 int pci_is_reassigndev(struct pci_dev
*dev
)
2575 return (pci_specified_resource_alignment(dev
) != 0);
2578 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2580 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2581 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2582 spin_lock(&resource_alignment_lock
);
2583 strncpy(resource_alignment_param
, buf
, count
);
2584 resource_alignment_param
[count
] = '\0';
2585 spin_unlock(&resource_alignment_lock
);
2589 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2592 spin_lock(&resource_alignment_lock
);
2593 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2594 spin_unlock(&resource_alignment_lock
);
2598 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2600 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2603 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2604 const char *buf
, size_t count
)
2606 return pci_set_resource_alignment_param(buf
, count
);
2609 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2610 pci_resource_alignment_store
);
2612 static int __init
pci_resource_alignment_sysfs_init(void)
2614 return bus_create_file(&pci_bus_type
,
2615 &bus_attr_resource_alignment
);
2618 late_initcall(pci_resource_alignment_sysfs_init
);
2620 static void __devinit
pci_no_domains(void)
2622 #ifdef CONFIG_PCI_DOMAINS
2623 pci_domains_supported
= 0;
2628 * pci_ext_cfg_enabled - can we access extended PCI config space?
2629 * @dev: The PCI device of the root bridge.
2631 * Returns 1 if we can access PCI extended config space (offsets
2632 * greater than 0xff). This is the default implementation. Architecture
2633 * implementations can override this.
2635 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2640 static int __devinit
pci_init(void)
2642 struct pci_dev
*dev
= NULL
;
2644 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2645 pci_fixup_device(pci_fixup_final
, dev
);
2651 static int __init
pci_setup(char *str
)
2654 char *k
= strchr(str
, ',');
2657 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2658 if (!strcmp(str
, "nomsi")) {
2660 } else if (!strcmp(str
, "noaer")) {
2662 } else if (!strcmp(str
, "nodomains")) {
2664 } else if (!strncmp(str
, "cbiosize=", 9)) {
2665 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2666 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2667 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2668 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2669 pci_set_resource_alignment_param(str
+ 19,
2671 } else if (!strncmp(str
, "ecrc=", 5)) {
2672 pcie_ecrc_get_policy(str
+ 5);
2674 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2682 early_param("pci", pci_setup
);
2684 device_initcall(pci_init
);
2686 EXPORT_SYMBOL(pci_reenable_device
);
2687 EXPORT_SYMBOL(pci_enable_device_io
);
2688 EXPORT_SYMBOL(pci_enable_device_mem
);
2689 EXPORT_SYMBOL(pci_enable_device
);
2690 EXPORT_SYMBOL(pcim_enable_device
);
2691 EXPORT_SYMBOL(pcim_pin_device
);
2692 EXPORT_SYMBOL(pci_disable_device
);
2693 EXPORT_SYMBOL(pci_find_capability
);
2694 EXPORT_SYMBOL(pci_bus_find_capability
);
2695 EXPORT_SYMBOL(pci_release_regions
);
2696 EXPORT_SYMBOL(pci_request_regions
);
2697 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2698 EXPORT_SYMBOL(pci_release_region
);
2699 EXPORT_SYMBOL(pci_request_region
);
2700 EXPORT_SYMBOL(pci_request_region_exclusive
);
2701 EXPORT_SYMBOL(pci_release_selected_regions
);
2702 EXPORT_SYMBOL(pci_request_selected_regions
);
2703 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2704 EXPORT_SYMBOL(pci_set_master
);
2705 EXPORT_SYMBOL(pci_clear_master
);
2706 EXPORT_SYMBOL(pci_set_mwi
);
2707 EXPORT_SYMBOL(pci_try_set_mwi
);
2708 EXPORT_SYMBOL(pci_clear_mwi
);
2709 EXPORT_SYMBOL_GPL(pci_intx
);
2710 EXPORT_SYMBOL(pci_set_dma_mask
);
2711 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2712 EXPORT_SYMBOL(pci_assign_resource
);
2713 EXPORT_SYMBOL(pci_find_parent_resource
);
2714 EXPORT_SYMBOL(pci_select_bars
);
2716 EXPORT_SYMBOL(pci_set_power_state
);
2717 EXPORT_SYMBOL(pci_save_state
);
2718 EXPORT_SYMBOL(pci_restore_state
);
2719 EXPORT_SYMBOL(pci_pme_capable
);
2720 EXPORT_SYMBOL(pci_pme_active
);
2721 EXPORT_SYMBOL(pci_enable_wake
);
2722 EXPORT_SYMBOL(pci_wake_from_d3
);
2723 EXPORT_SYMBOL(pci_target_state
);
2724 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2725 EXPORT_SYMBOL(pci_back_from_sleep
);
2726 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);