drivers/mtd/nand/atmel_nand.c

   1 /*
   2  *  Copyright (C) 2003 Rick Bronson
   3  *
   4  *  Derived from drivers/mtd/nand/autcpu12.c
   5  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
   6  *
   7  *  Derived from drivers/mtd/spia.c
   8  *       Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
   9  *
  10  *
  11  *  Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  12  *     Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
  13  *
  14  *     Derived from Das U-Boot source code
  15  *              (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  16  *     (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  17  *
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  *
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/nand.h>
  30 #include <linux/mtd/partitions.h>
  31
  32 #include <linux/gpio.h>
  33 #include <linux/io.h>
  34
  35 #include <mach/board.h>
  36 #include <mach/cpu.h>
  37
  38 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
  39 #define hard_ecc        1
  40 #else
  41 #define hard_ecc        0
  42 #endif
  43
  44 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
  45 #define no_ecc          1
  46 #else
  47 #define no_ecc          0
  48 #endif
  49
  50 /* Register access macros */
  51 #define ecc_readl(add, reg)                             \
  52         __raw_readl(add + ATMEL_ECC_##reg)
  53 #define ecc_writel(add, reg, value)                     \
  54         __raw_writel((value), add + ATMEL_ECC_##reg)
  55
  56 #include "atmel_nand_ecc.h"     /* Hardware ECC registers */
  57
  58 /* oob layout for large page size
  59  * bad block info is on bytes 0 and 1
  60  * the bytes have to be consecutives to avoid
  61  * several NAND_CMD_RNDOUT during read
  62  */
  63 static struct nand_ecclayout atmel_oobinfo_large = {
  64         .eccbytes = 4,
  65         .eccpos = {60, 61, 62, 63},
  66         .oobfree = {
  67                 {2, 58}
  68         },
  69 };
  70
  71 /* oob layout for small page size
  72  * bad block info is on bytes 4 and 5
  73  * the bytes have to be consecutives to avoid
  74  * several NAND_CMD_RNDOUT during read
  75  */
  76 static struct nand_ecclayout atmel_oobinfo_small = {
  77         .eccbytes = 4,
  78         .eccpos = {0, 1, 2, 3},
  79         .oobfree = {
  80                 {6, 10}
  81         },
  82 };
  83
  84 struct atmel_nand_host {
  85         struct nand_chip        nand_chip;
  86         struct mtd_info         mtd;
  87         void __iomem            *io_base;
  88         struct atmel_nand_data  *board;
  89         struct device           *dev;
  90         void __iomem            *ecc;
  91 };
  92
  93 /*
  94  * Enable NAND.
  95  */
  96 static void atmel_nand_enable(struct atmel_nand_host *host)
  97 {
  98         if (host->board->enable_pin)
  99                 gpio_set_value(host->board->enable_pin, 0);
 100 }
 101
 102 /*
 103  * Disable NAND.
 104  */
 105 static void atmel_nand_disable(struct atmel_nand_host *host)
 106 {
 107         if (host->board->enable_pin)
 108                 gpio_set_value(host->board->enable_pin, 1);
 109 }
 110
 111 /*
 112  * Hardware specific access to control-lines
 113  */
 114 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 115 {
 116         struct nand_chip *nand_chip = mtd->priv;
 117         struct atmel_nand_host *host = nand_chip->priv;
 118
 119         if (ctrl & NAND_CTRL_CHANGE) {
 120                 if (ctrl & NAND_NCE)
 121                         atmel_nand_enable(host);
 122                 else
 123                         atmel_nand_disable(host);
 124         }
 125         if (cmd == NAND_CMD_NONE)
 126                 return;
 127
 128         if (ctrl & NAND_CLE)
 129                 writeb(cmd, host->io_base + (1 << host->board->cle));
 130         else
 131                 writeb(cmd, host->io_base + (1 << host->board->ale));
 132 }
 133
 134 /*
 135  * Read the Device Ready pin.
 136  */
 137 static int atmel_nand_device_ready(struct mtd_info *mtd)
 138 {
 139         struct nand_chip *nand_chip = mtd->priv;
 140         struct atmel_nand_host *host = nand_chip->priv;
 141
 142         return gpio_get_value(host->board->rdy_pin) ^
 143                 !!host->board->rdy_pin_active_low;
 144 }
 145
 146 /*
 147  * Minimal-overhead PIO for data access.
 148  */
 149 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 150 {
 151         struct nand_chip        *nand_chip = mtd->priv;
 152
 153         __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
 154 }
 155
 156 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
 157 {
 158         struct nand_chip        *nand_chip = mtd->priv;
 159
 160         __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
 161 }
 162
 163 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 164 {
 165         struct nand_chip        *nand_chip = mtd->priv;
 166
 167         __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
 168 }
 169
 170 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
 171 {
 172         struct nand_chip        *nand_chip = mtd->priv;
 173
 174         __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
 175 }
 176
 177 /*
 178  * Calculate HW ECC
 179  *
 180  * function called after a write
 181  *
 182  * mtd:        MTD block structure
 183  * dat:        raw data (unused)
 184  * ecc_code:   buffer for ECC
 185  */
 186 static int atmel_nand_calculate(struct mtd_info *mtd,
 187                 const u_char *dat, unsigned char *ecc_code)
 188 {
 189         struct nand_chip *nand_chip = mtd->priv;
 190         struct atmel_nand_host *host = nand_chip->priv;
 191         uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
 192         unsigned int ecc_value;
 193
 194         /* get the first 2 ECC bytes */
 195         ecc_value = ecc_readl(host->ecc, PR);
 196
 197         ecc_code[0] = ecc_value & 0xFF;
 198         ecc_code[1] = (ecc_value >> 8) & 0xFF;
 199
 200         /* get the last 2 ECC bytes */
 201         ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
 202
 203         ecc_code[2] = ecc_value & 0xFF;
 204         ecc_code[3] = (ecc_value >> 8) & 0xFF;
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * HW ECC read page function
 211  *
 212  * mtd:        mtd info structure
 213  * chip:       nand chip info structure
 214  * buf:        buffer to store read data
 215  */
 216 static int atmel_nand_read_page(struct mtd_info *mtd,
 217                 struct nand_chip *chip, uint8_t *buf)
 218 {
 219         int eccsize = chip->ecc.size;
 220         int eccbytes = chip->ecc.bytes;
 221         uint32_t *eccpos = chip->ecc.layout->eccpos;
 222         uint8_t *p = buf;
 223         uint8_t *oob = chip->oob_poi;
 224         uint8_t *ecc_pos;
 225         int stat;
 226
 227         /*
 228          * Errata: ALE is incorrectly wired up to the ECC controller
 229          * on the AP7000, so it will include the address cycles in the
 230          * ECC calculation.
 231          *
 232          * Workaround: Reset the parity registers before reading the
 233          * actual data.
 234          */
 235         if (cpu_is_at32ap7000()) {
 236                 struct atmel_nand_host *host = chip->priv;
 237                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
 238         }
 239
 240         /* read the page */
 241         chip->read_buf(mtd, p, eccsize);
 242
 243         /* move to ECC position if needed */
 244         if (eccpos[0] != 0) {
 245                 /* This only works on large pages
 246                  * because the ECC controller waits for
 247                  * NAND_CMD_RNDOUTSTART after the
 248                  * NAND_CMD_RNDOUT.
 249                  * anyway, for small pages, the eccpos[0] == 0
 250                  */
 251                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 252                                 mtd->writesize + eccpos[0], -1);
 253         }
 254
 255         /* the ECC controller needs to read the ECC just after the data */
 256         ecc_pos = oob + eccpos[0];
 257         chip->read_buf(mtd, ecc_pos, eccbytes);
 258
 259         /* check if there's an error */
 260         stat = chip->ecc.correct(mtd, p, oob, NULL);
 261
 262         if (stat < 0)
 263                 mtd->ecc_stats.failed++;
 264         else
 265                 mtd->ecc_stats.corrected += stat;
 266
 267         /* get back to oob start (end of page) */
 268         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 269
 270         /* read the oob */
 271         chip->read_buf(mtd, oob, mtd->oobsize);
 272
 273         return 0;
 274 }
 275
 276 /*
 277  * HW ECC Correction
 278  *
 279  * function called after a read
 280  *
 281  * mtd:        MTD block structure
 282  * dat:        raw data read from the chip
 283  * read_ecc:   ECC from the chip (unused)
 284  * isnull:     unused
 285  *
 286  * Detect and correct a 1 bit error for a page
 287  */
 288 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 289                 u_char *read_ecc, u_char *isnull)
 290 {
 291         struct nand_chip *nand_chip = mtd->priv;
 292         struct atmel_nand_host *host = nand_chip->priv;
 293         unsigned int ecc_status;
 294         unsigned int ecc_word, ecc_bit;
 295
 296         /* get the status from the Status Register */
 297         ecc_status = ecc_readl(host->ecc, SR);
 298
 299         /* if there's no error */
 300         if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
 301                 return 0;
 302
 303         /* get error bit offset (4 bits) */
 304         ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
 305         /* get word address (12 bits) */
 306         ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
 307         ecc_word >>= 4;
 308
 309         /* if there are multiple errors */
 310         if (ecc_status & ATMEL_ECC_MULERR) {
 311                 /* check if it is a freshly erased block
 312                  * (filled with 0xff) */
 313                 if ((ecc_bit == ATMEL_ECC_BITADDR)
 314                                 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
 315                         /* the block has just been erased, return OK */
 316                         return 0;
 317                 }
 318                 /* it doesn't seems to be a freshly
 319                  * erased block.
 320                  * We can't correct so many errors */
 321                 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
 322                                 " Unable to correct.\n");
 323                 return -EIO;
 324         }
 325
 326         /* if there's a single bit error : we can correct it */
 327         if (ecc_status & ATMEL_ECC_ECCERR) {
 328                 /* there's nothing much to do here.
 329                  * the bit error is on the ECC itself.
 330                  */
 331                 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
 332                                 " Nothing to correct\n");
 333                 return 0;
 334         }
 335
 336         dev_dbg(host->dev, "atmel_nand : one bit error on data."
 337                         " (word offset in the page :"
 338                         " 0x%x bit offset : 0x%x)\n",
 339                         ecc_word, ecc_bit);
 340         /* correct the error */
 341         if (nand_chip->options & NAND_BUSWIDTH_16) {
 342                 /* 16 bits words */
 343                 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
 344         } else {
 345                 /* 8 bits words */
 346                 dat[ecc_word] ^= (1 << ecc_bit);
 347         }
 348         dev_dbg(host->dev, "atmel_nand : error corrected\n");
 349         return 1;
 350 }
 351
 352 /*
 353  * Enable HW ECC : unused on most chips
 354  */
 355 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
 356 {
 357         if (cpu_is_at32ap7000()) {
 358                 struct nand_chip *nand_chip = mtd->priv;
 359                 struct atmel_nand_host *host = nand_chip->priv;
 360                 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
 361         }
 362 }
 363
 364 #ifdef CONFIG_MTD_PARTITIONS
 365 static const char *part_probes[] = { "cmdlinepart", NULL };
 366 #endif
 367
 368 /*
 369  * Probe for the NAND device.
 370  */
 371 static int __init atmel_nand_probe(struct platform_device *pdev)
 372 {
 373         struct atmel_nand_host *host;
 374         struct mtd_info *mtd;
 375         struct nand_chip *nand_chip;
 376         struct resource *regs;
 377         struct resource *mem;
 378         int res;
 379
 380 #ifdef CONFIG_MTD_PARTITIONS
 381         struct mtd_partition *partitions = NULL;
 382         int num_partitions = 0;
 383 #endif
 384
 385         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 386         if (!mem) {
 387                 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
 388                 return -ENXIO;
 389         }
 390
 391         /* Allocate memory for the device structure (and zero it) */
 392         host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
 393         if (!host) {
 394                 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
 395                 return -ENOMEM;
 396         }
 397
 398         host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
 399         if (host->io_base == NULL) {
 400                 printk(KERN_ERR "atmel_nand: ioremap failed\n");
 401                 res = -EIO;
 402                 goto err_nand_ioremap;
 403         }
 404
 405         mtd = &host->mtd;
 406         nand_chip = &host->nand_chip;
 407         host->board = pdev->dev.platform_data;
 408         host->dev = &pdev->dev;
 409
 410         nand_chip->priv = host;         /* link the private data structures */
 411         mtd->priv = nand_chip;
 412         mtd->owner = THIS_MODULE;
 413
 414         /* Set address of NAND IO lines */
 415         nand_chip->IO_ADDR_R = host->io_base;
 416         nand_chip->IO_ADDR_W = host->io_base;
 417         nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
 418
 419         if (host->board->rdy_pin)
 420                 nand_chip->dev_ready = atmel_nand_device_ready;
 421
 422         regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 423         if (!regs && hard_ecc) {
 424                 printk(KERN_ERR "atmel_nand: can't get I/O resource "
 425                                 "regs\nFalling back on software ECC\n");
 426         }
 427
 428         nand_chip->ecc.mode = NAND_ECC_SOFT;    /* enable ECC */
 429         if (no_ecc)
 430                 nand_chip->ecc.mode = NAND_ECC_NONE;
 431         if (hard_ecc && regs) {
 432                 host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
 433                 if (host->ecc == NULL) {
 434                         printk(KERN_ERR "atmel_nand: ioremap failed\n");
 435                         res = -EIO;
 436                         goto err_ecc_ioremap;
 437                 }
 438                 nand_chip->ecc.mode = NAND_ECC_HW;
 439                 nand_chip->ecc.calculate = atmel_nand_calculate;
 440                 nand_chip->ecc.correct = atmel_nand_correct;
 441                 nand_chip->ecc.hwctl = atmel_nand_hwctl;
 442                 nand_chip->ecc.read_page = atmel_nand_read_page;
 443                 nand_chip->ecc.bytes = 4;
 444         }
 445
 446         nand_chip->chip_delay = 20;             /* 20us command delay time */
 447
 448         if (host->board->bus_width_16) {        /* 16-bit bus width */
 449                 nand_chip->options |= NAND_BUSWIDTH_16;
 450                 nand_chip->read_buf = atmel_read_buf16;
 451                 nand_chip->write_buf = atmel_write_buf16;
 452         } else {
 453                 nand_chip->read_buf = atmel_read_buf;
 454                 nand_chip->write_buf = atmel_write_buf;
 455         }
 456
 457         platform_set_drvdata(pdev, host);
 458         atmel_nand_enable(host);
 459
 460         if (host->board->det_pin) {
 461                 if (gpio_get_value(host->board->det_pin)) {
 462                         printk("No SmartMedia card inserted.\n");
 463                         res = ENXIO;
 464                         goto err_no_card;
 465                 }
 466         }
 467
 468         /* first scan to find the device and get the page size */
 469         if (nand_scan_ident(mtd, 1)) {
 470                 res = -ENXIO;
 471                 goto err_scan_ident;
 472         }
 473
 474         if (nand_chip->ecc.mode == NAND_ECC_HW) {
 475                 /* ECC is calculated for the whole page (1 step) */
 476                 nand_chip->ecc.size = mtd->writesize;
 477
 478                 /* set ECC page size and oob layout */
 479                 switch (mtd->writesize) {
 480                 case 512:
 481                         nand_chip->ecc.layout = &atmel_oobinfo_small;
 482                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
 483                         break;
 484                 case 1024:
 485                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 486                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
 487                         break;
 488                 case 2048:
 489                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 490                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
 491                         break;
 492                 case 4096:
 493                         nand_chip->ecc.layout = &atmel_oobinfo_large;
 494                         ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
 495                         break;
 496                 default:
 497                         /* page size not handled by HW ECC */
 498                         /* switching back to soft ECC */
 499                         nand_chip->ecc.mode = NAND_ECC_SOFT;
 500                         nand_chip->ecc.calculate = NULL;
 501                         nand_chip->ecc.correct = NULL;
 502                         nand_chip->ecc.hwctl = NULL;
 503                         nand_chip->ecc.read_page = NULL;
 504                         nand_chip->ecc.postpad = 0;
 505                         nand_chip->ecc.prepad = 0;
 506                         nand_chip->ecc.bytes = 0;
 507                         break;
 508                 }
 509         }
 510
 511         /* second phase scan */
 512         if (nand_scan_tail(mtd)) {
 513                 res = -ENXIO;
 514                 goto err_scan_tail;
 515         }
 516
 517 #ifdef CONFIG_MTD_PARTITIONS
 518 #ifdef CONFIG_MTD_CMDLINE_PARTS
 519         mtd->name = "atmel_nand";
 520         num_partitions = parse_mtd_partitions(mtd, part_probes,
 521                                               &partitions, 0);
 522 #endif
 523         if (num_partitions <= 0 && host->board->partition_info)
 524                 partitions = host->board->partition_info(mtd->size,
 525                                                          &num_partitions);
 526
 527         if ((!partitions) || (num_partitions == 0)) {
 528                 printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
 529                 res = ENXIO;
 530                 goto err_no_partitions;
 531         }
 532
 533         res = add_mtd_partitions(mtd, partitions, num_partitions);
 534 #else
 535         res = add_mtd_device(mtd);
 536 #endif
 537
 538         if (!res)
 539                 return res;
 540
 541 #ifdef CONFIG_MTD_PARTITIONS
 542 err_no_partitions:
 543 #endif
 544         nand_release(mtd);
 545 err_scan_tail:
 546 err_scan_ident:
 547 err_no_card:
 548         atmel_nand_disable(host);
 549         platform_set_drvdata(pdev, NULL);
 550         if (host->ecc)
 551                 iounmap(host->ecc);
 552 err_ecc_ioremap:
 553         iounmap(host->io_base);
 554 err_nand_ioremap:
 555         kfree(host);
 556         return res;
 557 }
 558
 559 /*
 560  * Remove a NAND device.
 561  */
 562 static int __exit atmel_nand_remove(struct platform_device *pdev)
 563 {
 564         struct atmel_nand_host *host = platform_get_drvdata(pdev);
 565         struct mtd_info *mtd = &host->mtd;
 566
 567         nand_release(mtd);
 568
 569         atmel_nand_disable(host);
 570
 571         if (host->ecc)
 572                 iounmap(host->ecc);
 573         iounmap(host->io_base);
 574         kfree(host);
 575
 576         return 0;
 577 }
 578
 579 static struct platform_driver atmel_nand_driver = {
 580         .remove         = __exit_p(atmel_nand_remove),
 581         .driver         = {
 582                 .name   = "atmel_nand",
 583                 .owner  = THIS_MODULE,
 584         },
 585 };
 586
 587 static int __init atmel_nand_init(void)
 588 {
 589         return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
 590 }
 591
 592
 593 static void __exit atmel_nand_exit(void)
 594 {
 595         platform_driver_unregister(&atmel_nand_driver);
 596 }
 597
 598
 599 module_init(atmel_nand_init);
 600 module_exit(atmel_nand_exit);
 601
 602 MODULE_LICENSE("GPL");
 603 MODULE_AUTHOR("Rick Bronson");
 604 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
 605 MODULE_ALIAS("platform:atmel_nand");