sound/soc/pxa/pxa2xx-i2s.c

   1 /*
   2  * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
   3  *
   4  * Copyright 2005 Wolfson Microelectronics PLC.
   5  * Author: Liam Girdwood
   6  *         lrg@slimlogic.co.uk
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/device.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/platform_device.h>
  20 #include <sound/core.h>
  21 #include <sound/pcm.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24 #include <sound/pxa2xx-lib.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/dma.h>
  28 #include <mach/audio.h>
  29
  30 #include "pxa2xx-pcm.h"
  31 #include "pxa2xx-i2s.h"
  32
  33 /*
  34  * I2S Controller Register and Bit Definitions
  35  */
  36 #define SACR0           __REG(0x40400000)  /* Global Control Register */
  37 #define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
  38 #define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
  39 #define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
  40 #define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
  41 #define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
  42 #define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
  43
  44 #define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
  45 #define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
  46 #define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
  47 #define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
  48 #define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
  49 #define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
  50 #define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
  51 #define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
  52 #define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
  53 #define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
  54 #define SACR1_AMSL      (1 << 0)        /* Specify Alternate Mode */
  55
  56 #define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
  57 #define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
  58 #define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
  59 #define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
  60 #define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
  61 #define SASR0_BSY       (1 << 2)        /* I2S Busy */
  62 #define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
  63 #define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
  64
  65 #define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
  66 #define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
  67
  68 #define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
  69 #define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
  70 #define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
  71 #define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
  72
  73 struct pxa_i2s_port {
  74         u32 sadiv;
  75         u32 sacr0;
  76         u32 sacr1;
  77         u32 saimr;
  78         int master;
  79         u32 fmt;
  80 };
  81 static struct pxa_i2s_port pxa_i2s;
  82 static struct clk *clk_i2s;
  83
  84 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  85         .name                   = "I2S PCM Stereo out",
  86         .dev_addr               = __PREG(SADR),
  87         .drcmr                  = &DRCMR(3),
  88         .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  89                                   DCMD_BURST32 | DCMD_WIDTH4,
  90 };
  91
  92 static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  93         .name                   = "I2S PCM Stereo in",
  94         .dev_addr               = __PREG(SADR),
  95         .drcmr                  = &DRCMR(2),
  96         .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  97                                   DCMD_BURST32 | DCMD_WIDTH4,
  98 };
  99
 100 static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
 101                               struct snd_soc_dai *dai)
 102 {
 103         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 104         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 105
 106         if (IS_ERR(clk_i2s))
 107                 return PTR_ERR(clk_i2s);
 108
 109         if (!cpu_dai->active)
 110                 SACR0 = 0;
 111
 112         return 0;
 113 }
 114
 115 /* wait for I2S controller to be ready */
 116 static int pxa_i2s_wait(void)
 117 {
 118         int i;
 119
 120         /* flush the Rx FIFO */
 121         for(i = 0; i < 16; i++)
 122                 SADR;
 123         return 0;
 124 }
 125
 126 static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 127                 unsigned int fmt)
 128 {
 129         /* interface format */
 130         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 131         case SND_SOC_DAIFMT_I2S:
 132                 pxa_i2s.fmt = 0;
 133                 break;
 134         case SND_SOC_DAIFMT_LEFT_J:
 135                 pxa_i2s.fmt = SACR1_AMSL;
 136                 break;
 137         }
 138
 139         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 140         case SND_SOC_DAIFMT_CBS_CFS:
 141                 pxa_i2s.master = 1;
 142                 break;
 143         case SND_SOC_DAIFMT_CBM_CFS:
 144                 pxa_i2s.master = 0;
 145                 break;
 146         default:
 147                 break;
 148         }
 149         return 0;
 150 }
 151
 152 static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 153                 int clk_id, unsigned int freq, int dir)
 154 {
 155         if (clk_id != PXA2XX_I2S_SYSCLK)
 156                 return -ENODEV;
 157
 158         return 0;
 159 }
 160
 161 static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
 162                                 struct snd_pcm_hw_params *params,
 163                                 struct snd_soc_dai *dai)
 164 {
 165         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 166         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 167
 168         BUG_ON(IS_ERR(clk_i2s));
 169         clk_enable(clk_i2s);
 170         pxa_i2s_wait();
 171
 172         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 173                 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
 174         else
 175                 cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
 176
 177         /* is port used by another stream */
 178         if (!(SACR0 & SACR0_ENB)) {
 179                 SACR0 = 0;
 180                 if (pxa_i2s.master)
 181                         SACR0 |= SACR0_BCKD;
 182
 183                 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
 184                 SACR1 |= pxa_i2s.fmt;
 185         }
 186         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 187                 SAIMR |= SAIMR_TFS;
 188         else
 189                 SAIMR |= SAIMR_RFS;
 190
 191         switch (params_rate(params)) {
 192         case 8000:
 193                 SADIV = 0x48;
 194                 break;
 195         case 11025:
 196                 SADIV = 0x34;
 197                 break;
 198         case 16000:
 199                 SADIV = 0x24;
 200                 break;
 201         case 22050:
 202                 SADIV = 0x1a;
 203                 break;
 204         case 44100:
 205                 SADIV = 0xd;
 206                 break;
 207         case 48000:
 208                 SADIV = 0xc;
 209                 break;
 210         case 96000: /* not in manual and possibly slightly inaccurate */
 211                 SADIV = 0x6;
 212                 break;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 219                               struct snd_soc_dai *dai)
 220 {
 221         int ret = 0;
 222
 223         switch (cmd) {
 224         case SNDRV_PCM_TRIGGER_START:
 225                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 226                         SACR1 &= ~SACR1_DRPL;
 227                 else
 228                         SACR1 &= ~SACR1_DREC;
 229                 SACR0 |= SACR0_ENB;
 230                 break;
 231         case SNDRV_PCM_TRIGGER_RESUME:
 232         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 233         case SNDRV_PCM_TRIGGER_STOP:
 234         case SNDRV_PCM_TRIGGER_SUSPEND:
 235         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 236                 break;
 237         default:
 238                 ret = -EINVAL;
 239         }
 240
 241         return ret;
 242 }
 243
 244 static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
 245                                 struct snd_soc_dai *dai)
 246 {
 247         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 248                 SACR1 |= SACR1_DRPL;
 249                 SAIMR &= ~SAIMR_TFS;
 250         } else {
 251                 SACR1 |= SACR1_DREC;
 252                 SAIMR &= ~SAIMR_RFS;
 253         }
 254
 255         if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
 256                 SACR0 &= ~SACR0_ENB;
 257                 pxa_i2s_wait();
 258                 clk_disable(clk_i2s);
 259         }
 260 }
 261
 262 #ifdef CONFIG_PM
 263 static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
 264 {
 265         /* store registers */
 266         pxa_i2s.sacr0 = SACR0;
 267         pxa_i2s.sacr1 = SACR1;
 268         pxa_i2s.saimr = SAIMR;
 269         pxa_i2s.sadiv = SADIV;
 270
 271         /* deactivate link */
 272         SACR0 &= ~SACR0_ENB;
 273         pxa_i2s_wait();
 274         return 0;
 275 }
 276
 277 static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
 278 {
 279         pxa_i2s_wait();
 280
 281         SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
 282         SACR1 = pxa_i2s.sacr1;
 283         SAIMR = pxa_i2s.saimr;
 284         SADIV = pxa_i2s.sadiv;
 285
 286         SACR0 = pxa_i2s.sacr0;
 287
 288         return 0;
 289 }
 290
 291 #else
 292 #define pxa2xx_i2s_suspend      NULL
 293 #define pxa2xx_i2s_resume       NULL
 294 #endif
 295
 296 #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 297                 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
 298                 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
 299
 300 static struct snd_soc_dai_ops pxa_i2s_dai_ops = {
 301         .startup        = pxa2xx_i2s_startup,
 302         .shutdown       = pxa2xx_i2s_shutdown,
 303         .trigger        = pxa2xx_i2s_trigger,
 304         .hw_params      = pxa2xx_i2s_hw_params,
 305         .set_fmt        = pxa2xx_i2s_set_dai_fmt,
 306         .set_sysclk     = pxa2xx_i2s_set_dai_sysclk,
 307 };
 308
 309 struct snd_soc_dai pxa_i2s_dai = {
 310         .name = "pxa2xx-i2s",
 311         .id = 0,
 312         .suspend = pxa2xx_i2s_suspend,
 313         .resume = pxa2xx_i2s_resume,
 314         .playback = {
 315                 .channels_min = 2,
 316                 .channels_max = 2,
 317                 .rates = PXA2XX_I2S_RATES,
 318                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 319         .capture = {
 320                 .channels_min = 2,
 321                 .channels_max = 2,
 322                 .rates = PXA2XX_I2S_RATES,
 323                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 324         .ops = &pxa_i2s_dai_ops,
 325         .symmetric_rates = 1,
 326 };
 327
 328 EXPORT_SYMBOL_GPL(pxa_i2s_dai);
 329
 330 static int pxa2xx_i2s_probe(struct platform_device *dev)
 331 {
 332         int ret;
 333
 334         clk_i2s = clk_get(&dev->dev, "I2SCLK");
 335         if (IS_ERR(clk_i2s))
 336                 return PTR_ERR(clk_i2s);
 337
 338         pxa_i2s_dai.dev = &dev->dev;
 339         ret = snd_soc_register_dai(&pxa_i2s_dai);
 340         if (ret != 0)
 341                 clk_put(clk_i2s);
 342
 343         /*
 344          * PXA Developer's Manual:
 345          * If SACR0[ENB] is toggled in the middle of a normal operation,
 346          * the SACR0[RST] bit must also be set and cleared to reset all
 347          * I2S controller registers.
 348          */
 349         SACR0 = SACR0_RST;
 350         SACR0 = 0;
 351         /* Make sure RPL and REC are disabled */
 352         SACR1 = SACR1_DRPL | SACR1_DREC;
 353         /* Along with FIFO servicing */
 354         SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
 355
 356         return ret;
 357 }
 358
 359 static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
 360 {
 361         snd_soc_unregister_dai(&pxa_i2s_dai);
 362         clk_put(clk_i2s);
 363         clk_i2s = ERR_PTR(-ENOENT);
 364         return 0;
 365 }
 366
 367 static struct platform_driver pxa2xx_i2s_driver = {
 368         .probe = pxa2xx_i2s_probe,
 369         .remove = __devexit_p(pxa2xx_i2s_remove),
 370
 371         .driver = {
 372                 .name = "pxa2xx-i2s",
 373                 .owner = THIS_MODULE,
 374         },
 375 };
 376
 377 static int __init pxa2xx_i2s_init(void)
 378 {
 379         clk_i2s = ERR_PTR(-ENOENT);
 380         return platform_driver_register(&pxa2xx_i2s_driver);
 381 }
 382
 383 static void __exit pxa2xx_i2s_exit(void)
 384 {
 385         platform_driver_unregister(&pxa2xx_i2s_driver);
 386 }
 387
 388 module_init(pxa2xx_i2s_init);
 389 module_exit(pxa2xx_i2s_exit);
 390
 391 /* Module information */
 392 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
 393 MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
 394 MODULE_LICENSE("GPL");