?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MIPS: handle write_combine in pci_mmap_page_range
[linux-2.6/linux-loongson.git] / drivers / usb / musb / musb_host.c
blobdb1b57415ec7ad2a443d35cce7a8202de2f4bfef
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44
45 #include "musb_core.h"
46 #include "musb_host.h"
47
48
49 /* MUSB HOST status 22-mar-2006
50 *
51 * - There's still lots of partial code duplication for fault paths, so
52 * they aren't handled as consistently as they need to be.
53 *
54 * - PIO mostly behaved when last tested.
55 * + including ep0, with all usbtest cases 9, 10
56 * + usbtest 14 (ep0out) doesn't seem to run at all
57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
58 * configurations, but otherwise double buffering passes basic tests.
59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 *
61 * - DMA (CPPI) ... partially behaves, not currently recommended
62 * + about 1/15 the speed of typical EHCI implementations (PCI)
63 * + RX, all too often reqpkt seems to misbehave after tx
64 * + TX, no known issues (other than evident silicon issue)
65 *
66 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 *
68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
69 * starvation ... nothing yet for TX, interrupt, or bulk.
70 *
71 * - Not tested with HNP, but some SRP paths seem to behave.
72 *
73 * NOTE 24-August-2006:
74 *
75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
76 * extra endpoint for periodic use enabling hub + keybd + mouse. That
77 * mostly works, except that with "usbnet" it's easy to trigger cases
78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
80 * although ARP RX wins. (That test was done with a full speed link.)
81 */
82
83
84 /*
85 * NOTE on endpoint usage:
86 *
87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
89 * (Yes, bulk _could_ use more of the endpoints than that, and would even
90 * benefit from it.)
91 *
92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
93 * So far that scheduling is both dumb and optimistic: the endpoint will be
94 * "claimed" until its software queue is no longer refilled. No multiplexing
95 * of transfers between endpoints, or anything clever.
96 */
97
98
99 static void musb_ep_program(struct musb *musb, u8 epnum,
100 struct urb *urb, int is_out,
101 u8 *buf, u32 offset, u32 len);
102
103 /*
104 * Clear TX fifo. Needed to avoid BABBLE errors.
105 */
106 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
107 {
108 void __iomem *epio = ep->regs;
109 u16 csr;
110 u16 lastcsr = 0;
111 int retries = 1000;
112
113 csr = musb_readw(epio, MUSB_TXCSR);
114 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
115 if (csr != lastcsr)
116 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
117 lastcsr = csr;
118 csr |= MUSB_TXCSR_FLUSHFIFO;
119 musb_writew(epio, MUSB_TXCSR, csr);
120 csr = musb_readw(epio, MUSB_TXCSR);
121 if (WARN(retries-- < 1,
122 "Could not flush host TX%d fifo: csr: %04x\n",
123 ep->epnum, csr))
124 return;
125 mdelay(1);
126 }
127 }
128
129 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
130 {
131 void __iomem *epio = ep->regs;
132 u16 csr;
133 int retries = 5;
134
135 /* scrub any data left in the fifo */
136 do {
137 csr = musb_readw(epio, MUSB_TXCSR);
138 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
139 break;
140 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
141 csr = musb_readw(epio, MUSB_TXCSR);
142 udelay(10);
143 } while (--retries);
144
145 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
146 ep->epnum, csr);
147
148 /* and reset for the next transfer */
149 musb_writew(epio, MUSB_TXCSR, 0);
150 }
151
152 /*
153 * Start transmit. Caller is responsible for locking shared resources.
154 * musb must be locked.
155 */
156 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
157 {
158 u16 txcsr;
159
160 /* NOTE: no locks here; caller should lock and select EP */
161 if (ep->epnum) {
162 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
163 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
164 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
165 } else {
166 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
167 musb_writew(ep->regs, MUSB_CSR0, txcsr);
168 }
169
170 }
171
172 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
173 {
174 u16 txcsr;
175
176 /* NOTE: no locks here; caller should lock and select EP */
177 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
178 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
179 if (is_cppi_enabled())
180 txcsr |= MUSB_TXCSR_DMAMODE;
181 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
182 }
183
184 /*
185 * Start the URB at the front of an endpoint's queue
186 * end must be claimed from the caller.
187 *
188 * Context: controller locked, irqs blocked
189 */
190 static void
191 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
192 {
193 u16 frame;
194 u32 len;
195 void __iomem *mbase = musb->mregs;
196 struct urb *urb = next_urb(qh);
197 void *buf = urb->transfer_buffer;
198 u32 offset = 0;
199 struct musb_hw_ep *hw_ep = qh->hw_ep;
200 unsigned pipe = urb->pipe;
201 u8 address = usb_pipedevice(pipe);
202 int epnum = hw_ep->epnum;
203
204 /* initialize software qh state */
205 qh->offset = 0;
206 qh->segsize = 0;
207
208 /* gather right source of data */
209 switch (qh->type) {
210 case USB_ENDPOINT_XFER_CONTROL:
211 /* control transfers always start with SETUP */
212 is_in = 0;
213 hw_ep->out_qh = qh;
214 musb->ep0_stage = MUSB_EP0_START;
215 buf = urb->setup_packet;
216 len = 8;
217 break;
218 case USB_ENDPOINT_XFER_ISOC:
219 qh->iso_idx = 0;
220 qh->frame = 0;
221 offset = urb->iso_frame_desc[0].offset;
222 len = urb->iso_frame_desc[0].length;
223 break;
224 default: /* bulk, interrupt */
225 /* actual_length may be nonzero on retry paths */
226 buf = urb->transfer_buffer + urb->actual_length;
227 len = urb->transfer_buffer_length - urb->actual_length;
228 }
229
230 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
231 qh, urb, address, qh->epnum,
232 is_in ? "in" : "out",
233 ({char *s; switch (qh->type) {
234 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
235 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
236 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
237 default: s = "-intr"; break;
238 }; s; }),
239 epnum, buf + offset, len);
240
241 /* Configure endpoint */
242 if (is_in || hw_ep->is_shared_fifo)
243 hw_ep->in_qh = qh;
244 else
245 hw_ep->out_qh = qh;
246 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
247
248 /* transmit may have more work: start it when it is time */
249 if (is_in)
250 return;
251
252 /* determine if the time is right for a periodic transfer */
253 switch (qh->type) {
254 case USB_ENDPOINT_XFER_ISOC:
255 case USB_ENDPOINT_XFER_INT:
256 DBG(3, "check whether there's still time for periodic Tx\n");
257 frame = musb_readw(mbase, MUSB_FRAME);
258 /* FIXME this doesn't implement that scheduling policy ...
259 * or handle framecounter wrapping
260 */
261 if ((urb->transfer_flags & URB_ISO_ASAP)
262 || (frame >= urb->start_frame)) {
263 /* REVISIT the SOF irq handler shouldn't duplicate
264 * this code; and we don't init urb->start_frame...
265 */
266 qh->frame = 0;
267 goto start;
268 } else {
269 qh->frame = urb->start_frame;
270 /* enable SOF interrupt so we can count down */
271 DBG(1, "SOF for %d\n", epnum);
272 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
273 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
274 #endif
275 }
276 break;
277 default:
278 start:
279 DBG(4, "Start TX%d %s\n", epnum,
280 hw_ep->tx_channel ? "dma" : "pio");
281
282 if (!hw_ep->tx_channel)
283 musb_h_tx_start(hw_ep);
284 else if (is_cppi_enabled() || tusb_dma_omap())
285 musb_h_tx_dma_start(hw_ep);
286 }
287 }
288
289 /* caller owns controller lock, irqs are blocked */
290 static void
291 __musb_giveback(struct musb *musb, struct urb *urb, int status)
292 __releases(musb->lock)
293 __acquires(musb->lock)
294 {
295 DBG(({ int level; switch (status) {
296 case 0:
297 level = 4;
298 break;
299 /* common/boring faults */
300 case -EREMOTEIO:
301 case -ESHUTDOWN:
302 case -ECONNRESET:
303 case -EPIPE:
304 level = 3;
305 break;
306 default:
307 level = 2;
308 break;
309 }; level; }),
310 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
311 urb, urb->complete, status,
312 usb_pipedevice(urb->pipe),
313 usb_pipeendpoint(urb->pipe),
314 usb_pipein(urb->pipe) ? "in" : "out",
315 urb->actual_length, urb->transfer_buffer_length
316 );
317
318 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
319 spin_unlock(&musb->lock);
320 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
321 spin_lock(&musb->lock);
322 }
323
324 /* for bulk/interrupt endpoints only */
325 static inline void
326 musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
327 {
328 struct usb_device *udev = urb->dev;
329 u16 csr;
330 void __iomem *epio = ep->regs;
331 struct musb_qh *qh;
332
333 /* FIXME: the current Mentor DMA code seems to have
334 * problems getting toggle correct.
335 */
336
337 if (is_in || ep->is_shared_fifo)
338 qh = ep->in_qh;
339 else
340 qh = ep->out_qh;
341
342 if (!is_in) {
343 csr = musb_readw(epio, MUSB_TXCSR);
344 usb_settoggle(udev, qh->epnum, 1,
345 (csr & MUSB_TXCSR_H_DATATOGGLE)
346 ? 1 : 0);
347 } else {
348 csr = musb_readw(epio, MUSB_RXCSR);
349 usb_settoggle(udev, qh->epnum, 0,
350 (csr & MUSB_RXCSR_H_DATATOGGLE)
351 ? 1 : 0);
352 }
353 }
354
355 /* caller owns controller lock, irqs are blocked */
356 static struct musb_qh *
357 musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
358 {
359 struct musb_hw_ep *ep = qh->hw_ep;
360 struct musb *musb = ep->musb;
361 int is_in = usb_pipein(urb->pipe);
362 int ready = qh->is_ready;
363
364 /* save toggle eagerly, for paranoia */
365 switch (qh->type) {
366 case USB_ENDPOINT_XFER_BULK:
367 case USB_ENDPOINT_XFER_INT:
368 musb_save_toggle(ep, is_in, urb);
369 break;
370 case USB_ENDPOINT_XFER_ISOC:
371 if (status == 0 && urb->error_count)
372 status = -EXDEV;
373 break;
374 }
375
376 qh->is_ready = 0;
377 __musb_giveback(musb, urb, status);
378 qh->is_ready = ready;
379
380 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
381 * invalidate qh as soon as list_empty(&hep->urb_list)
382 */
383 if (list_empty(&qh->hep->urb_list)) {
384 struct list_head *head;
385
386 if (is_in)
387 ep->rx_reinit = 1;
388 else
389 ep->tx_reinit = 1;
390
391 /* clobber old pointers to this qh */
392 if (is_in || ep->is_shared_fifo)
393 ep->in_qh = NULL;
394 else
395 ep->out_qh = NULL;
396 qh->hep->hcpriv = NULL;
397
398 switch (qh->type) {
399
400 case USB_ENDPOINT_XFER_CONTROL:
401 case USB_ENDPOINT_XFER_BULK:
402 /* fifo policy for these lists, except that NAKing
403 * should rotate a qh to the end (for fairness).
404 */
405 if (qh->mux == 1) {
406 head = qh->ring.prev;
407 list_del(&qh->ring);
408 kfree(qh);
409 qh = first_qh(head);
410 break;
411 }
412
413 case USB_ENDPOINT_XFER_ISOC:
414 case USB_ENDPOINT_XFER_INT:
415 /* this is where periodic bandwidth should be
416 * de-allocated if it's tracked and allocated;
417 * and where we'd update the schedule tree...
418 */
419 kfree(qh);
420 qh = NULL;
421 break;
422 }
423 }
424 return qh;
425 }
426
427 /*
428 * Advance this hardware endpoint's queue, completing the specified urb and
429 * advancing to either the next urb queued to that qh, or else invalidating
430 * that qh and advancing to the next qh scheduled after the current one.
431 *
432 * Context: caller owns controller lock, irqs are blocked
433 */
434 static void
435 musb_advance_schedule(struct musb *musb, struct urb *urb,
436 struct musb_hw_ep *hw_ep, int is_in)
437 {
438 struct musb_qh *qh;
439
440 if (is_in || hw_ep->is_shared_fifo)
441 qh = hw_ep->in_qh;
442 else
443 qh = hw_ep->out_qh;
444
445 if (urb->status == -EINPROGRESS)
446 qh = musb_giveback(qh, urb, 0);
447 else
448 qh = musb_giveback(qh, urb, urb->status);
449
450 if (qh != NULL && qh->is_ready) {
451 DBG(4, "... next ep%d %cX urb %p\n",
452 hw_ep->epnum, is_in ? 'R' : 'T',
453 next_urb(qh));
454 musb_start_urb(musb, is_in, qh);
455 }
456 }
457
458 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
459 {
460 /* we don't want fifo to fill itself again;
461 * ignore dma (various models),
462 * leave toggle alone (may not have been saved yet)
463 */
464 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
465 csr &= ~(MUSB_RXCSR_H_REQPKT
466 | MUSB_RXCSR_H_AUTOREQ
467 | MUSB_RXCSR_AUTOCLEAR);
468
469 /* write 2x to allow double buffering */
470 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
471 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
472
473 /* flush writebuffer */
474 return musb_readw(hw_ep->regs, MUSB_RXCSR);
475 }
476
477 /*
478 * PIO RX for a packet (or part of it).
479 */
480 static bool
481 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
482 {
483 u16 rx_count;
484 u8 *buf;
485 u16 csr;
486 bool done = false;
487 u32 length;
488 int do_flush = 0;
489 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
490 void __iomem *epio = hw_ep->regs;
491 struct musb_qh *qh = hw_ep->in_qh;
492 int pipe = urb->pipe;
493 void *buffer = urb->transfer_buffer;
494
495 /* musb_ep_select(mbase, epnum); */
496 rx_count = musb_readw(epio, MUSB_RXCOUNT);
497 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
498 urb->transfer_buffer, qh->offset,
499 urb->transfer_buffer_length);
500
501 /* unload FIFO */
502 if (usb_pipeisoc(pipe)) {
503 int status = 0;
504 struct usb_iso_packet_descriptor *d;
505
506 if (iso_err) {
507 status = -EILSEQ;
508 urb->error_count++;
509 }
510
511 d = urb->iso_frame_desc + qh->iso_idx;
512 buf = buffer + d->offset;
513 length = d->length;
514 if (rx_count > length) {
515 if (status == 0) {
516 status = -EOVERFLOW;
517 urb->error_count++;
518 }
519 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
520 do_flush = 1;
521 } else
522 length = rx_count;
523 urb->actual_length += length;
524 d->actual_length = length;
525
526 d->status = status;
527
528 /* see if we are done */
529 done = (++qh->iso_idx >= urb->number_of_packets);
530 } else {
531 /* non-isoch */
532 buf = buffer + qh->offset;
533 length = urb->transfer_buffer_length - qh->offset;
534 if (rx_count > length) {
535 if (urb->status == -EINPROGRESS)
536 urb->status = -EOVERFLOW;
537 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
538 do_flush = 1;
539 } else
540 length = rx_count;
541 urb->actual_length += length;
542 qh->offset += length;
543
544 /* see if we are done */
545 done = (urb->actual_length == urb->transfer_buffer_length)
546 || (rx_count < qh->maxpacket)
547 || (urb->status != -EINPROGRESS);
548 if (done
549 && (urb->status == -EINPROGRESS)
550 && (urb->transfer_flags & URB_SHORT_NOT_OK)
551 && (urb->actual_length
552 < urb->transfer_buffer_length))
553 urb->status = -EREMOTEIO;
554 }
555
556 musb_read_fifo(hw_ep, length, buf);
557
558 csr = musb_readw(epio, MUSB_RXCSR);
559 csr |= MUSB_RXCSR_H_WZC_BITS;
560 if (unlikely(do_flush))
561 musb_h_flush_rxfifo(hw_ep, csr);
562 else {
563 /* REVISIT this assumes AUTOCLEAR is never set */
564 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
565 if (!done)
566 csr |= MUSB_RXCSR_H_REQPKT;
567 musb_writew(epio, MUSB_RXCSR, csr);
568 }
569
570 return done;
571 }
572
573 /* we don't always need to reinit a given side of an endpoint...
574 * when we do, use tx/rx reinit routine and then construct a new CSR
575 * to address data toggle, NYET, and DMA or PIO.
576 *
577 * it's possible that driver bugs (especially for DMA) or aborting a
578 * transfer might have left the endpoint busier than it should be.
579 * the busy/not-empty tests are basically paranoia.
580 */
581 static void
582 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
583 {
584 u16 csr;
585
586 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
587 * That always uses tx_reinit since ep0 repurposes TX register
588 * offsets; the initial SETUP packet is also a kind of OUT.
589 */
590
591 /* if programmed for Tx, put it in RX mode */
592 if (ep->is_shared_fifo) {
593 csr = musb_readw(ep->regs, MUSB_TXCSR);
594 if (csr & MUSB_TXCSR_MODE) {
595 musb_h_tx_flush_fifo(ep);
596 csr = musb_readw(ep->regs, MUSB_TXCSR);
597 musb_writew(ep->regs, MUSB_TXCSR,
598 csr | MUSB_TXCSR_FRCDATATOG);
599 }
600
601 /*
602 * Clear the MODE bit (and everything else) to enable Rx.
603 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
604 */
605 if (csr & MUSB_TXCSR_DMAMODE)
606 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
607 musb_writew(ep->regs, MUSB_TXCSR, 0);
608
609 /* scrub all previous state, clearing toggle */
610 } else {
611 csr = musb_readw(ep->regs, MUSB_RXCSR);
612 if (csr & MUSB_RXCSR_RXPKTRDY)
613 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
614 musb_readw(ep->regs, MUSB_RXCOUNT));
615
616 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
617 }
618
619 /* target addr and (for multipoint) hub addr/port */
620 if (musb->is_multipoint) {
621 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
622 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
623 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
624
625 } else
626 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
627
628 /* protocol/endpoint, interval/NAKlimit, i/o size */
629 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
630 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
631 /* NOTE: bulk combining rewrites high bits of maxpacket */
632 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
633
634 ep->rx_reinit = 0;
635 }
636
637 static bool musb_tx_dma_program(struct dma_controller *dma,
638 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
639 struct urb *urb, u32 offset, u32 length)
640 {
641 struct dma_channel *channel = hw_ep->tx_channel;
642 void __iomem *epio = hw_ep->regs;
643 u16 pkt_size = qh->maxpacket;
644 u16 csr;
645 u8 mode;
646
647 #ifdef CONFIG_USB_INVENTRA_DMA
648 if (length > channel->max_len)
649 length = channel->max_len;
650
651 csr = musb_readw(epio, MUSB_TXCSR);
652 if (length > pkt_size) {
653 mode = 1;
654 csr |= MUSB_TXCSR_AUTOSET
655 | MUSB_TXCSR_DMAMODE
656 | MUSB_TXCSR_DMAENAB;
657 } else {
658 mode = 0;
659 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
660 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
661 }
662 channel->desired_mode = mode;
663 musb_writew(epio, MUSB_TXCSR, csr);
664 #else
665 if (!is_cppi_enabled() && !tusb_dma_omap())
666 return false;
667
668 channel->actual_len = 0;
669
670 /*
671 * TX uses "RNDIS" mode automatically but needs help
672 * to identify the zero-length-final-packet case.
673 */
674 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
675 #endif
676
677 qh->segsize = length;
678
679 if (!dma->channel_program(channel, pkt_size, mode,
680 urb->transfer_dma + offset, length)) {
681 dma->channel_release(channel);
682 hw_ep->tx_channel = NULL;
683
684 csr = musb_readw(epio, MUSB_TXCSR);
685 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
686 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
687 return false;
688 }
689 return true;
690 }
691
692 /*
693 * Program an HDRC endpoint as per the given URB
694 * Context: irqs blocked, controller lock held
695 */
696 static void musb_ep_program(struct musb *musb, u8 epnum,
697 struct urb *urb, int is_out,
698 u8 *buf, u32 offset, u32 len)
699 {
700 struct dma_controller *dma_controller;
701 struct dma_channel *dma_channel;
702 u8 dma_ok;
703 void __iomem *mbase = musb->mregs;
704 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
705 void __iomem *epio = hw_ep->regs;
706 struct musb_qh *qh;
707 u16 packet_sz;
708
709 if (!is_out || hw_ep->is_shared_fifo)
710 qh = hw_ep->in_qh;
711 else
712 qh = hw_ep->out_qh;
713
714 packet_sz = qh->maxpacket;
715
716 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
717 "h_addr%02x h_port%02x bytes %d\n",
718 is_out ? "-->" : "<--",
719 epnum, urb, urb->dev->speed,
720 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
721 qh->h_addr_reg, qh->h_port_reg,
722 len);
723
724 musb_ep_select(mbase, epnum);
725
726 /* candidate for DMA? */
727 dma_controller = musb->dma_controller;
728 if (is_dma_capable() && epnum && dma_controller) {
729 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
730 if (!dma_channel) {
731 dma_channel = dma_controller->channel_alloc(
732 dma_controller, hw_ep, is_out);
733 if (is_out)
734 hw_ep->tx_channel = dma_channel;
735 else
736 hw_ep->rx_channel = dma_channel;
737 }
738 } else
739 dma_channel = NULL;
740
741 /* make sure we clear DMAEnab, autoSet bits from previous run */
742
743 /* OUT/transmit/EP0 or IN/receive? */
744 if (is_out) {
745 u16 csr;
746 u16 int_txe;
747 u16 load_count;
748
749 csr = musb_readw(epio, MUSB_TXCSR);
750
751 /* disable interrupt in case we flush */
752 int_txe = musb_readw(mbase, MUSB_INTRTXE);
753 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
754
755 /* general endpoint setup */
756 if (epnum) {
757 /* flush all old state, set default */
758 musb_h_tx_flush_fifo(hw_ep);
759
760 /*
761 * We must not clear the DMAMODE bit before or in
762 * the same cycle with the DMAENAB bit, so we clear
763 * the latter first...
764 */
765 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
766 | MUSB_TXCSR_AUTOSET
767 | MUSB_TXCSR_DMAENAB
768 | MUSB_TXCSR_FRCDATATOG
769 | MUSB_TXCSR_H_RXSTALL
770 | MUSB_TXCSR_H_ERROR
771 | MUSB_TXCSR_TXPKTRDY
772 );
773 csr |= MUSB_TXCSR_MODE;
774
775 if (usb_gettoggle(urb->dev, qh->epnum, 1))
776 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
777 | MUSB_TXCSR_H_DATATOGGLE;
778 else
779 csr |= MUSB_TXCSR_CLRDATATOG;
780
781 musb_writew(epio, MUSB_TXCSR, csr);
782 /* REVISIT may need to clear FLUSHFIFO ... */
783 csr &= ~MUSB_TXCSR_DMAMODE;
784 musb_writew(epio, MUSB_TXCSR, csr);
785 csr = musb_readw(epio, MUSB_TXCSR);
786 } else {
787 /* endpoint 0: just flush */
788 musb_h_ep0_flush_fifo(hw_ep);
789 }
790
791 /* target addr and (for multipoint) hub addr/port */
792 if (musb->is_multipoint) {
793 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
794 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
795 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
796 /* FIXME if !epnum, do the same for RX ... */
797 } else
798 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
799
800 /* protocol/endpoint/interval/NAKlimit */
801 if (epnum) {
802 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
803 if (can_bulk_split(musb, qh->type))
804 musb_writew(epio, MUSB_TXMAXP,
805 packet_sz
806 | ((hw_ep->max_packet_sz_tx /
807 packet_sz) - 1) << 11);
808 else
809 musb_writew(epio, MUSB_TXMAXP,
810 packet_sz);
811 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
812 } else {
813 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
814 if (musb->is_multipoint)
815 musb_writeb(epio, MUSB_TYPE0,
816 qh->type_reg);
817 }
818
819 if (can_bulk_split(musb, qh->type))
820 load_count = min((u32) hw_ep->max_packet_sz_tx,
821 len);
822 else
823 load_count = min((u32) packet_sz, len);
824
825 if (dma_channel && musb_tx_dma_program(dma_controller,
826 hw_ep, qh, urb, offset, len))
827 load_count = 0;
828
829 if (load_count) {
830 /* PIO to load FIFO */
831 qh->segsize = load_count;
832 musb_write_fifo(hw_ep, load_count, buf);
833 }
834
835 /* re-enable interrupt */
836 musb_writew(mbase, MUSB_INTRTXE, int_txe);
837
838 /* IN/receive */
839 } else {
840 u16 csr;
841
842 if (hw_ep->rx_reinit) {
843 musb_rx_reinit(musb, qh, hw_ep);
844
845 /* init new state: toggle and NYET, maybe DMA later */
846 if (usb_gettoggle(urb->dev, qh->epnum, 0))
847 csr = MUSB_RXCSR_H_WR_DATATOGGLE
848 | MUSB_RXCSR_H_DATATOGGLE;
849 else
850 csr = 0;
851 if (qh->type == USB_ENDPOINT_XFER_INT)
852 csr |= MUSB_RXCSR_DISNYET;
853
854 } else {
855 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
856
857 if (csr & (MUSB_RXCSR_RXPKTRDY
858 | MUSB_RXCSR_DMAENAB
859 | MUSB_RXCSR_H_REQPKT))
860 ERR("broken !rx_reinit, ep%d csr %04x\n",
861 hw_ep->epnum, csr);
862
863 /* scrub any stale state, leaving toggle alone */
864 csr &= MUSB_RXCSR_DISNYET;
865 }
866
867 /* kick things off */
868
869 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
870 /* candidate for DMA */
871 if (dma_channel) {
872 dma_channel->actual_len = 0L;
873 qh->segsize = len;
874
875 /* AUTOREQ is in a DMA register */
876 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
877 csr = musb_readw(hw_ep->regs,
878 MUSB_RXCSR);
879
880 /* unless caller treats short rx transfers as
881 * errors, we dare not queue multiple transfers.
882 */
883 dma_ok = dma_controller->channel_program(
884 dma_channel, packet_sz,
885 !(urb->transfer_flags
886 & URB_SHORT_NOT_OK),
887 urb->transfer_dma + offset,
888 qh->segsize);
889 if (!dma_ok) {
890 dma_controller->channel_release(
891 dma_channel);
892 hw_ep->rx_channel = NULL;
893 dma_channel = NULL;
894 } else
895 csr |= MUSB_RXCSR_DMAENAB;
896 }
897 }
898
899 csr |= MUSB_RXCSR_H_REQPKT;
900 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
901 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
902 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
903 }
904 }
905
906
907 /*
908 * Service the default endpoint (ep0) as host.
909 * Return true until it's time to start the status stage.
910 */
911 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
912 {
913 bool more = false;
914 u8 *fifo_dest = NULL;
915 u16 fifo_count = 0;
916 struct musb_hw_ep *hw_ep = musb->control_ep;
917 struct musb_qh *qh = hw_ep->in_qh;
918 struct usb_ctrlrequest *request;
919
920 switch (musb->ep0_stage) {
921 case MUSB_EP0_IN:
922 fifo_dest = urb->transfer_buffer + urb->actual_length;
923 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
924 urb->actual_length);
925 if (fifo_count < len)
926 urb->status = -EOVERFLOW;
927
928 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
929
930 urb->actual_length += fifo_count;
931 if (len < qh->maxpacket) {
932 /* always terminate on short read; it's
933 * rarely reported as an error.
934 */
935 } else if (urb->actual_length <
936 urb->transfer_buffer_length)
937 more = true;
938 break;
939 case MUSB_EP0_START:
940 request = (struct usb_ctrlrequest *) urb->setup_packet;
941
942 if (!request->wLength) {
943 DBG(4, "start no-DATA\n");
944 break;
945 } else if (request->bRequestType & USB_DIR_IN) {
946 DBG(4, "start IN-DATA\n");
947 musb->ep0_stage = MUSB_EP0_IN;
948 more = true;
949 break;
950 } else {
951 DBG(4, "start OUT-DATA\n");
952 musb->ep0_stage = MUSB_EP0_OUT;
953 more = true;
954 }
955 /* FALLTHROUGH */
956 case MUSB_EP0_OUT:
957 fifo_count = min_t(size_t, qh->maxpacket,
958 urb->transfer_buffer_length -
959 urb->actual_length);
960 if (fifo_count) {
961 fifo_dest = (u8 *) (urb->transfer_buffer
962 + urb->actual_length);
963 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
964 fifo_count,
965 (fifo_count == 1) ? "" : "s",
966 fifo_dest);
967 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
968
969 urb->actual_length += fifo_count;
970 more = true;
971 }
972 break;
973 default:
974 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
975 break;
976 }
977
978 return more;
979 }
980
981 /*
982 * Handle default endpoint interrupt as host. Only called in IRQ time
983 * from musb_interrupt().
984 *
985 * called with controller irqlocked
986 */
987 irqreturn_t musb_h_ep0_irq(struct musb *musb)
988 {
989 struct urb *urb;
990 u16 csr, len;
991 int status = 0;
992 void __iomem *mbase = musb->mregs;
993 struct musb_hw_ep *hw_ep = musb->control_ep;
994 void __iomem *epio = hw_ep->regs;
995 struct musb_qh *qh = hw_ep->in_qh;
996 bool complete = false;
997 irqreturn_t retval = IRQ_NONE;
998
999 /* ep0 only has one queue, "in" */
1000 urb = next_urb(qh);
1001
1002 musb_ep_select(mbase, 0);
1003 csr = musb_readw(epio, MUSB_CSR0);
1004 len = (csr & MUSB_CSR0_RXPKTRDY)
1005 ? musb_readb(epio, MUSB_COUNT0)
1006 : 0;
1007
1008 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1009 csr, qh, len, urb, musb->ep0_stage);
1010
1011 /* if we just did status stage, we are done */
1012 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1013 retval = IRQ_HANDLED;
1014 complete = true;
1015 }
1016
1017 /* prepare status */
1018 if (csr & MUSB_CSR0_H_RXSTALL) {
1019 DBG(6, "STALLING ENDPOINT\n");
1020 status = -EPIPE;
1021
1022 } else if (csr & MUSB_CSR0_H_ERROR) {
1023 DBG(2, "no response, csr0 %04x\n", csr);
1024 status = -EPROTO;
1025
1026 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1027 DBG(2, "control NAK timeout\n");
1028
1029 /* NOTE: this code path would be a good place to PAUSE a
1030 * control transfer, if another one is queued, so that
1031 * ep0 is more likely to stay busy. That's already done
1032 * for bulk RX transfers.
1033 *
1034 * if (qh->ring.next != &musb->control), then
1035 * we have a candidate... NAKing is *NOT* an error
1036 */
1037 musb_writew(epio, MUSB_CSR0, 0);
1038 retval = IRQ_HANDLED;
1039 }
1040
1041 if (status) {
1042 DBG(6, "aborting\n");
1043 retval = IRQ_HANDLED;
1044 if (urb)
1045 urb->status = status;
1046 complete = true;
1047
1048 /* use the proper sequence to abort the transfer */
1049 if (csr & MUSB_CSR0_H_REQPKT) {
1050 csr &= ~MUSB_CSR0_H_REQPKT;
1051 musb_writew(epio, MUSB_CSR0, csr);
1052 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1053 musb_writew(epio, MUSB_CSR0, csr);
1054 } else {
1055 musb_h_ep0_flush_fifo(hw_ep);
1056 }
1057
1058 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1059
1060 /* clear it */
1061 musb_writew(epio, MUSB_CSR0, 0);
1062 }
1063
1064 if (unlikely(!urb)) {
1065 /* stop endpoint since we have no place for its data, this
1066 * SHOULD NEVER HAPPEN! */
1067 ERR("no URB for end 0\n");
1068
1069 musb_h_ep0_flush_fifo(hw_ep);
1070 goto done;
1071 }
1072
1073 if (!complete) {
1074 /* call common logic and prepare response */
1075 if (musb_h_ep0_continue(musb, len, urb)) {
1076 /* more packets required */
1077 csr = (MUSB_EP0_IN == musb->ep0_stage)
1078 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1079 } else {
1080 /* data transfer complete; perform status phase */
1081 if (usb_pipeout(urb->pipe)
1082 || !urb->transfer_buffer_length)
1083 csr = MUSB_CSR0_H_STATUSPKT
1084 | MUSB_CSR0_H_REQPKT;
1085 else
1086 csr = MUSB_CSR0_H_STATUSPKT
1087 | MUSB_CSR0_TXPKTRDY;
1088
1089 /* flag status stage */
1090 musb->ep0_stage = MUSB_EP0_STATUS;
1091
1092 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1093
1094 }
1095 musb_writew(epio, MUSB_CSR0, csr);
1096 retval = IRQ_HANDLED;
1097 } else
1098 musb->ep0_stage = MUSB_EP0_IDLE;
1099
1100 /* call completion handler if done */
1101 if (complete)
1102 musb_advance_schedule(musb, urb, hw_ep, 1);
1103 done:
1104 return retval;
1105 }
1106
1107
1108 #ifdef CONFIG_USB_INVENTRA_DMA
1109
1110 /* Host side TX (OUT) using Mentor DMA works as follows:
1111 submit_urb ->
1112 - if queue was empty, Program Endpoint
1113 - ... which starts DMA to fifo in mode 1 or 0
1114
1115 DMA Isr (transfer complete) -> TxAvail()
1116 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1117 only in musb_cleanup_urb)
1118 - TxPktRdy has to be set in mode 0 or for
1119 short packets in mode 1.
1120 */
1121
1122 #endif
1123
1124 /* Service a Tx-Available or dma completion irq for the endpoint */
1125 void musb_host_tx(struct musb *musb, u8 epnum)
1126 {
1127 int pipe;
1128 bool done = false;
1129 u16 tx_csr;
1130 size_t length = 0;
1131 size_t offset = 0;
1132 struct urb *urb;
1133 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1134 void __iomem *epio = hw_ep->regs;
1135 struct musb_qh *qh = hw_ep->is_shared_fifo ? hw_ep->in_qh
1136 : hw_ep->out_qh;
1137 u32 status = 0;
1138 void __iomem *mbase = musb->mregs;
1139 struct dma_channel *dma;
1140
1141 urb = next_urb(qh);
1142
1143 musb_ep_select(mbase, epnum);
1144 tx_csr = musb_readw(epio, MUSB_TXCSR);
1145
1146 /* with CPPI, DMA sometimes triggers "extra" irqs */
1147 if (!urb) {
1148 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1149 return;
1150 }
1151
1152 pipe = urb->pipe;
1153 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1154 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1155 dma ? ", dma" : "");
1156
1157 /* check for errors */
1158 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1159 /* dma was disabled, fifo flushed */
1160 DBG(3, "TX end %d stall\n", epnum);
1161
1162 /* stall; record URB status */
1163 status = -EPIPE;
1164
1165 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1166 /* (NON-ISO) dma was disabled, fifo flushed */
1167 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1168
1169 status = -ETIMEDOUT;
1170
1171 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1172 DBG(6, "TX end=%d device not responding\n", epnum);
1173
1174 /* NOTE: this code path would be a good place to PAUSE a
1175 * transfer, if there's some other (nonperiodic) tx urb
1176 * that could use this fifo. (dma complicates it...)
1177 * That's already done for bulk RX transfers.
1178 *
1179 * if (bulk && qh->ring.next != &musb->out_bulk), then
1180 * we have a candidate... NAKing is *NOT* an error
1181 */
1182 musb_ep_select(mbase, epnum);
1183 musb_writew(epio, MUSB_TXCSR,
1184 MUSB_TXCSR_H_WZC_BITS
1185 | MUSB_TXCSR_TXPKTRDY);
1186 return;
1187 }
1188
1189 if (status) {
1190 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1191 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1192 (void) musb->dma_controller->channel_abort(dma);
1193 }
1194
1195 /* do the proper sequence to abort the transfer in the
1196 * usb core; the dma engine should already be stopped.
1197 */
1198 musb_h_tx_flush_fifo(hw_ep);
1199 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1200 | MUSB_TXCSR_DMAENAB
1201 | MUSB_TXCSR_H_ERROR
1202 | MUSB_TXCSR_H_RXSTALL
1203 | MUSB_TXCSR_H_NAKTIMEOUT
1204 );
1205
1206 musb_ep_select(mbase, epnum);
1207 musb_writew(epio, MUSB_TXCSR, tx_csr);
1208 /* REVISIT may need to clear FLUSHFIFO ... */
1209 musb_writew(epio, MUSB_TXCSR, tx_csr);
1210 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1211
1212 done = true;
1213 }
1214
1215 /* second cppi case */
1216 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1217 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1218 return;
1219 }
1220
1221 if (is_dma_capable() && dma && !status) {
1222 /*
1223 * DMA has completed. But if we're using DMA mode 1 (multi
1224 * packet DMA), we need a terminal TXPKTRDY interrupt before
1225 * we can consider this transfer completed, lest we trash
1226 * its last packet when writing the next URB's data. So we
1227 * switch back to mode 0 to get that interrupt; we'll come
1228 * back here once it happens.
1229 */
1230 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1231 /*
1232 * We shouldn't clear DMAMODE with DMAENAB set; so
1233 * clear them in a safe order. That should be OK
1234 * once TXPKTRDY has been set (and I've never seen
1235 * it being 0 at this moment -- DMA interrupt latency
1236 * is significant) but if it hasn't been then we have
1237 * no choice but to stop being polite and ignore the
1238 * programmer's guide... :-)
1239 *
1240 * Note that we must write TXCSR with TXPKTRDY cleared
1241 * in order not to re-trigger the packet send (this bit
1242 * can't be cleared by CPU), and there's another caveat:
1243 * TXPKTRDY may be set shortly and then cleared in the
1244 * double-buffered FIFO mode, so we do an extra TXCSR
1245 * read for debouncing...
1246 */
1247 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1248 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1249 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1250 MUSB_TXCSR_TXPKTRDY);
1251 musb_writew(epio, MUSB_TXCSR,
1252 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1253 }
1254 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1255 MUSB_TXCSR_TXPKTRDY);
1256 musb_writew(epio, MUSB_TXCSR,
1257 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1258
1259 /*
1260 * There is no guarantee that we'll get an interrupt
1261 * after clearing DMAMODE as we might have done this
1262 * too late (after TXPKTRDY was cleared by controller).
1263 * Re-read TXCSR as we have spoiled its previous value.
1264 */
1265 tx_csr = musb_readw(epio, MUSB_TXCSR);
1266 }
1267
1268 /*
1269 * We may get here from a DMA completion or TXPKTRDY interrupt.
1270 * In any case, we must check the FIFO status here and bail out
1271 * only if the FIFO still has data -- that should prevent the
1272 * "missed" TXPKTRDY interrupts and deal with double-buffered
1273 * FIFO mode too...
1274 */
1275 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1276 DBG(2, "DMA complete but packet still in FIFO, "
1277 "CSR %04x\n", tx_csr);
1278 return;
1279 }
1280 }
1281
1282 if (!status || dma || usb_pipeisoc(pipe)) {
1283 if (dma)
1284 length = dma->actual_len;
1285 else
1286 length = qh->segsize;
1287 qh->offset += length;
1288
1289 if (usb_pipeisoc(pipe)) {
1290 struct usb_iso_packet_descriptor *d;
1291
1292 d = urb->iso_frame_desc + qh->iso_idx;
1293 d->actual_length = length;
1294 d->status = status;
1295 if (++qh->iso_idx >= urb->number_of_packets) {
1296 done = true;
1297 } else {
1298 d++;
1299 offset = d->offset;
1300 length = d->length;
1301 }
1302 } else if (dma) {
1303 done = true;
1304 } else {
1305 /* see if we need to send more data, or ZLP */
1306 if (qh->segsize < qh->maxpacket)
1307 done = true;
1308 else if (qh->offset == urb->transfer_buffer_length
1309 && !(urb->transfer_flags
1310 & URB_ZERO_PACKET))
1311 done = true;
1312 if (!done) {
1313 offset = qh->offset;
1314 length = urb->transfer_buffer_length - offset;
1315 }
1316 }
1317 }
1318
1319 /* urb->status != -EINPROGRESS means request has been faulted,
1320 * so we must abort this transfer after cleanup
1321 */
1322 if (urb->status != -EINPROGRESS) {
1323 done = true;
1324 if (status == 0)
1325 status = urb->status;
1326 }
1327
1328 if (done) {
1329 /* set status */
1330 urb->status = status;
1331 urb->actual_length = qh->offset;
1332 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1333 return;
1334 } else if (usb_pipeisoc(pipe) && dma) {
1335 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1336 offset, length))
1337 return;
1338 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1339 DBG(1, "not complete, but DMA enabled?\n");
1340 return;
1341 }
1342
1343 /*
1344 * PIO: start next packet in this URB.
1345 *
1346 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1347 * (and presumably, FIFO is not half-full) we should write *two*
1348 * packets before updating TXCSR; other docs disagree...
1349 */
1350 if (length > qh->maxpacket)
1351 length = qh->maxpacket;
1352 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1353 qh->segsize = length;
1354
1355 musb_ep_select(mbase, epnum);
1356 musb_writew(epio, MUSB_TXCSR,
1357 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1358 }
1359
1360
1361 #ifdef CONFIG_USB_INVENTRA_DMA
1362
1363 /* Host side RX (IN) using Mentor DMA works as follows:
1364 submit_urb ->
1365 - if queue was empty, ProgramEndpoint
1366 - first IN token is sent out (by setting ReqPkt)
1367 LinuxIsr -> RxReady()
1368 /\ => first packet is received
1369 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1370 | -> DMA Isr (transfer complete) -> RxReady()
1371 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1372 | - if urb not complete, send next IN token (ReqPkt)
1373 | | else complete urb.
1374 | |
1375 ---------------------------
1376 *
1377 * Nuances of mode 1:
1378 * For short packets, no ack (+RxPktRdy) is sent automatically
1379 * (even if AutoClear is ON)
1380 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1381 * automatically => major problem, as collecting the next packet becomes
1382 * difficult. Hence mode 1 is not used.
1383 *
1384 * REVISIT
1385 * All we care about at this driver level is that
1386 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1387 * (b) termination conditions are: short RX, or buffer full;
1388 * (c) fault modes include
1389 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1390 * (and that endpoint's dma queue stops immediately)
1391 * - overflow (full, PLUS more bytes in the terminal packet)
1392 *
1393 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1394 * thus be a great candidate for using mode 1 ... for all but the
1395 * last packet of one URB's transfer.
1396 */
1397
1398 #endif
1399
1400 /* Schedule next QH from musb->in_bulk and move the current qh to
1401 * the end; avoids starvation for other endpoints.
1402 */
1403 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1404 {
1405 struct dma_channel *dma;
1406 struct urb *urb;
1407 void __iomem *mbase = musb->mregs;
1408 void __iomem *epio = ep->regs;
1409 struct musb_qh *cur_qh, *next_qh;
1410 u16 rx_csr;
1411
1412 musb_ep_select(mbase, ep->epnum);
1413 dma = is_dma_capable() ? ep->rx_channel : NULL;
1414
1415 /* clear nak timeout bit */
1416 rx_csr = musb_readw(epio, MUSB_RXCSR);
1417 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1418 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1419 musb_writew(epio, MUSB_RXCSR, rx_csr);
1420
1421 cur_qh = first_qh(&musb->in_bulk);
1422 if (cur_qh) {
1423 urb = next_urb(cur_qh);
1424 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1425 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1426 musb->dma_controller->channel_abort(dma);
1427 urb->actual_length += dma->actual_len;
1428 dma->actual_len = 0L;
1429 }
1430 musb_save_toggle(ep, 1, urb);
1431
1432 /* move cur_qh to end of queue */
1433 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1434
1435 /* get the next qh from musb->in_bulk */
1436 next_qh = first_qh(&musb->in_bulk);
1437
1438 /* set rx_reinit and schedule the next qh */
1439 ep->rx_reinit = 1;
1440 musb_start_urb(musb, 1, next_qh);
1441 }
1442 }
1443
1444 /*
1445 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1446 * and high-bandwidth IN transfer cases.
1447 */
1448 void musb_host_rx(struct musb *musb, u8 epnum)
1449 {
1450 struct urb *urb;
1451 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1452 void __iomem *epio = hw_ep->regs;
1453 struct musb_qh *qh = hw_ep->in_qh;
1454 size_t xfer_len;
1455 void __iomem *mbase = musb->mregs;
1456 int pipe;
1457 u16 rx_csr, val;
1458 bool iso_err = false;
1459 bool done = false;
1460 u32 status;
1461 struct dma_channel *dma;
1462
1463 musb_ep_select(mbase, epnum);
1464
1465 urb = next_urb(qh);
1466 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1467 status = 0;
1468 xfer_len = 0;
1469
1470 rx_csr = musb_readw(epio, MUSB_RXCSR);
1471 val = rx_csr;
1472
1473 if (unlikely(!urb)) {
1474 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1475 * usbtest #11 (unlinks) triggers it regularly, sometimes
1476 * with fifo full. (Only with DMA??)
1477 */
1478 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1479 musb_readw(epio, MUSB_RXCOUNT));
1480 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1481 return;
1482 }
1483
1484 pipe = urb->pipe;
1485
1486 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1487 epnum, rx_csr, urb->actual_length,
1488 dma ? dma->actual_len : 0);
1489
1490 /* check for errors, concurrent stall & unlink is not really
1491 * handled yet! */
1492 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1493 DBG(3, "RX end %d STALL\n", epnum);
1494
1495 /* stall; record URB status */
1496 status = -EPIPE;
1497
1498 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1499 DBG(3, "end %d RX proto error\n", epnum);
1500
1501 status = -EPROTO;
1502 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1503
1504 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1505
1506 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1507 DBG(6, "RX end %d NAK timeout\n", epnum);
1508
1509 /* NOTE: NAKing is *NOT* an error, so we want to
1510 * continue. Except ... if there's a request for
1511 * another QH, use that instead of starving it.
1512 *
1513 * Devices like Ethernet and serial adapters keep
1514 * reads posted at all times, which will starve
1515 * other devices without this logic.
1516 */
1517 if (usb_pipebulk(urb->pipe)
1518 && qh->mux == 1
1519 && !list_is_singular(&musb->in_bulk)) {
1520 musb_bulk_rx_nak_timeout(musb, hw_ep);
1521 return;
1522 }
1523 musb_ep_select(mbase, epnum);
1524 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1525 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1526 musb_writew(epio, MUSB_RXCSR, rx_csr);
1527
1528 goto finish;
1529 } else {
1530 DBG(4, "RX end %d ISO data error\n", epnum);
1531 /* packet error reported later */
1532 iso_err = true;
1533 }
1534 }
1535
1536 /* faults abort the transfer */
1537 if (status) {
1538 /* clean up dma and collect transfer count */
1539 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1540 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1541 (void) musb->dma_controller->channel_abort(dma);
1542 xfer_len = dma->actual_len;
1543 }
1544 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1545 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1546 done = true;
1547 goto finish;
1548 }
1549
1550 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1551 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1552 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1553 goto finish;
1554 }
1555
1556 /* thorough shutdown for now ... given more precise fault handling
1557 * and better queueing support, we might keep a DMA pipeline going
1558 * while processing this irq for earlier completions.
1559 */
1560
1561 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1562
1563 #ifndef CONFIG_USB_INVENTRA_DMA
1564 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1565 /* REVISIT this happened for a while on some short reads...
1566 * the cleanup still needs investigation... looks bad...
1567 * and also duplicates dma cleanup code above ... plus,
1568 * shouldn't this be the "half full" double buffer case?
1569 */
1570 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1571 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1572 (void) musb->dma_controller->channel_abort(dma);
1573 xfer_len = dma->actual_len;
1574 done = true;
1575 }
1576
1577 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1578 xfer_len, dma ? ", dma" : "");
1579 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1580
1581 musb_ep_select(mbase, epnum);
1582 musb_writew(epio, MUSB_RXCSR,
1583 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1584 }
1585 #endif
1586 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1587 xfer_len = dma->actual_len;
1588
1589 val &= ~(MUSB_RXCSR_DMAENAB
1590 | MUSB_RXCSR_H_AUTOREQ
1591 | MUSB_RXCSR_AUTOCLEAR
1592 | MUSB_RXCSR_RXPKTRDY);
1593 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1594
1595 #ifdef CONFIG_USB_INVENTRA_DMA
1596 if (usb_pipeisoc(pipe)) {
1597 struct usb_iso_packet_descriptor *d;
1598
1599 d = urb->iso_frame_desc + qh->iso_idx;
1600 d->actual_length = xfer_len;
1601
1602 /* even if there was an error, we did the dma
1603 * for iso_frame_desc->length
1604 */
1605 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1606 d->status = 0;
1607
1608 if (++qh->iso_idx >= urb->number_of_packets)
1609 done = true;
1610 else
1611 done = false;
1612
1613 } else {
1614 /* done if urb buffer is full or short packet is recd */
1615 done = (urb->actual_length + xfer_len >=
1616 urb->transfer_buffer_length
1617 || dma->actual_len < qh->maxpacket);
1618 }
1619
1620 /* send IN token for next packet, without AUTOREQ */
1621 if (!done) {
1622 val |= MUSB_RXCSR_H_REQPKT;
1623 musb_writew(epio, MUSB_RXCSR,
1624 MUSB_RXCSR_H_WZC_BITS | val);
1625 }
1626
1627 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1628 done ? "off" : "reset",
1629 musb_readw(epio, MUSB_RXCSR),
1630 musb_readw(epio, MUSB_RXCOUNT));
1631 #else
1632 done = true;
1633 #endif
1634 } else if (urb->status == -EINPROGRESS) {
1635 /* if no errors, be sure a packet is ready for unloading */
1636 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1637 status = -EPROTO;
1638 ERR("Rx interrupt with no errors or packet!\n");
1639
1640 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1641
1642 /* SCRUB (RX) */
1643 /* do the proper sequence to abort the transfer */
1644 musb_ep_select(mbase, epnum);
1645 val &= ~MUSB_RXCSR_H_REQPKT;
1646 musb_writew(epio, MUSB_RXCSR, val);
1647 goto finish;
1648 }
1649
1650 /* we are expecting IN packets */
1651 #ifdef CONFIG_USB_INVENTRA_DMA
1652 if (dma) {
1653 struct dma_controller *c;
1654 u16 rx_count;
1655 int ret, length;
1656 dma_addr_t buf;
1657
1658 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1659
1660 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1661 epnum, rx_count,
1662 urb->transfer_dma
1663 + urb->actual_length,
1664 qh->offset,
1665 urb->transfer_buffer_length);
1666
1667 c = musb->dma_controller;
1668
1669 if (usb_pipeisoc(pipe)) {
1670 int status = 0;
1671 struct usb_iso_packet_descriptor *d;
1672
1673 d = urb->iso_frame_desc + qh->iso_idx;
1674
1675 if (iso_err) {
1676 status = -EILSEQ;
1677 urb->error_count++;
1678 }
1679 if (rx_count > d->length) {
1680 if (status == 0) {
1681 status = -EOVERFLOW;
1682 urb->error_count++;
1683 }
1684 DBG(2, "** OVERFLOW %d into %d\n",\
1685 rx_count, d->length);
1686
1687 length = d->length;
1688 } else
1689 length = rx_count;
1690 d->status = status;
1691 buf = urb->transfer_dma + d->offset;
1692 } else {
1693 length = rx_count;
1694 buf = urb->transfer_dma +
1695 urb->actual_length;
1696 }
1697
1698 dma->desired_mode = 0;
1699 #ifdef USE_MODE1
1700 /* because of the issue below, mode 1 will
1701 * only rarely behave with correct semantics.
1702 */
1703 if ((urb->transfer_flags &
1704 URB_SHORT_NOT_OK)
1705 && (urb->transfer_buffer_length -
1706 urb->actual_length)
1707 > qh->maxpacket)
1708 dma->desired_mode = 1;
1709 if (rx_count < hw_ep->max_packet_sz_rx) {
1710 length = rx_count;
1711 dma->bDesiredMode = 0;
1712 } else {
1713 length = urb->transfer_buffer_length;
1714 }
1715 #endif
1716
1717 /* Disadvantage of using mode 1:
1718 * It's basically usable only for mass storage class; essentially all
1719 * other protocols also terminate transfers on short packets.
1720 *
1721 * Details:
1722 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1723 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1724 * to use the extra IN token to grab the last packet using mode 0, then
1725 * the problem is that you cannot be sure when the device will send the
1726 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1727 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1728 * transfer, while sometimes it is recd just a little late so that if you
1729 * try to configure for mode 0 soon after the mode 1 transfer is
1730 * completed, you will find rxcount 0. Okay, so you might think why not
1731 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1732 */
1733
1734 val = musb_readw(epio, MUSB_RXCSR);
1735 val &= ~MUSB_RXCSR_H_REQPKT;
1736
1737 if (dma->desired_mode == 0)
1738 val &= ~MUSB_RXCSR_H_AUTOREQ;
1739 else
1740 val |= MUSB_RXCSR_H_AUTOREQ;
1741 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
1742
1743 musb_writew(epio, MUSB_RXCSR,
1744 MUSB_RXCSR_H_WZC_BITS | val);
1745
1746 /* REVISIT if when actual_length != 0,
1747 * transfer_buffer_length needs to be
1748 * adjusted first...
1749 */
1750 ret = c->channel_program(
1751 dma, qh->maxpacket,
1752 dma->desired_mode, buf, length);
1753
1754 if (!ret) {
1755 c->channel_release(dma);
1756 hw_ep->rx_channel = NULL;
1757 dma = NULL;
1758 /* REVISIT reset CSR */
1759 }
1760 }
1761 #endif /* Mentor DMA */
1762
1763 if (!dma) {
1764 done = musb_host_packet_rx(musb, urb,
1765 epnum, iso_err);
1766 DBG(6, "read %spacket\n", done ? "last " : "");
1767 }
1768 }
1769
1770 finish:
1771 urb->actual_length += xfer_len;
1772 qh->offset += xfer_len;
1773 if (done) {
1774 if (urb->status == -EINPROGRESS)
1775 urb->status = status;
1776 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1777 }
1778 }
1779
1780 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1781 * the software schedule associates multiple such nodes with a given
1782 * host side hardware endpoint + direction; scheduling may activate
1783 * that hardware endpoint.
1784 */
1785 static int musb_schedule(
1786 struct musb *musb,
1787 struct musb_qh *qh,
1788 int is_in)
1789 {
1790 int idle;
1791 int best_diff;
1792 int best_end, epnum;
1793 struct musb_hw_ep *hw_ep = NULL;
1794 struct list_head *head = NULL;
1795
1796 /* use fixed hardware for control and bulk */
1797 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1798 head = &musb->control;
1799 hw_ep = musb->control_ep;
1800 goto success;
1801 }
1802
1803 /* else, periodic transfers get muxed to other endpoints */
1804
1805 /*
1806 * We know this qh hasn't been scheduled, so all we need to do
1807 * is choose which hardware endpoint to put it on ...
1808 *
1809 * REVISIT what we really want here is a regular schedule tree
1810 * like e.g. OHCI uses.
1811 */
1812 best_diff = 4096;
1813 best_end = -1;
1814
1815 for (epnum = 1, hw_ep = musb->endpoints + 1;
1816 epnum < musb->nr_endpoints;
1817 epnum++, hw_ep++) {
1818 int diff;
1819
1820 if (is_in || hw_ep->is_shared_fifo) {
1821 if (hw_ep->in_qh != NULL)
1822 continue;
1823 } else if (hw_ep->out_qh != NULL)
1824 continue;
1825
1826 if (hw_ep == musb->bulk_ep)
1827 continue;
1828
1829 if (is_in)
1830 diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
1831 else
1832 diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
1833
1834 if (diff >= 0 && best_diff > diff) {
1835 best_diff = diff;
1836 best_end = epnum;
1837 }
1838 }
1839 /* use bulk reserved ep1 if no other ep is free */
1840 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1841 hw_ep = musb->bulk_ep;
1842 if (is_in)
1843 head = &musb->in_bulk;
1844 else
1845 head = &musb->out_bulk;
1846
1847 /* Enable bulk RX NAK timeout scheme when bulk requests are
1848 * multiplexed. This scheme doen't work in high speed to full
1849 * speed scenario as NAK interrupts are not coming from a
1850 * full speed device connected to a high speed device.
1851 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1852 * 4 (8 frame or 8ms) for FS device.
1853 */
1854 if (is_in && qh->dev)
1855 qh->intv_reg =
1856 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1857 goto success;
1858 } else if (best_end < 0) {
1859 return -ENOSPC;
1860 }
1861
1862 idle = 1;
1863 qh->mux = 0;
1864 hw_ep = musb->endpoints + best_end;
1865 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1866 success:
1867 if (head) {
1868 idle = list_empty(head);
1869 list_add_tail(&qh->ring, head);
1870 qh->mux = 1;
1871 }
1872 qh->hw_ep = hw_ep;
1873 qh->hep->hcpriv = qh;
1874 if (idle)
1875 musb_start_urb(musb, is_in, qh);
1876 return 0;
1877 }
1878
1879 static int musb_urb_enqueue(
1880 struct usb_hcd *hcd,
1881 struct urb *urb,
1882 gfp_t mem_flags)
1883 {
1884 unsigned long flags;
1885 struct musb *musb = hcd_to_musb(hcd);
1886 struct usb_host_endpoint *hep = urb->ep;
1887 struct musb_qh *qh;
1888 struct usb_endpoint_descriptor *epd = &hep->desc;
1889 int ret;
1890 unsigned type_reg;
1891 unsigned interval;
1892
1893 /* host role must be active */
1894 if (!is_host_active(musb) || !musb->is_active)
1895 return -ENODEV;
1896
1897 spin_lock_irqsave(&musb->lock, flags);
1898 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1899 qh = ret ? NULL : hep->hcpriv;
1900 if (qh)
1901 urb->hcpriv = qh;
1902 spin_unlock_irqrestore(&musb->lock, flags);
1903
1904 /* DMA mapping was already done, if needed, and this urb is on
1905 * hep->urb_list now ... so we're done, unless hep wasn't yet
1906 * scheduled onto a live qh.
1907 *
1908 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1909 * disabled, testing for empty qh->ring and avoiding qh setup costs
1910 * except for the first urb queued after a config change.
1911 */
1912 if (qh || ret)
1913 return ret;
1914
1915 /* Allocate and initialize qh, minimizing the work done each time
1916 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1917 *
1918 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1919 * for bugs in other kernel code to break this driver...
1920 */
1921 qh = kzalloc(sizeof *qh, mem_flags);
1922 if (!qh) {
1923 spin_lock_irqsave(&musb->lock, flags);
1924 usb_hcd_unlink_urb_from_ep(hcd, urb);
1925 spin_unlock_irqrestore(&musb->lock, flags);
1926 return -ENOMEM;
1927 }
1928
1929 qh->hep = hep;
1930 qh->dev = urb->dev;
1931 INIT_LIST_HEAD(&qh->ring);
1932 qh->is_ready = 1;
1933
1934 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1935
1936 /* no high bandwidth support yet */
1937 if (qh->maxpacket & ~0x7ff) {
1938 ret = -EMSGSIZE;
1939 goto done;
1940 }
1941
1942 qh->epnum = usb_endpoint_num(epd);
1943 qh->type = usb_endpoint_type(epd);
1944
1945 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1946 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1947
1948 /* precompute rxtype/txtype/type0 register */
1949 type_reg = (qh->type << 4) | qh->epnum;
1950 switch (urb->dev->speed) {
1951 case USB_SPEED_LOW:
1952 type_reg |= 0xc0;
1953 break;
1954 case USB_SPEED_FULL:
1955 type_reg |= 0x80;
1956 break;
1957 default:
1958 type_reg |= 0x40;
1959 }
1960 qh->type_reg = type_reg;
1961
1962 /* Precompute RXINTERVAL/TXINTERVAL register */
1963 switch (qh->type) {
1964 case USB_ENDPOINT_XFER_INT:
1965 /*
1966 * Full/low speeds use the linear encoding,
1967 * high speed uses the logarithmic encoding.
1968 */
1969 if (urb->dev->speed <= USB_SPEED_FULL) {
1970 interval = max_t(u8, epd->bInterval, 1);
1971 break;
1972 }
1973 /* FALLTHROUGH */
1974 case USB_ENDPOINT_XFER_ISOC:
1975 /* ISO always uses logarithmic encoding */
1976 interval = min_t(u8, epd->bInterval, 16);
1977 break;
1978 default:
1979 /* REVISIT we actually want to use NAK limits, hinting to the
1980 * transfer scheduling logic to try some other qh, e.g. try
1981 * for 2 msec first:
1982 *
1983 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
1984 *
1985 * The downside of disabling this is that transfer scheduling
1986 * gets VERY unfair for nonperiodic transfers; a misbehaving
1987 * peripheral could make that hurt. That's perfectly normal
1988 * for reads from network or serial adapters ... so we have
1989 * partial NAKlimit support for bulk RX.
1990 *
1991 * The upside of disabling it is simpler transfer scheduling.
1992 */
1993 interval = 0;
1994 }
1995 qh->intv_reg = interval;
1996
1997 /* precompute addressing for external hub/tt ports */
1998 if (musb->is_multipoint) {
1999 struct usb_device *parent = urb->dev->parent;
2000
2001 if (parent != hcd->self.root_hub) {
2002 qh->h_addr_reg = (u8) parent->devnum;
2003
2004 /* set up tt info if needed */
2005 if (urb->dev->tt) {
2006 qh->h_port_reg = (u8) urb->dev->ttport;
2007 if (urb->dev->tt->hub)
2008 qh->h_addr_reg =
2009 (u8) urb->dev->tt->hub->devnum;
2010 if (urb->dev->tt->multi)
2011 qh->h_addr_reg |= 0x80;
2012 }
2013 }
2014 }
2015
2016 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2017 * until we get real dma queues (with an entry for each urb/buffer),
2018 * we only have work to do in the former case.
2019 */
2020 spin_lock_irqsave(&musb->lock, flags);
2021 if (hep->hcpriv) {
2022 /* some concurrent activity submitted another urb to hep...
2023 * odd, rare, error prone, but legal.
2024 */
2025 kfree(qh);
2026 ret = 0;
2027 } else
2028 ret = musb_schedule(musb, qh,
2029 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2030
2031 if (ret == 0) {
2032 urb->hcpriv = qh;
2033 /* FIXME set urb->start_frame for iso/intr, it's tested in
2034 * musb_start_urb(), but otherwise only konicawc cares ...
2035 */
2036 }
2037 spin_unlock_irqrestore(&musb->lock, flags);
2038
2039 done:
2040 if (ret != 0) {
2041 spin_lock_irqsave(&musb->lock, flags);
2042 usb_hcd_unlink_urb_from_ep(hcd, urb);
2043 spin_unlock_irqrestore(&musb->lock, flags);
2044 kfree(qh);
2045 }
2046 return ret;
2047 }
2048
2049
2050 /*
2051 * abort a transfer that's at the head of a hardware queue.
2052 * called with controller locked, irqs blocked
2053 * that hardware queue advances to the next transfer, unless prevented
2054 */
2055 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
2056 {
2057 struct musb_hw_ep *ep = qh->hw_ep;
2058 void __iomem *epio = ep->regs;
2059 unsigned hw_end = ep->epnum;
2060 void __iomem *regs = ep->musb->mregs;
2061 u16 csr;
2062 int status = 0;
2063
2064 musb_ep_select(regs, hw_end);
2065
2066 if (is_dma_capable()) {
2067 struct dma_channel *dma;
2068
2069 dma = is_in ? ep->rx_channel : ep->tx_channel;
2070 if (dma) {
2071 status = ep->musb->dma_controller->channel_abort(dma);
2072 DBG(status ? 1 : 3,
2073 "abort %cX%d DMA for urb %p --> %d\n",
2074 is_in ? 'R' : 'T', ep->epnum,
2075 urb, status);
2076 urb->actual_length += dma->actual_len;
2077 }
2078 }
2079
2080 /* turn off DMA requests, discard state, stop polling ... */
2081 if (is_in) {
2082 /* giveback saves bulk toggle */
2083 csr = musb_h_flush_rxfifo(ep, 0);
2084
2085 /* REVISIT we still get an irq; should likely clear the
2086 * endpoint's irq status here to avoid bogus irqs.
2087 * clearing that status is platform-specific...
2088 */
2089 } else if (ep->epnum) {
2090 musb_h_tx_flush_fifo(ep);
2091 csr = musb_readw(epio, MUSB_TXCSR);
2092 csr &= ~(MUSB_TXCSR_AUTOSET
2093 | MUSB_TXCSR_DMAENAB
2094 | MUSB_TXCSR_H_RXSTALL
2095 | MUSB_TXCSR_H_NAKTIMEOUT
2096 | MUSB_TXCSR_H_ERROR
2097 | MUSB_TXCSR_TXPKTRDY);
2098 musb_writew(epio, MUSB_TXCSR, csr);
2099 /* REVISIT may need to clear FLUSHFIFO ... */
2100 musb_writew(epio, MUSB_TXCSR, csr);
2101 /* flush cpu writebuffer */
2102 csr = musb_readw(epio, MUSB_TXCSR);
2103 } else {
2104 musb_h_ep0_flush_fifo(ep);
2105 }
2106 if (status == 0)
2107 musb_advance_schedule(ep->musb, urb, ep, is_in);
2108 return status;
2109 }
2110
2111 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2112 {
2113 struct musb *musb = hcd_to_musb(hcd);
2114 struct musb_qh *qh;
2115 struct list_head *sched;
2116 unsigned long flags;
2117 int ret;
2118
2119 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2120 usb_pipedevice(urb->pipe),
2121 usb_pipeendpoint(urb->pipe),
2122 usb_pipein(urb->pipe) ? "in" : "out");
2123
2124 spin_lock_irqsave(&musb->lock, flags);
2125 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2126 if (ret)
2127 goto done;
2128
2129 qh = urb->hcpriv;
2130 if (!qh)
2131 goto done;
2132
2133 /* Any URB not actively programmed into endpoint hardware can be
2134 * immediately given back; that's any URB not at the head of an
2135 * endpoint queue, unless someday we get real DMA queues. And even
2136 * if it's at the head, it might not be known to the hardware...
2137 *
2138 * Otherwise abort current transfer, pending dma, etc.; urb->status
2139 * has already been updated. This is a synchronous abort; it'd be
2140 * OK to hold off until after some IRQ, though.
2141 */
2142 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
2143 ret = -EINPROGRESS;
2144 else {
2145 switch (qh->type) {
2146 case USB_ENDPOINT_XFER_CONTROL:
2147 sched = &musb->control;
2148 break;
2149 case USB_ENDPOINT_XFER_BULK:
2150 if (qh->mux == 1) {
2151 if (usb_pipein(urb->pipe))
2152 sched = &musb->in_bulk;
2153 else
2154 sched = &musb->out_bulk;
2155 break;
2156 }
2157 default:
2158 /* REVISIT when we get a schedule tree, periodic
2159 * transfers won't always be at the head of a
2160 * singleton queue...
2161 */
2162 sched = NULL;
2163 break;
2164 }
2165 }
2166
2167 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2168 if (ret < 0 || (sched && qh != first_qh(sched))) {
2169 int ready = qh->is_ready;
2170
2171 ret = 0;
2172 qh->is_ready = 0;
2173 __musb_giveback(musb, urb, 0);
2174 qh->is_ready = ready;
2175
2176 /* If nothing else (usually musb_giveback) is using it
2177 * and its URB list has emptied, recycle this qh.
2178 */
2179 if (ready && list_empty(&qh->hep->urb_list)) {
2180 qh->hep->hcpriv = NULL;
2181 list_del(&qh->ring);
2182 kfree(qh);
2183 }
2184 } else
2185 ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2186 done:
2187 spin_unlock_irqrestore(&musb->lock, flags);
2188 return ret;
2189 }
2190
2191 /* disable an endpoint */
2192 static void
2193 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2194 {
2195 u8 epnum = hep->desc.bEndpointAddress;
2196 unsigned long flags;
2197 struct musb *musb = hcd_to_musb(hcd);
2198 u8 is_in = epnum & USB_DIR_IN;
2199 struct musb_qh *qh;
2200 struct urb *urb;
2201 struct list_head *sched;
2202
2203 spin_lock_irqsave(&musb->lock, flags);
2204
2205 qh = hep->hcpriv;
2206 if (qh == NULL)
2207 goto exit;
2208
2209 switch (qh->type) {
2210 case USB_ENDPOINT_XFER_CONTROL:
2211 sched = &musb->control;
2212 break;
2213 case USB_ENDPOINT_XFER_BULK:
2214 if (qh->mux == 1) {
2215 if (is_in)
2216 sched = &musb->in_bulk;
2217 else
2218 sched = &musb->out_bulk;
2219 break;
2220 }
2221 default:
2222 /* REVISIT when we get a schedule tree, periodic transfers
2223 * won't always be at the head of a singleton queue...
2224 */
2225 sched = NULL;
2226 break;
2227 }
2228
2229 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2230
2231 /* kick first urb off the hardware, if needed */
2232 qh->is_ready = 0;
2233 if (!sched || qh == first_qh(sched)) {
2234 urb = next_urb(qh);
2235
2236 /* make software (then hardware) stop ASAP */
2237 if (!urb->unlinked)
2238 urb->status = -ESHUTDOWN;
2239
2240 /* cleanup */
2241 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2242
2243 /* Then nuke all the others ... and advance the
2244 * queue on hw_ep (e.g. bulk ring) when we're done.
2245 */
2246 while (!list_empty(&hep->urb_list)) {
2247 urb = next_urb(qh);
2248 urb->status = -ESHUTDOWN;
2249 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2250 }
2251 } else {
2252 /* Just empty the queue; the hardware is busy with
2253 * other transfers, and since !qh->is_ready nothing
2254 * will activate any of these as it advances.
2255 */
2256 while (!list_empty(&hep->urb_list))
2257 __musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2258
2259 hep->hcpriv = NULL;
2260 list_del(&qh->ring);
2261 kfree(qh);
2262 }
2263 exit:
2264 spin_unlock_irqrestore(&musb->lock, flags);
2265 }
2266
2267 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2268 {
2269 struct musb *musb = hcd_to_musb(hcd);
2270
2271 return musb_readw(musb->mregs, MUSB_FRAME);
2272 }
2273
2274 static int musb_h_start(struct usb_hcd *hcd)
2275 {
2276 struct musb *musb = hcd_to_musb(hcd);
2277
2278 /* NOTE: musb_start() is called when the hub driver turns
2279 * on port power, or when (OTG) peripheral starts.
2280 */
2281 hcd->state = HC_STATE_RUNNING;
2282 musb->port1_status = 0;
2283 return 0;
2284 }
2285
2286 static void musb_h_stop(struct usb_hcd *hcd)
2287 {
2288 musb_stop(hcd_to_musb(hcd));
2289 hcd->state = HC_STATE_HALT;
2290 }
2291
2292 static int musb_bus_suspend(struct usb_hcd *hcd)
2293 {
2294 struct musb *musb = hcd_to_musb(hcd);
2295
2296 if (musb->xceiv.state == OTG_STATE_A_SUSPEND)
2297 return 0;
2298
2299 if (is_host_active(musb) && musb->is_active) {
2300 WARNING("trying to suspend as %s is_active=%i\n",
2301 otg_state_string(musb), musb->is_active);
2302 return -EBUSY;
2303 } else
2304 return 0;
2305 }
2306
2307 static int musb_bus_resume(struct usb_hcd *hcd)
2308 {
2309 /* resuming child port does the work */
2310 return 0;
2311 }
2312
2313 const struct hc_driver musb_hc_driver = {
2314 .description = "musb-hcd",
2315 .product_desc = "MUSB HDRC host driver",
2316 .hcd_priv_size = sizeof(struct musb),
2317 .flags = HCD_USB2 | HCD_MEMORY,
2318
2319 /* not using irq handler or reset hooks from usbcore, since
2320 * those must be shared with peripheral code for OTG configs
2321 */
2322
2323 .start = musb_h_start,
2324 .stop = musb_h_stop,
2325
2326 .get_frame_number = musb_h_get_frame_number,
2327
2328 .urb_enqueue = musb_urb_enqueue,
2329 .urb_dequeue = musb_urb_dequeue,
2330 .endpoint_disable = musb_h_disable,
2331
2332 .hub_status_data = musb_hub_status_data,
2333 .hub_control = musb_hub_control,
2334 .bus_suspend = musb_bus_suspend,
2335 .bus_resume = musb_bus_resume,
2336 /* .start_port_reset = NULL, */
2337 /* .hub_irq_enable = NULL, */
2338 };
linux kernel for loongson