drivers/video/smi/sm7xxhw.h

   1 /*
   2  *  linux/drivers/video/sm7xxhw.h -- Silicon Motion SM7xx frame buffer device
   3  *
   4  *      Copyright (C) 2006 Silicon Motion, Inc.
   5  *      Ge Wang, gewang@siliconmotion.com
   6  *
   7  *  This file is subject to the terms and conditions of the GNU General Public
   8  *  License. See the file COPYING in the main directory of this archive for
   9  *  more details.
  10  */
  11
  12
  13 #define SM712_VIDEOMEMORYSIZE    0x00400000  /*Assume SM712 graphics chip has 4MB VRAM */
  14 #define SM722_VIDEOMEMORYSIZE    0x00800000  /*Assume SM722 graphics chip has 8MB VRAM */
  15
  16 #define dac_reg (0x3c8)
  17 #define dac_val (0x3c9)
  18
  19 #define smtc_mmiowb(dat,reg)    writeb(dat, smtc_RegBaseAddress + reg)
  20 #define smtc_mmioww(dat,reg)    writew(dat, smtc_RegBaseAddress + reg)
  21 #define smtc_mmiowl(dat,reg)    writel(dat, smtc_RegBaseAddress + reg)
  22
  23 #define smtc_mmiorb(reg)                readb(smtc_RegBaseAddress + reg)
  24 #define smtc_mmiorw(reg)                readw(smtc_RegBaseAddress + reg)
  25 #define smtc_mmiorl(reg)                readl(smtc_RegBaseAddress + reg)
  26
  27 #define SIZE_SR00_SR04      (0x04 - 0x00 + 1)
  28 #define SIZE_SR10_SR24      (0x24 - 0x10 + 1)
  29 #define SIZE_SR30_SR75      (0x75 - 0x30 + 1)
  30 #define SIZE_SR80_SR93      (0x93 - 0x80 + 1)
  31 #define SIZE_SRA0_SRAF      (0xAF - 0xA0 + 1)
  32 #define SIZE_GR00_GR08      (0x08 - 0x00 + 1)
  33 #define SIZE_AR00_AR14      (0x14 - 0x00 + 1)
  34 #define SIZE_CR00_CR18      (0x18 - 0x00 + 1)
  35 #define SIZE_CR30_CR4D      (0x4D - 0x30 + 1)
  36 #define SIZE_CR90_CRA7      (0xA7 - 0x90 + 1)
  37 #define SIZE_VPR            (0x6C + 1)
  38 #define SIZE_DPR                        (0x44 + 1)
  39
  40
  41 static inline void smtc_crtcw(int reg, int val)
  42 {
  43         smtc_mmiowb(reg, 0x3d4);
  44         smtc_mmiowb(val, 0x3d5);
  45 }
  46
  47 static inline unsigned int smtc_crtcr(int reg)
  48 {
  49         smtc_mmiowb(reg, 0x3d4);
  50         return smtc_mmiorb(0x3d5);
  51 }
  52
  53 static inline void smtc_grphw(int reg, int val)
  54 {
  55         smtc_mmiowb(reg, 0x3ce);
  56         smtc_mmiowb(val, 0x3cf);
  57 }
  58
  59 static inline unsigned int smtc_grphr(int reg)
  60 {
  61         smtc_mmiowb(reg, 0x3ce);
  62         return smtc_mmiorb(0x3cf);
  63 }
  64
  65 static inline void smtc_attrw(int reg, int val)
  66 {
  67         smtc_mmiorb(0x3da);
  68         smtc_mmiowb(reg, 0x3c0);
  69         smtc_mmiorb(0x3c1);
  70         smtc_mmiowb(val, 0x3c0);
  71 }
  72
  73 static inline void smtc_seqw(int reg, int val)
  74 {
  75         smtc_mmiowb(reg, 0x3c4);
  76         smtc_mmiowb(val, 0x3c5);
  77 }
  78
  79 static inline unsigned int smtc_seqr(int reg)
  80 {
  81         smtc_mmiowb(reg, 0x3c4);
  82         return smtc_mmiorb(0x3c5);
  83 }
  84
  85 // The next structure holds all information relevant for a specific video mode.
  86 struct ModeInit
  87 {
  88         int                       mmSizeX;
  89         int                       mmSizeY;
  90         int                       bpp;
  91         int                       hz;
  92         unsigned char Init_MISC;
  93         unsigned char Init_SR00_SR04[SIZE_SR00_SR04];
  94         unsigned char Init_SR10_SR24[SIZE_SR10_SR24];
  95         unsigned char Init_SR30_SR75[SIZE_SR30_SR75];
  96         unsigned char Init_SR80_SR93[SIZE_SR80_SR93];
  97         unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF];
  98         unsigned char Init_GR00_GR08[SIZE_GR00_GR08];
  99         unsigned char Init_AR00_AR14[SIZE_AR00_AR14];
 100         unsigned char Init_CR00_CR18[SIZE_CR00_CR18];
 101         unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D];
 102         unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7];
 103 };
 104