5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
51 #ifdef CONFIG_MTD_PARTITIONS
52 #include <linux/mtd/partitions.h>
55 /* Define default oob placement schemes for large and small page devices */
56 static struct nand_ecclayout nand_oob_8
= {
66 static struct nand_ecclayout nand_oob_16
= {
68 .eccpos
= {0, 1, 2, 3, 6, 7},
74 static struct nand_ecclayout nand_oob_64
= {
77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
85 static struct nand_ecclayout nand_oob_128
= {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
99 static int nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
,
102 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
103 struct mtd_oob_ops
*ops
);
106 * For devices which display every fart in the system on a separate LED. Is
107 * compiled away when LED support is disabled.
109 DEFINE_LED_TRIGGER(nand_led_trigger
);
111 static int check_offs_len(struct mtd_info
*mtd
,
112 loff_t ofs
, uint64_t len
)
114 struct nand_chip
*chip
= mtd
->priv
;
117 /* Start address must align on block boundary */
118 if (ofs
& ((1 << chip
->phys_erase_shift
) - 1)) {
119 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Unaligned address\n", __func__
);
123 /* Length must align on block boundary */
124 if (len
& ((1 << chip
->phys_erase_shift
) - 1)) {
125 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Length not block aligned\n",
130 /* Do not allow past end of device */
131 if (ofs
+ len
> mtd
->size
) {
132 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Past end of device\n",
141 * nand_release_device - [GENERIC] release chip
142 * @mtd: MTD device structure
144 * Deselect, release chip lock and wake up anyone waiting on the device
146 static void nand_release_device(struct mtd_info
*mtd
)
148 struct nand_chip
*chip
= mtd
->priv
;
150 /* De-select the NAND device */
151 chip
->select_chip(mtd
, -1);
153 /* Release the controller and the chip */
154 spin_lock(&chip
->controller
->lock
);
155 chip
->controller
->active
= NULL
;
156 chip
->state
= FL_READY
;
157 wake_up(&chip
->controller
->wq
);
158 spin_unlock(&chip
->controller
->lock
);
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
165 * Default read function for 8bit buswith
167 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
169 struct nand_chip
*chip
= mtd
->priv
;
170 return readb(chip
->IO_ADDR_R
);
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
177 * Default read function for 16bit buswith with
178 * endianess conversion
180 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
182 struct nand_chip
*chip
= mtd
->priv
;
183 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
190 * Default read function for 16bit buswith without
191 * endianess conversion
193 static u16
nand_read_word(struct mtd_info
*mtd
)
195 struct nand_chip
*chip
= mtd
->priv
;
196 return readw(chip
->IO_ADDR_R
);
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
202 * @chipnr: chipnumber to select, -1 for deselect
204 * Default select function for 1 chip devices.
206 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
208 struct nand_chip
*chip
= mtd
->priv
;
212 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
226 * @len: number of bytes to write
228 * Default write function for 8bit buswith
230 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
233 struct nand_chip
*chip
= mtd
->priv
;
235 for (i
= 0; i
< len
; i
++)
236 writeb(buf
[i
], chip
->IO_ADDR_W
);
240 * nand_read_buf - [DEFAULT] read chip data into buffer
241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
245 * Default read function for 8bit buswith
247 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
250 struct nand_chip
*chip
= mtd
->priv
;
252 for (i
= 0; i
< len
; i
++)
253 buf
[i
] = readb(chip
->IO_ADDR_R
);
257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
262 * Default verify function for 8bit buswith
264 static int nand_verify_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
267 struct nand_chip
*chip
= mtd
->priv
;
269 for (i
= 0; i
< len
; i
++)
270 if (buf
[i
] != readb(chip
->IO_ADDR_R
))
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
279 * @len: number of bytes to write
281 * Default write function for 16bit buswith
283 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
286 struct nand_chip
*chip
= mtd
->priv
;
287 u16
*p
= (u16
*) buf
;
290 for (i
= 0; i
< len
; i
++)
291 writew(p
[i
], chip
->IO_ADDR_W
);
296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
301 * Default read function for 16bit buswith
303 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
306 struct nand_chip
*chip
= mtd
->priv
;
307 u16
*p
= (u16
*) buf
;
310 for (i
= 0; i
< len
; i
++)
311 p
[i
] = readw(chip
->IO_ADDR_R
);
315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
320 * Default verify function for 16bit buswith
322 static int nand_verify_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
325 struct nand_chip
*chip
= mtd
->priv
;
326 u16
*p
= (u16
*) buf
;
329 for (i
= 0; i
< len
; i
++)
330 if (p
[i
] != readw(chip
->IO_ADDR_R
))
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
342 * Check, if the block is bad.
344 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
346 int page
, chipnr
, res
= 0;
347 struct nand_chip
*chip
= mtd
->priv
;
350 if (chip
->options
& NAND_BBT_SCANLASTPAGE
)
351 ofs
+= mtd
->erasesize
- mtd
->writesize
;
353 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
356 chipnr
= (int)(ofs
>> chip
->chip_shift
);
358 nand_get_device(chip
, mtd
, FL_READING
);
360 /* Select the NAND device */
361 chip
->select_chip(mtd
, chipnr
);
364 if (chip
->options
& NAND_BUSWIDTH_16
) {
365 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
& 0xFE,
367 bad
= cpu_to_le16(chip
->read_word(mtd
));
368 if (chip
->badblockpos
& 0x1)
373 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
, page
);
374 bad
= chip
->read_byte(mtd
);
377 if (likely(chip
->badblockbits
== 8))
380 res
= hweight8(bad
) < chip
->badblockbits
;
383 nand_release_device(mtd
);
389 * nand_default_block_markbad - [DEFAULT] mark a block bad
390 * @mtd: MTD device structure
391 * @ofs: offset from device start
393 * This is the default implementation, which can be overridden by
394 * a hardware specific driver.
396 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
398 struct nand_chip
*chip
= mtd
->priv
;
399 uint8_t buf
[2] = { 0, 0 };
400 int block
, ret
, i
= 0;
402 if (chip
->options
& NAND_BBT_SCANLASTPAGE
)
403 ofs
+= mtd
->erasesize
- mtd
->writesize
;
405 /* Get block number */
406 block
= (int)(ofs
>> chip
->bbt_erase_shift
);
408 chip
->bbt
[block
>> 2] |= 0x01 << ((block
& 0x03) << 1);
410 /* Do we have a flash based bad block table ? */
411 if (chip
->options
& NAND_USE_FLASH_BBT
)
412 ret
= nand_update_bbt(mtd
, ofs
);
414 nand_get_device(chip
, mtd
, FL_WRITING
);
416 /* Write to first two pages and to byte 1 and 6 if necessary.
417 * If we write to more than one location, the first error
418 * encountered quits the procedure. We write two bytes per
419 * location, so we dont have to mess with 16 bit access.
422 chip
->ops
.len
= chip
->ops
.ooblen
= 2;
423 chip
->ops
.datbuf
= NULL
;
424 chip
->ops
.oobbuf
= buf
;
425 chip
->ops
.ooboffs
= chip
->badblockpos
& ~0x01;
427 ret
= nand_do_write_oob(mtd
, ofs
, &chip
->ops
);
429 if (!ret
&& (chip
->options
& NAND_BBT_SCANBYTE1AND6
)) {
430 chip
->ops
.ooboffs
= NAND_SMALL_BADBLOCK_POS
432 ret
= nand_do_write_oob(mtd
, ofs
, &chip
->ops
);
435 ofs
+= mtd
->writesize
;
436 } while (!ret
&& (chip
->options
& NAND_BBT_SCAN2NDPAGE
) &&
439 nand_release_device(mtd
);
442 mtd
->ecc_stats
.badblocks
++;
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
452 * The function expects, that the device is already selected
454 static int nand_check_wp(struct mtd_info
*mtd
)
456 struct nand_chip
*chip
= mtd
->priv
;
458 /* broken xD cards report WP despite being writable */
459 if (chip
->options
& NAND_BROKEN_XD
)
462 /* Check the WP bit */
463 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
464 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
468 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
469 * @mtd: MTD device structure
470 * @ofs: offset from device start
471 * @getchip: 0, if the chip is already selected
472 * @allowbbt: 1, if its allowed to access the bbt area
474 * Check, if the block is bad. Either by reading the bad block table or
475 * calling of the scan function.
477 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
480 struct nand_chip
*chip
= mtd
->priv
;
483 return chip
->block_bad(mtd
, ofs
, getchip
);
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
490 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
491 * @mtd: MTD device structure
494 * Helper function for nand_wait_ready used when needing to wait in interrupt
497 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
499 struct nand_chip
*chip
= mtd
->priv
;
502 /* Wait for the device to get ready */
503 for (i
= 0; i
< timeo
; i
++) {
504 if (chip
->dev_ready(mtd
))
506 touch_softlockup_watchdog();
512 * Wait for the ready pin, after a command
513 * The timeout is catched later.
515 void nand_wait_ready(struct mtd_info
*mtd
)
517 struct nand_chip
*chip
= mtd
->priv
;
518 unsigned long timeo
= jiffies
+ 2;
521 if (in_interrupt() || oops_in_progress
)
522 return panic_nand_wait_ready(mtd
, 400);
524 led_trigger_event(nand_led_trigger
, LED_FULL
);
525 /* wait until command is processed or timeout occures */
527 if (chip
->dev_ready(mtd
))
529 touch_softlockup_watchdog();
530 } while (time_before(jiffies
, timeo
));
531 led_trigger_event(nand_led_trigger
, LED_OFF
);
533 EXPORT_SYMBOL_GPL(nand_wait_ready
);
536 * nand_command - [DEFAULT] Send command to NAND device
537 * @mtd: MTD device structure
538 * @command: the command to be sent
539 * @column: the column address for this command, -1 if none
540 * @page_addr: the page address for this command, -1 if none
542 * Send command to NAND device. This function is used for small page
543 * devices (256/512 Bytes per page)
545 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
546 int column
, int page_addr
)
548 register struct nand_chip
*chip
= mtd
->priv
;
549 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
552 * Write out the command to the device.
554 if (command
== NAND_CMD_SEQIN
) {
557 if (column
>= mtd
->writesize
) {
559 column
-= mtd
->writesize
;
560 readcmd
= NAND_CMD_READOOB
;
561 } else if (column
< 256) {
562 /* First 256 bytes --> READ0 */
563 readcmd
= NAND_CMD_READ0
;
566 readcmd
= NAND_CMD_READ1
;
568 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
569 ctrl
&= ~NAND_CTRL_CHANGE
;
571 chip
->cmd_ctrl(mtd
, command
, ctrl
);
574 * Address cycle, when necessary
576 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
577 /* Serially input address */
579 /* Adjust columns for 16 bit buswidth */
580 if (chip
->options
& NAND_BUSWIDTH_16
)
582 chip
->cmd_ctrl(mtd
, column
, ctrl
);
583 ctrl
&= ~NAND_CTRL_CHANGE
;
585 if (page_addr
!= -1) {
586 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
587 ctrl
&= ~NAND_CTRL_CHANGE
;
588 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
589 /* One more address cycle for devices > 32MiB */
590 if (chip
->chipsize
> (32 << 20))
591 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
593 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
596 * program and erase have their own busy handlers
597 * status and sequential in needs no delay
601 case NAND_CMD_PAGEPROG
:
602 case NAND_CMD_ERASE1
:
603 case NAND_CMD_ERASE2
:
605 case NAND_CMD_STATUS
:
611 udelay(chip
->chip_delay
);
612 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
613 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
615 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
616 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
620 /* This applies to read commands */
623 * If we don't have access to the busy pin, we apply the given
626 if (!chip
->dev_ready
) {
627 udelay(chip
->chip_delay
);
631 /* Apply this short delay always to ensure that we do wait tWB in
632 * any case on any machine. */
635 nand_wait_ready(mtd
);
639 * nand_command_lp - [DEFAULT] Send command to NAND large page device
640 * @mtd: MTD device structure
641 * @command: the command to be sent
642 * @column: the column address for this command, -1 if none
643 * @page_addr: the page address for this command, -1 if none
645 * Send command to NAND device. This is the version for the new large page
646 * devices We dont have the separate regions as we have in the small page
647 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
649 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
650 int column
, int page_addr
)
652 register struct nand_chip
*chip
= mtd
->priv
;
654 /* Emulate NAND_CMD_READOOB */
655 if (command
== NAND_CMD_READOOB
) {
656 column
+= mtd
->writesize
;
657 command
= NAND_CMD_READ0
;
660 /* Command latch cycle */
661 chip
->cmd_ctrl(mtd
, command
& 0xff,
662 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
664 if (column
!= -1 || page_addr
!= -1) {
665 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
667 /* Serially input address */
669 /* Adjust columns for 16 bit buswidth */
670 if (chip
->options
& NAND_BUSWIDTH_16
)
672 chip
->cmd_ctrl(mtd
, column
, ctrl
);
673 ctrl
&= ~NAND_CTRL_CHANGE
;
674 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
676 if (page_addr
!= -1) {
677 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
678 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
679 NAND_NCE
| NAND_ALE
);
680 /* One more address cycle for devices > 128MiB */
681 if (chip
->chipsize
> (128 << 20))
682 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
683 NAND_NCE
| NAND_ALE
);
686 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
689 * program and erase have their own busy handlers
690 * status, sequential in, and deplete1 need no delay
694 case NAND_CMD_CACHEDPROG
:
695 case NAND_CMD_PAGEPROG
:
696 case NAND_CMD_ERASE1
:
697 case NAND_CMD_ERASE2
:
700 case NAND_CMD_STATUS
:
701 case NAND_CMD_DEPLETE1
:
705 * read error status commands require only a short delay
707 case NAND_CMD_STATUS_ERROR
:
708 case NAND_CMD_STATUS_ERROR0
:
709 case NAND_CMD_STATUS_ERROR1
:
710 case NAND_CMD_STATUS_ERROR2
:
711 case NAND_CMD_STATUS_ERROR3
:
712 udelay(chip
->chip_delay
);
718 udelay(chip
->chip_delay
);
719 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
720 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
721 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
722 NAND_NCE
| NAND_CTRL_CHANGE
);
723 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
727 case NAND_CMD_RNDOUT
:
728 /* No ready / busy check necessary */
729 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
730 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
731 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
732 NAND_NCE
| NAND_CTRL_CHANGE
);
736 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
737 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
738 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
739 NAND_NCE
| NAND_CTRL_CHANGE
);
741 /* This applies to read commands */
744 * If we don't have access to the busy pin, we apply the given
747 if (!chip
->dev_ready
) {
748 udelay(chip
->chip_delay
);
753 /* Apply this short delay always to ensure that we do wait tWB in
754 * any case on any machine. */
757 nand_wait_ready(mtd
);
761 * panic_nand_get_device - [GENERIC] Get chip for selected access
762 * @chip: the nand chip descriptor
763 * @mtd: MTD device structure
764 * @new_state: the state which is requested
766 * Used when in panic, no locks are taken.
768 static void panic_nand_get_device(struct nand_chip
*chip
,
769 struct mtd_info
*mtd
, int new_state
)
771 /* Hardware controller shared among independend devices */
772 chip
->controller
->active
= chip
;
773 chip
->state
= new_state
;
777 * nand_get_device - [GENERIC] Get chip for selected access
778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
782 * Get the device and lock it for exclusive access
785 nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
, int new_state
)
787 spinlock_t
*lock
= &chip
->controller
->lock
;
788 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
789 DECLARE_WAITQUEUE(wait
, current
);
793 /* Hardware controller shared among independent devices */
794 if (!chip
->controller
->active
)
795 chip
->controller
->active
= chip
;
797 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
798 chip
->state
= new_state
;
802 if (new_state
== FL_PM_SUSPENDED
) {
803 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
804 chip
->state
= FL_PM_SUSPENDED
;
809 set_current_state(TASK_UNINTERRUPTIBLE
);
810 add_wait_queue(wq
, &wait
);
813 remove_wait_queue(wq
, &wait
);
818 * panic_nand_wait - [GENERIC] wait until the command is done
819 * @mtd: MTD device structure
820 * @chip: NAND chip structure
823 * Wait for command done. This is a helper function for nand_wait used when
824 * we are in interrupt context. May happen when in panic and trying to write
825 * an oops through mtdoops.
827 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
831 for (i
= 0; i
< timeo
; i
++) {
832 if (chip
->dev_ready
) {
833 if (chip
->dev_ready(mtd
))
836 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
844 * nand_wait - [DEFAULT] wait until the command is done
845 * @mtd: MTD device structure
846 * @chip: NAND chip structure
848 * Wait for command done. This applies to erase and program only
849 * Erase can take up to 400ms and program up to 20ms according to
850 * general NAND and SmartMedia specs
852 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
855 unsigned long timeo
= jiffies
;
856 int status
, state
= chip
->state
;
858 if (state
== FL_ERASING
)
859 timeo
+= (HZ
* 400) / 1000;
861 timeo
+= (HZ
* 20) / 1000;
863 led_trigger_event(nand_led_trigger
, LED_FULL
);
865 /* Apply this short delay always to ensure that we do wait tWB in
866 * any case on any machine. */
869 if ((state
== FL_ERASING
) && (chip
->options
& NAND_IS_AND
))
870 chip
->cmdfunc(mtd
, NAND_CMD_STATUS_MULTI
, -1, -1);
872 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
874 if (in_interrupt() || oops_in_progress
)
875 panic_nand_wait(mtd
, chip
, timeo
);
877 while (time_before(jiffies
, timeo
)) {
878 if (chip
->dev_ready
) {
879 if (chip
->dev_ready(mtd
))
882 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
888 led_trigger_event(nand_led_trigger
, LED_OFF
);
890 status
= (int)chip
->read_byte(mtd
);
895 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
898 * @ofs: offset to start unlock from
899 * @len: length to unlock
900 * @invert: when = 0, unlock the range of blocks within the lower and
901 * upper boundary address
902 * when = 1, unlock the range of blocks outside the boundaries
903 * of the lower and upper boundary address
905 * return - unlock status
907 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
908 uint64_t len
, int invert
)
912 struct nand_chip
*chip
= mtd
->priv
;
914 /* Submit address of first page to unlock */
915 page
= ofs
>> chip
->page_shift
;
916 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
918 /* Submit address of last page to unlock */
919 page
= (ofs
+ len
) >> chip
->page_shift
;
920 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
921 (page
| invert
) & chip
->pagemask
);
923 /* Call wait ready function */
924 status
= chip
->waitfunc(mtd
, chip
);
926 /* See if device thinks it succeeded */
928 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Error status = 0x%08x\n",
937 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
940 * @ofs: offset to start unlock from
941 * @len: length to unlock
943 * return - unlock status
945 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
949 struct nand_chip
*chip
= mtd
->priv
;
951 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
952 __func__
, (unsigned long long)ofs
, len
);
954 if (check_offs_len(mtd
, ofs
, len
))
957 /* Align to last block address if size addresses end of the device */
958 if (ofs
+ len
== mtd
->size
)
959 len
-= mtd
->erasesize
;
961 nand_get_device(chip
, mtd
, FL_UNLOCKING
);
963 /* Shift to get chip number */
964 chipnr
= ofs
>> chip
->chip_shift
;
966 chip
->select_chip(mtd
, chipnr
);
968 /* Check, if it is write protected */
969 if (nand_check_wp(mtd
)) {
970 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
976 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
979 /* de-select the NAND device */
980 chip
->select_chip(mtd
, -1);
982 nand_release_device(mtd
);
986 EXPORT_SYMBOL(nand_unlock
);
989 * nand_lock - [REPLACEABLE] locks all blocks present in the device
992 * @ofs: offset to start unlock from
993 * @len: length to unlock
995 * return - lock status
997 * This feature is not supported in many NAND parts. 'Micron' NAND parts
998 * do have this feature, but it allows only to lock all blocks, not for
999 * specified range for block.
1001 * Implementing 'lock' feature by making use of 'unlock', for now.
1003 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1006 int chipnr
, status
, page
;
1007 struct nand_chip
*chip
= mtd
->priv
;
1009 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
1010 __func__
, (unsigned long long)ofs
, len
);
1012 if (check_offs_len(mtd
, ofs
, len
))
1015 nand_get_device(chip
, mtd
, FL_LOCKING
);
1017 /* Shift to get chip number */
1018 chipnr
= ofs
>> chip
->chip_shift
;
1020 chip
->select_chip(mtd
, chipnr
);
1022 /* Check, if it is write protected */
1023 if (nand_check_wp(mtd
)) {
1024 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
1026 status
= MTD_ERASE_FAILED
;
1031 /* Submit address of first page to lock */
1032 page
= ofs
>> chip
->page_shift
;
1033 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1035 /* Call wait ready function */
1036 status
= chip
->waitfunc(mtd
, chip
);
1038 /* See if device thinks it succeeded */
1039 if (status
& 0x01) {
1040 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Error status = 0x%08x\n",
1046 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1049 /* de-select the NAND device */
1050 chip
->select_chip(mtd
, -1);
1052 nand_release_device(mtd
);
1056 EXPORT_SYMBOL(nand_lock
);
1059 * nand_read_page_raw - [Intern] read raw page data without ecc
1060 * @mtd: mtd info structure
1061 * @chip: nand chip info structure
1062 * @buf: buffer to store read data
1063 * @page: page number to read
1065 * Not for syndrome calculating ecc controllers, which use a special oob layout
1067 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1068 uint8_t *buf
, int page
)
1070 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1071 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1076 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1077 * @mtd: mtd info structure
1078 * @chip: nand chip info structure
1079 * @buf: buffer to store read data
1080 * @page: page number to read
1082 * We need a special oob layout and handling even when OOB isn't used.
1084 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1085 struct nand_chip
*chip
,
1086 uint8_t *buf
, int page
)
1088 int eccsize
= chip
->ecc
.size
;
1089 int eccbytes
= chip
->ecc
.bytes
;
1090 uint8_t *oob
= chip
->oob_poi
;
1093 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1094 chip
->read_buf(mtd
, buf
, eccsize
);
1097 if (chip
->ecc
.prepad
) {
1098 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1099 oob
+= chip
->ecc
.prepad
;
1102 chip
->read_buf(mtd
, oob
, eccbytes
);
1105 if (chip
->ecc
.postpad
) {
1106 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1107 oob
+= chip
->ecc
.postpad
;
1111 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1113 chip
->read_buf(mtd
, oob
, size
);
1119 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1120 * @mtd: mtd info structure
1121 * @chip: nand chip info structure
1122 * @buf: buffer to store read data
1123 * @page: page number to read
1125 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1126 uint8_t *buf
, int page
)
1128 int i
, eccsize
= chip
->ecc
.size
;
1129 int eccbytes
= chip
->ecc
.bytes
;
1130 int eccsteps
= chip
->ecc
.steps
;
1132 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1133 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1134 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1136 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, page
);
1138 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1139 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1141 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1142 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1144 eccsteps
= chip
->ecc
.steps
;
1147 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1150 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1152 mtd
->ecc_stats
.failed
++;
1154 mtd
->ecc_stats
.corrected
+= stat
;
1160 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1161 * @mtd: mtd info structure
1162 * @chip: nand chip info structure
1163 * @data_offs: offset of requested data within the page
1164 * @readlen: data length
1165 * @bufpoi: buffer to store read data
1167 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1168 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
)
1170 int start_step
, end_step
, num_steps
;
1171 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1173 int data_col_addr
, i
, gaps
= 0;
1174 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1175 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1178 /* Column address wihin the page aligned to ECC size (256bytes). */
1179 start_step
= data_offs
/ chip
->ecc
.size
;
1180 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1181 num_steps
= end_step
- start_step
+ 1;
1183 /* Data size aligned to ECC ecc.size*/
1184 datafrag_len
= num_steps
* chip
->ecc
.size
;
1185 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1187 data_col_addr
= start_step
* chip
->ecc
.size
;
1188 /* If we read not a page aligned data */
1189 if (data_col_addr
!= 0)
1190 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1192 p
= bufpoi
+ data_col_addr
;
1193 chip
->read_buf(mtd
, p
, datafrag_len
);
1196 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1197 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1199 /* The performance is faster if to position offsets
1200 according to ecc.pos. Let make sure here that
1201 there are no gaps in ecc positions */
1202 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1203 if (eccpos
[i
+ start_step
* chip
->ecc
.bytes
] + 1 !=
1204 eccpos
[i
+ start_step
* chip
->ecc
.bytes
+ 1]) {
1210 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1211 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1213 /* send the command to read the particular ecc bytes */
1214 /* take care about buswidth alignment in read_buf */
1215 index
= start_step
* chip
->ecc
.bytes
;
1217 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1218 aligned_len
= eccfrag_len
;
1219 if (eccpos
[index
] & (busw
- 1))
1221 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1224 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1225 mtd
->writesize
+ aligned_pos
, -1);
1226 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1229 for (i
= 0; i
< eccfrag_len
; i
++)
1230 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1232 p
= bufpoi
+ data_col_addr
;
1233 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1236 stat
= chip
->ecc
.correct(mtd
, p
,
1237 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1239 mtd
->ecc_stats
.failed
++;
1241 mtd
->ecc_stats
.corrected
+= stat
;
1247 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1248 * @mtd: mtd info structure
1249 * @chip: nand chip info structure
1250 * @buf: buffer to store read data
1251 * @page: page number to read
1253 * Not for syndrome calculating ecc controllers which need a special oob layout
1255 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1256 uint8_t *buf
, int page
)
1258 int i
, eccsize
= chip
->ecc
.size
;
1259 int eccbytes
= chip
->ecc
.bytes
;
1260 int eccsteps
= chip
->ecc
.steps
;
1262 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1263 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1264 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1266 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1267 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1268 chip
->read_buf(mtd
, p
, eccsize
);
1269 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1271 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1273 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1274 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1276 eccsteps
= chip
->ecc
.steps
;
1279 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1282 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1284 mtd
->ecc_stats
.failed
++;
1286 mtd
->ecc_stats
.corrected
+= stat
;
1292 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1293 * @mtd: mtd info structure
1294 * @chip: nand chip info structure
1295 * @buf: buffer to store read data
1296 * @page: page number to read
1298 * Hardware ECC for large page chips, require OOB to be read first.
1299 * For this ECC mode, the write_page method is re-used from ECC_HW.
1300 * These methods read/write ECC from the OOB area, unlike the
1301 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1302 * "infix ECC" scheme and reads/writes ECC from the data area, by
1303 * overwriting the NAND manufacturer bad block markings.
1305 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1306 struct nand_chip
*chip
, uint8_t *buf
, int page
)
1308 int i
, eccsize
= chip
->ecc
.size
;
1309 int eccbytes
= chip
->ecc
.bytes
;
1310 int eccsteps
= chip
->ecc
.steps
;
1312 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1313 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1314 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1316 /* Read the OOB area first */
1317 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1318 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1319 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1321 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1322 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1324 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1327 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1328 chip
->read_buf(mtd
, p
, eccsize
);
1329 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1331 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1333 mtd
->ecc_stats
.failed
++;
1335 mtd
->ecc_stats
.corrected
+= stat
;
1341 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1342 * @mtd: mtd info structure
1343 * @chip: nand chip info structure
1344 * @buf: buffer to store read data
1345 * @page: page number to read
1347 * The hw generator calculates the error syndrome automatically. Therefor
1348 * we need a special oob layout and handling.
1350 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1351 uint8_t *buf
, int page
)
1353 int i
, eccsize
= chip
->ecc
.size
;
1354 int eccbytes
= chip
->ecc
.bytes
;
1355 int eccsteps
= chip
->ecc
.steps
;
1357 uint8_t *oob
= chip
->oob_poi
;
1359 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1362 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1363 chip
->read_buf(mtd
, p
, eccsize
);
1365 if (chip
->ecc
.prepad
) {
1366 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1367 oob
+= chip
->ecc
.prepad
;
1370 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1371 chip
->read_buf(mtd
, oob
, eccbytes
);
1372 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1375 mtd
->ecc_stats
.failed
++;
1377 mtd
->ecc_stats
.corrected
+= stat
;
1381 if (chip
->ecc
.postpad
) {
1382 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1383 oob
+= chip
->ecc
.postpad
;
1387 /* Calculate remaining oob bytes */
1388 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1390 chip
->read_buf(mtd
, oob
, i
);
1396 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1397 * @chip: nand chip structure
1398 * @oob: oob destination address
1399 * @ops: oob ops structure
1400 * @len: size of oob to transfer
1402 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1403 struct mtd_oob_ops
*ops
, size_t len
)
1405 switch (ops
->mode
) {
1409 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1412 case MTD_OOB_AUTO
: {
1413 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1414 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1417 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1418 /* Read request not from offset 0 ? */
1419 if (unlikely(roffs
)) {
1420 if (roffs
>= free
->length
) {
1421 roffs
-= free
->length
;
1424 boffs
= free
->offset
+ roffs
;
1425 bytes
= min_t(size_t, len
,
1426 (free
->length
- roffs
));
1429 bytes
= min_t(size_t, len
, free
->length
);
1430 boffs
= free
->offset
;
1432 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1444 * nand_do_read_ops - [Internal] Read data with ECC
1446 * @mtd: MTD device structure
1447 * @from: offset to read from
1448 * @ops: oob ops structure
1450 * Internal function. Called with chip held.
1452 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1453 struct mtd_oob_ops
*ops
)
1455 int chipnr
, page
, realpage
, col
, bytes
, aligned
;
1456 struct nand_chip
*chip
= mtd
->priv
;
1457 struct mtd_ecc_stats stats
;
1458 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1461 uint32_t readlen
= ops
->len
;
1462 uint32_t oobreadlen
= ops
->ooblen
;
1463 uint32_t max_oobsize
= ops
->mode
== MTD_OOB_AUTO
?
1464 mtd
->oobavail
: mtd
->oobsize
;
1466 uint8_t *bufpoi
, *oob
, *buf
;
1468 stats
= mtd
->ecc_stats
;
1470 chipnr
= (int)(from
>> chip
->chip_shift
);
1471 chip
->select_chip(mtd
, chipnr
);
1473 realpage
= (int)(from
>> chip
->page_shift
);
1474 page
= realpage
& chip
->pagemask
;
1476 col
= (int)(from
& (mtd
->writesize
- 1));
1482 bytes
= min(mtd
->writesize
- col
, readlen
);
1483 aligned
= (bytes
== mtd
->writesize
);
1485 /* Is the current page in the buffer ? */
1486 if (realpage
!= chip
->pagebuf
|| oob
) {
1487 bufpoi
= aligned
? buf
: chip
->buffers
->databuf
;
1489 if (likely(sndcmd
)) {
1490 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1494 /* Now read the page into the buffer */
1495 if (unlikely(ops
->mode
== MTD_OOB_RAW
))
1496 ret
= chip
->ecc
.read_page_raw(mtd
, chip
,
1498 else if (!aligned
&& NAND_SUBPAGE_READ(chip
) && !oob
)
1499 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1500 col
, bytes
, bufpoi
);
1502 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1507 /* Transfer not aligned data */
1509 if (!NAND_SUBPAGE_READ(chip
) && !oob
&&
1510 !(mtd
->ecc_stats
.failed
- stats
.failed
))
1511 chip
->pagebuf
= realpage
;
1512 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1517 if (unlikely(oob
)) {
1519 int toread
= min(oobreadlen
, max_oobsize
);
1522 oob
= nand_transfer_oob(chip
,
1524 oobreadlen
-= toread
;
1528 if (!(chip
->options
& NAND_NO_READRDY
)) {
1530 * Apply delay or wait for ready/busy pin. Do
1531 * this before the AUTOINCR check, so no
1532 * problems arise if a chip which does auto
1533 * increment is marked as NOAUTOINCR by the
1536 if (!chip
->dev_ready
)
1537 udelay(chip
->chip_delay
);
1539 nand_wait_ready(mtd
);
1542 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1551 /* For subsequent reads align to page boundary. */
1553 /* Increment page address */
1556 page
= realpage
& chip
->pagemask
;
1557 /* Check, if we cross a chip boundary */
1560 chip
->select_chip(mtd
, -1);
1561 chip
->select_chip(mtd
, chipnr
);
1564 /* Check, if the chip supports auto page increment
1565 * or if we have hit a block boundary.
1567 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1571 ops
->retlen
= ops
->len
- (size_t) readlen
;
1573 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1578 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1581 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1585 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1586 * @mtd: MTD device structure
1587 * @from: offset to read from
1588 * @len: number of bytes to read
1589 * @retlen: pointer to variable to store the number of read bytes
1590 * @buf: the databuffer to put data
1592 * Get hold of the chip and call nand_do_read
1594 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1595 size_t *retlen
, uint8_t *buf
)
1597 struct nand_chip
*chip
= mtd
->priv
;
1600 /* Do not allow reads past end of device */
1601 if ((from
+ len
) > mtd
->size
)
1606 nand_get_device(chip
, mtd
, FL_READING
);
1608 chip
->ops
.len
= len
;
1609 chip
->ops
.datbuf
= buf
;
1610 chip
->ops
.oobbuf
= NULL
;
1612 ret
= nand_do_read_ops(mtd
, from
, &chip
->ops
);
1614 *retlen
= chip
->ops
.retlen
;
1616 nand_release_device(mtd
);
1622 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1623 * @mtd: mtd info structure
1624 * @chip: nand chip info structure
1625 * @page: page number to read
1626 * @sndcmd: flag whether to issue read command or not
1628 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1629 int page
, int sndcmd
)
1632 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1635 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1640 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1642 * @mtd: mtd info structure
1643 * @chip: nand chip info structure
1644 * @page: page number to read
1645 * @sndcmd: flag whether to issue read command or not
1647 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1648 int page
, int sndcmd
)
1650 uint8_t *buf
= chip
->oob_poi
;
1651 int length
= mtd
->oobsize
;
1652 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1653 int eccsize
= chip
->ecc
.size
;
1654 uint8_t *bufpoi
= buf
;
1655 int i
, toread
, sndrnd
= 0, pos
;
1657 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1658 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1660 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1661 if (mtd
->writesize
> 512)
1662 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1664 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1667 toread
= min_t(int, length
, chunk
);
1668 chip
->read_buf(mtd
, bufpoi
, toread
);
1673 chip
->read_buf(mtd
, bufpoi
, length
);
1679 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1680 * @mtd: mtd info structure
1681 * @chip: nand chip info structure
1682 * @page: page number to write
1684 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1688 const uint8_t *buf
= chip
->oob_poi
;
1689 int length
= mtd
->oobsize
;
1691 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1692 chip
->write_buf(mtd
, buf
, length
);
1693 /* Send command to program the OOB data */
1694 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1696 status
= chip
->waitfunc(mtd
, chip
);
1698 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1702 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1703 * with syndrome - only for large page flash !
1704 * @mtd: mtd info structure
1705 * @chip: nand chip info structure
1706 * @page: page number to write
1708 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1709 struct nand_chip
*chip
, int page
)
1711 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1712 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1713 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1714 const uint8_t *bufpoi
= chip
->oob_poi
;
1717 * data-ecc-data-ecc ... ecc-oob
1719 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1721 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1722 pos
= steps
* (eccsize
+ chunk
);
1727 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1728 for (i
= 0; i
< steps
; i
++) {
1730 if (mtd
->writesize
<= 512) {
1731 uint32_t fill
= 0xFFFFFFFF;
1735 int num
= min_t(int, len
, 4);
1736 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1741 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1742 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1746 len
= min_t(int, length
, chunk
);
1747 chip
->write_buf(mtd
, bufpoi
, len
);
1752 chip
->write_buf(mtd
, bufpoi
, length
);
1754 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1755 status
= chip
->waitfunc(mtd
, chip
);
1757 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1761 * nand_do_read_oob - [Intern] NAND read out-of-band
1762 * @mtd: MTD device structure
1763 * @from: offset to read from
1764 * @ops: oob operations description structure
1766 * NAND read out-of-band data from the spare area
1768 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1769 struct mtd_oob_ops
*ops
)
1771 int page
, realpage
, chipnr
, sndcmd
= 1;
1772 struct nand_chip
*chip
= mtd
->priv
;
1773 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1774 int readlen
= ops
->ooblen
;
1776 uint8_t *buf
= ops
->oobbuf
;
1778 DEBUG(MTD_DEBUG_LEVEL3
, "%s: from = 0x%08Lx, len = %i\n",
1779 __func__
, (unsigned long long)from
, readlen
);
1781 if (ops
->mode
== MTD_OOB_AUTO
)
1782 len
= chip
->ecc
.layout
->oobavail
;
1786 if (unlikely(ops
->ooboffs
>= len
)) {
1787 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to start read "
1788 "outside oob\n", __func__
);
1792 /* Do not allow reads past end of device */
1793 if (unlikely(from
>= mtd
->size
||
1794 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1795 (from
>> chip
->page_shift
)) * len
)) {
1796 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt read beyond end "
1797 "of device\n", __func__
);
1801 chipnr
= (int)(from
>> chip
->chip_shift
);
1802 chip
->select_chip(mtd
, chipnr
);
1804 /* Shift to get page */
1805 realpage
= (int)(from
>> chip
->page_shift
);
1806 page
= realpage
& chip
->pagemask
;
1809 sndcmd
= chip
->ecc
.read_oob(mtd
, chip
, page
, sndcmd
);
1811 len
= min(len
, readlen
);
1812 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1814 if (!(chip
->options
& NAND_NO_READRDY
)) {
1816 * Apply delay or wait for ready/busy pin. Do this
1817 * before the AUTOINCR check, so no problems arise if a
1818 * chip which does auto increment is marked as
1819 * NOAUTOINCR by the board driver.
1821 if (!chip
->dev_ready
)
1822 udelay(chip
->chip_delay
);
1824 nand_wait_ready(mtd
);
1831 /* Increment page address */
1834 page
= realpage
& chip
->pagemask
;
1835 /* Check, if we cross a chip boundary */
1838 chip
->select_chip(mtd
, -1);
1839 chip
->select_chip(mtd
, chipnr
);
1842 /* Check, if the chip supports auto page increment
1843 * or if we have hit a block boundary.
1845 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1849 ops
->oobretlen
= ops
->ooblen
;
1854 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1855 * @mtd: MTD device structure
1856 * @from: offset to read from
1857 * @ops: oob operation description structure
1859 * NAND read data and/or out-of-band data
1861 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1862 struct mtd_oob_ops
*ops
)
1864 struct nand_chip
*chip
= mtd
->priv
;
1865 int ret
= -ENOTSUPP
;
1869 /* Do not allow reads past end of device */
1870 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1871 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt read "
1872 "beyond end of device\n", __func__
);
1876 nand_get_device(chip
, mtd
, FL_READING
);
1878 switch (ops
->mode
) {
1889 ret
= nand_do_read_oob(mtd
, from
, ops
);
1891 ret
= nand_do_read_ops(mtd
, from
, ops
);
1894 nand_release_device(mtd
);
1900 * nand_write_page_raw - [Intern] raw page write function
1901 * @mtd: mtd info structure
1902 * @chip: nand chip info structure
1905 * Not for syndrome calculating ecc controllers, which use a special oob layout
1907 static void nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1910 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1911 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1915 * nand_write_page_raw_syndrome - [Intern] raw page write function
1916 * @mtd: mtd info structure
1917 * @chip: nand chip info structure
1920 * We need a special oob layout and handling even when ECC isn't checked.
1922 static void nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1923 struct nand_chip
*chip
,
1926 int eccsize
= chip
->ecc
.size
;
1927 int eccbytes
= chip
->ecc
.bytes
;
1928 uint8_t *oob
= chip
->oob_poi
;
1931 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1932 chip
->write_buf(mtd
, buf
, eccsize
);
1935 if (chip
->ecc
.prepad
) {
1936 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1937 oob
+= chip
->ecc
.prepad
;
1940 chip
->read_buf(mtd
, oob
, eccbytes
);
1943 if (chip
->ecc
.postpad
) {
1944 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1945 oob
+= chip
->ecc
.postpad
;
1949 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1951 chip
->write_buf(mtd
, oob
, size
);
1954 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1955 * @mtd: mtd info structure
1956 * @chip: nand chip info structure
1959 static void nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1962 int i
, eccsize
= chip
->ecc
.size
;
1963 int eccbytes
= chip
->ecc
.bytes
;
1964 int eccsteps
= chip
->ecc
.steps
;
1965 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1966 const uint8_t *p
= buf
;
1967 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1969 /* Software ecc calculation */
1970 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1971 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1973 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1974 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1976 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
1980 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
1985 static void nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1988 int i
, eccsize
= chip
->ecc
.size
;
1989 int eccbytes
= chip
->ecc
.bytes
;
1990 int eccsteps
= chip
->ecc
.steps
;
1991 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1992 const uint8_t *p
= buf
;
1993 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1995 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1996 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1997 chip
->write_buf(mtd
, p
, eccsize
);
1998 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2001 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2002 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2004 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2008 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
2009 * @mtd: mtd info structure
2010 * @chip: nand chip info structure
2013 * The hw generator calculates the error syndrome automatically. Therefor
2014 * we need a special oob layout and handling.
2016 static void nand_write_page_syndrome(struct mtd_info
*mtd
,
2017 struct nand_chip
*chip
, const uint8_t *buf
)
2019 int i
, eccsize
= chip
->ecc
.size
;
2020 int eccbytes
= chip
->ecc
.bytes
;
2021 int eccsteps
= chip
->ecc
.steps
;
2022 const uint8_t *p
= buf
;
2023 uint8_t *oob
= chip
->oob_poi
;
2025 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2027 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2028 chip
->write_buf(mtd
, p
, eccsize
);
2030 if (chip
->ecc
.prepad
) {
2031 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2032 oob
+= chip
->ecc
.prepad
;
2035 chip
->ecc
.calculate(mtd
, p
, oob
);
2036 chip
->write_buf(mtd
, oob
, eccbytes
);
2039 if (chip
->ecc
.postpad
) {
2040 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2041 oob
+= chip
->ecc
.postpad
;
2045 /* Calculate remaining oob bytes */
2046 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2048 chip
->write_buf(mtd
, oob
, i
);
2052 * nand_write_page - [REPLACEABLE] write one page
2053 * @mtd: MTD device structure
2054 * @chip: NAND chip descriptor
2055 * @buf: the data to write
2056 * @page: page number to write
2057 * @cached: cached programming
2058 * @raw: use _raw version of write_page
2060 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2061 const uint8_t *buf
, int page
, int cached
, int raw
)
2065 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2068 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
2070 chip
->ecc
.write_page(mtd
, chip
, buf
);
2073 * Cached progamming disabled for now, Not sure if its worth the
2074 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2078 if (!cached
|| !(chip
->options
& NAND_CACHEPRG
)) {
2080 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2081 status
= chip
->waitfunc(mtd
, chip
);
2083 * See if operation failed and additional status checks are
2086 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2087 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2090 if (status
& NAND_STATUS_FAIL
)
2093 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2094 status
= chip
->waitfunc(mtd
, chip
);
2097 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2098 /* Send command to read back the data */
2099 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
2101 if (chip
->verify_buf(mtd
, buf
, mtd
->writesize
))
2108 * nand_fill_oob - [Internal] Transfer client buffer to oob
2109 * @chip: nand chip structure
2110 * @oob: oob data buffer
2111 * @len: oob data write length
2112 * @ops: oob ops structure
2114 static uint8_t *nand_fill_oob(struct nand_chip
*chip
, uint8_t *oob
, size_t len
,
2115 struct mtd_oob_ops
*ops
)
2117 switch (ops
->mode
) {
2121 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2124 case MTD_OOB_AUTO
: {
2125 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2126 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2129 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2130 /* Write request not from offset 0 ? */
2131 if (unlikely(woffs
)) {
2132 if (woffs
>= free
->length
) {
2133 woffs
-= free
->length
;
2136 boffs
= free
->offset
+ woffs
;
2137 bytes
= min_t(size_t, len
,
2138 (free
->length
- woffs
));
2141 bytes
= min_t(size_t, len
, free
->length
);
2142 boffs
= free
->offset
;
2144 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2155 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2158 * nand_do_write_ops - [Internal] NAND write with ECC
2159 * @mtd: MTD device structure
2160 * @to: offset to write to
2161 * @ops: oob operations description structure
2163 * NAND write with ECC
2165 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2166 struct mtd_oob_ops
*ops
)
2168 int chipnr
, realpage
, page
, blockmask
, column
;
2169 struct nand_chip
*chip
= mtd
->priv
;
2170 uint32_t writelen
= ops
->len
;
2172 uint32_t oobwritelen
= ops
->ooblen
;
2173 uint32_t oobmaxlen
= ops
->mode
== MTD_OOB_AUTO
?
2174 mtd
->oobavail
: mtd
->oobsize
;
2176 uint8_t *oob
= ops
->oobbuf
;
2177 uint8_t *buf
= ops
->datbuf
;
2184 /* reject writes, which are not page aligned */
2185 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2186 printk(KERN_NOTICE
"%s: Attempt to write not "
2187 "page aligned data\n", __func__
);
2191 column
= to
& (mtd
->writesize
- 1);
2192 subpage
= column
|| (writelen
& (mtd
->writesize
- 1));
2197 chipnr
= (int)(to
>> chip
->chip_shift
);
2198 chip
->select_chip(mtd
, chipnr
);
2200 /* Check, if it is write protected */
2201 if (nand_check_wp(mtd
))
2204 realpage
= (int)(to
>> chip
->page_shift
);
2205 page
= realpage
& chip
->pagemask
;
2206 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2208 /* Invalidate the page cache, when we write to the cached page */
2209 if (to
<= (chip
->pagebuf
<< chip
->page_shift
) &&
2210 (chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2213 /* If we're not given explicit OOB data, let it be 0xFF */
2215 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2217 /* Don't allow multipage oob writes with offset */
2218 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
))
2222 int bytes
= mtd
->writesize
;
2223 int cached
= writelen
> bytes
&& page
!= blockmask
;
2224 uint8_t *wbuf
= buf
;
2226 /* Partial page write ? */
2227 if (unlikely(column
|| writelen
< (mtd
->writesize
- 1))) {
2229 bytes
= min_t(int, bytes
- column
, (int) writelen
);
2231 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2232 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2233 wbuf
= chip
->buffers
->databuf
;
2236 if (unlikely(oob
)) {
2237 size_t len
= min(oobwritelen
, oobmaxlen
);
2238 oob
= nand_fill_oob(chip
, oob
, len
, ops
);
2242 ret
= chip
->write_page(mtd
, chip
, wbuf
, page
, cached
,
2243 (ops
->mode
== MTD_OOB_RAW
));
2255 page
= realpage
& chip
->pagemask
;
2256 /* Check, if we cross a chip boundary */
2259 chip
->select_chip(mtd
, -1);
2260 chip
->select_chip(mtd
, chipnr
);
2264 ops
->retlen
= ops
->len
- writelen
;
2266 ops
->oobretlen
= ops
->ooblen
;
2271 * panic_nand_write - [MTD Interface] NAND write with ECC
2272 * @mtd: MTD device structure
2273 * @to: offset to write to
2274 * @len: number of bytes to write
2275 * @retlen: pointer to variable to store the number of written bytes
2276 * @buf: the data to write
2278 * NAND write with ECC. Used when performing writes in interrupt context, this
2279 * may for example be called by mtdoops when writing an oops while in panic.
2281 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2282 size_t *retlen
, const uint8_t *buf
)
2284 struct nand_chip
*chip
= mtd
->priv
;
2287 /* Do not allow reads past end of device */
2288 if ((to
+ len
) > mtd
->size
)
2293 /* Wait for the device to get ready. */
2294 panic_nand_wait(mtd
, chip
, 400);
2296 /* Grab the device. */
2297 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2299 chip
->ops
.len
= len
;
2300 chip
->ops
.datbuf
= (uint8_t *)buf
;
2301 chip
->ops
.oobbuf
= NULL
;
2303 ret
= nand_do_write_ops(mtd
, to
, &chip
->ops
);
2305 *retlen
= chip
->ops
.retlen
;
2310 * nand_write - [MTD Interface] NAND write with ECC
2311 * @mtd: MTD device structure
2312 * @to: offset to write to
2313 * @len: number of bytes to write
2314 * @retlen: pointer to variable to store the number of written bytes
2315 * @buf: the data to write
2317 * NAND write with ECC
2319 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2320 size_t *retlen
, const uint8_t *buf
)
2322 struct nand_chip
*chip
= mtd
->priv
;
2325 /* Do not allow reads past end of device */
2326 if ((to
+ len
) > mtd
->size
)
2331 nand_get_device(chip
, mtd
, FL_WRITING
);
2333 chip
->ops
.len
= len
;
2334 chip
->ops
.datbuf
= (uint8_t *)buf
;
2335 chip
->ops
.oobbuf
= NULL
;
2337 ret
= nand_do_write_ops(mtd
, to
, &chip
->ops
);
2339 *retlen
= chip
->ops
.retlen
;
2341 nand_release_device(mtd
);
2347 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2348 * @mtd: MTD device structure
2349 * @to: offset to write to
2350 * @ops: oob operation description structure
2352 * NAND write out-of-band
2354 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2355 struct mtd_oob_ops
*ops
)
2357 int chipnr
, page
, status
, len
;
2358 struct nand_chip
*chip
= mtd
->priv
;
2360 DEBUG(MTD_DEBUG_LEVEL3
, "%s: to = 0x%08x, len = %i\n",
2361 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2363 if (ops
->mode
== MTD_OOB_AUTO
)
2364 len
= chip
->ecc
.layout
->oobavail
;
2368 /* Do not allow write past end of page */
2369 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2370 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to write "
2371 "past end of page\n", __func__
);
2375 if (unlikely(ops
->ooboffs
>= len
)) {
2376 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to start "
2377 "write outside oob\n", __func__
);
2381 /* Do not allow write past end of device */
2382 if (unlikely(to
>= mtd
->size
||
2383 ops
->ooboffs
+ ops
->ooblen
>
2384 ((mtd
->size
>> chip
->page_shift
) -
2385 (to
>> chip
->page_shift
)) * len
)) {
2386 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt write beyond "
2387 "end of device\n", __func__
);
2391 chipnr
= (int)(to
>> chip
->chip_shift
);
2392 chip
->select_chip(mtd
, chipnr
);
2394 /* Shift to get page */
2395 page
= (int)(to
>> chip
->page_shift
);
2398 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2399 * of my DiskOnChip 2000 test units) will clear the whole data page too
2400 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2401 * it in the doc2000 driver in August 1999. dwmw2.
2403 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2405 /* Check, if it is write protected */
2406 if (nand_check_wp(mtd
))
2409 /* Invalidate the page cache, if we write to the cached page */
2410 if (page
== chip
->pagebuf
)
2413 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2414 nand_fill_oob(chip
, ops
->oobbuf
, ops
->ooblen
, ops
);
2415 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2416 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2421 ops
->oobretlen
= ops
->ooblen
;
2427 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2428 * @mtd: MTD device structure
2429 * @to: offset to write to
2430 * @ops: oob operation description structure
2432 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2433 struct mtd_oob_ops
*ops
)
2435 struct nand_chip
*chip
= mtd
->priv
;
2436 int ret
= -ENOTSUPP
;
2440 /* Do not allow writes past end of device */
2441 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2442 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt write beyond "
2443 "end of device\n", __func__
);
2447 nand_get_device(chip
, mtd
, FL_WRITING
);
2449 switch (ops
->mode
) {
2460 ret
= nand_do_write_oob(mtd
, to
, ops
);
2462 ret
= nand_do_write_ops(mtd
, to
, ops
);
2465 nand_release_device(mtd
);
2470 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2471 * @mtd: MTD device structure
2472 * @page: the page address of the block which will be erased
2474 * Standard erase command for NAND chips
2476 static void single_erase_cmd(struct mtd_info
*mtd
, int page
)
2478 struct nand_chip
*chip
= mtd
->priv
;
2479 /* Send commands to erase a block */
2480 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2481 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2485 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2486 * @mtd: MTD device structure
2487 * @page: the page address of the block which will be erased
2489 * AND multi block erase command function
2490 * Erase 4 consecutive blocks
2492 static void multi_erase_cmd(struct mtd_info
*mtd
, int page
)
2494 struct nand_chip
*chip
= mtd
->priv
;
2495 /* Send commands to erase a block */
2496 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2497 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2498 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2499 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2500 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2504 * nand_erase - [MTD Interface] erase block(s)
2505 * @mtd: MTD device structure
2506 * @instr: erase instruction
2508 * Erase one ore more blocks
2510 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2512 return nand_erase_nand(mtd
, instr
, 0);
2515 #define BBT_PAGE_MASK 0xffffff3f
2517 * nand_erase_nand - [Internal] erase block(s)
2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
2520 * @allowbbt: allow erasing the bbt area
2522 * Erase one ore more blocks
2524 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2527 int page
, status
, pages_per_block
, ret
, chipnr
;
2528 struct nand_chip
*chip
= mtd
->priv
;
2529 loff_t rewrite_bbt
[NAND_MAX_CHIPS
] = {0};
2530 unsigned int bbt_masked_page
= 0xffffffff;
2533 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
2534 __func__
, (unsigned long long)instr
->addr
,
2535 (unsigned long long)instr
->len
);
2537 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2540 instr
->fail_addr
= MTD_FAIL_ADDR_UNKNOWN
;
2542 /* Grab the lock and see if the device is available */
2543 nand_get_device(chip
, mtd
, FL_ERASING
);
2545 /* Shift to get first page */
2546 page
= (int)(instr
->addr
>> chip
->page_shift
);
2547 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2549 /* Calculate pages in each block */
2550 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2552 /* Select the NAND device */
2553 chip
->select_chip(mtd
, chipnr
);
2555 /* Check, if it is write protected */
2556 if (nand_check_wp(mtd
)) {
2557 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
2559 instr
->state
= MTD_ERASE_FAILED
;
2564 * If BBT requires refresh, set the BBT page mask to see if the BBT
2565 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2566 * can not be matched. This is also done when the bbt is actually
2567 * erased to avoid recusrsive updates
2569 if (chip
->options
& BBT_AUTO_REFRESH
&& !allowbbt
)
2570 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] & BBT_PAGE_MASK
;
2572 /* Loop through the pages */
2575 instr
->state
= MTD_ERASING
;
2579 * heck if we have a bad block, we do not erase bad blocks !
2581 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2582 chip
->page_shift
, 0, allowbbt
)) {
2583 printk(KERN_WARNING
"%s: attempt to erase a bad block "
2584 "at page 0x%08x\n", __func__
, page
);
2585 instr
->state
= MTD_ERASE_FAILED
;
2590 * Invalidate the page cache, if we erase the block which
2591 * contains the current cached page
2593 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2594 (page
+ pages_per_block
))
2597 chip
->erase_cmd(mtd
, page
& chip
->pagemask
);
2599 status
= chip
->waitfunc(mtd
, chip
);
2602 * See if operation failed and additional status checks are
2605 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2606 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2609 /* See if block erase succeeded */
2610 if (status
& NAND_STATUS_FAIL
) {
2611 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Failed erase, "
2612 "page 0x%08x\n", __func__
, page
);
2613 instr
->state
= MTD_ERASE_FAILED
;
2615 ((loff_t
)page
<< chip
->page_shift
);
2620 * If BBT requires refresh, set the BBT rewrite flag to the
2623 if (bbt_masked_page
!= 0xffffffff &&
2624 (page
& BBT_PAGE_MASK
) == bbt_masked_page
)
2625 rewrite_bbt
[chipnr
] =
2626 ((loff_t
)page
<< chip
->page_shift
);
2628 /* Increment page address and decrement length */
2629 len
-= (1 << chip
->phys_erase_shift
);
2630 page
+= pages_per_block
;
2632 /* Check, if we cross a chip boundary */
2633 if (len
&& !(page
& chip
->pagemask
)) {
2635 chip
->select_chip(mtd
, -1);
2636 chip
->select_chip(mtd
, chipnr
);
2639 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2640 * page mask to see if this BBT should be rewritten
2642 if (bbt_masked_page
!= 0xffffffff &&
2643 (chip
->bbt_td
->options
& NAND_BBT_PERCHIP
))
2644 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] &
2648 instr
->state
= MTD_ERASE_DONE
;
2652 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2654 /* Deselect and wake up anyone waiting on the device */
2655 nand_release_device(mtd
);
2657 /* Do call back function */
2659 mtd_erase_callback(instr
);
2662 * If BBT requires refresh and erase was successful, rewrite any
2663 * selected bad block tables
2665 if (bbt_masked_page
== 0xffffffff || ret
)
2668 for (chipnr
= 0; chipnr
< chip
->numchips
; chipnr
++) {
2669 if (!rewrite_bbt
[chipnr
])
2671 /* update the BBT for chip */
2672 DEBUG(MTD_DEBUG_LEVEL0
, "%s: nand_update_bbt "
2673 "(%d:0x%0llx 0x%0x)\n", __func__
, chipnr
,
2674 rewrite_bbt
[chipnr
], chip
->bbt_td
->pages
[chipnr
]);
2675 nand_update_bbt(mtd
, rewrite_bbt
[chipnr
]);
2678 /* Return more or less happy */
2683 * nand_sync - [MTD Interface] sync
2684 * @mtd: MTD device structure
2686 * Sync is actually a wait for chip ready function
2688 static void nand_sync(struct mtd_info
*mtd
)
2690 struct nand_chip
*chip
= mtd
->priv
;
2692 DEBUG(MTD_DEBUG_LEVEL3
, "%s: called\n", __func__
);
2694 /* Grab the lock and see if the device is available */
2695 nand_get_device(chip
, mtd
, FL_SYNCING
);
2696 /* Release it and go back */
2697 nand_release_device(mtd
);
2701 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2702 * @mtd: MTD device structure
2703 * @offs: offset relative to mtd start
2705 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2707 /* Check for invalid offset */
2708 if (offs
> mtd
->size
)
2711 return nand_block_checkbad(mtd
, offs
, 1, 0);
2715 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2716 * @mtd: MTD device structure
2717 * @ofs: offset relative to mtd start
2719 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2721 struct nand_chip
*chip
= mtd
->priv
;
2724 ret
= nand_block_isbad(mtd
, ofs
);
2726 /* If it was bad already, return success and do nothing. */
2732 return chip
->block_markbad(mtd
, ofs
);
2736 * nand_suspend - [MTD Interface] Suspend the NAND flash
2737 * @mtd: MTD device structure
2739 static int nand_suspend(struct mtd_info
*mtd
)
2741 struct nand_chip
*chip
= mtd
->priv
;
2743 return nand_get_device(chip
, mtd
, FL_PM_SUSPENDED
);
2747 * nand_resume - [MTD Interface] Resume the NAND flash
2748 * @mtd: MTD device structure
2750 static void nand_resume(struct mtd_info
*mtd
)
2752 struct nand_chip
*chip
= mtd
->priv
;
2754 if (chip
->state
== FL_PM_SUSPENDED
)
2755 nand_release_device(mtd
);
2757 printk(KERN_ERR
"%s called for a chip which is not "
2758 "in suspended state\n", __func__
);
2762 * Set default functions
2764 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2766 /* check for proper chip_delay setup, set 20us if not */
2767 if (!chip
->chip_delay
)
2768 chip
->chip_delay
= 20;
2770 /* check, if a user supplied command function given */
2771 if (chip
->cmdfunc
== NULL
)
2772 chip
->cmdfunc
= nand_command
;
2774 /* check, if a user supplied wait function given */
2775 if (chip
->waitfunc
== NULL
)
2776 chip
->waitfunc
= nand_wait
;
2778 if (!chip
->select_chip
)
2779 chip
->select_chip
= nand_select_chip
;
2780 if (!chip
->read_byte
)
2781 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2782 if (!chip
->read_word
)
2783 chip
->read_word
= nand_read_word
;
2784 if (!chip
->block_bad
)
2785 chip
->block_bad
= nand_block_bad
;
2786 if (!chip
->block_markbad
)
2787 chip
->block_markbad
= nand_default_block_markbad
;
2788 if (!chip
->write_buf
)
2789 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2790 if (!chip
->read_buf
)
2791 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2792 if (!chip
->verify_buf
)
2793 chip
->verify_buf
= busw
? nand_verify_buf16
: nand_verify_buf
;
2794 if (!chip
->scan_bbt
)
2795 chip
->scan_bbt
= nand_default_bbt
;
2797 if (!chip
->controller
) {
2798 chip
->controller
= &chip
->hwcontrol
;
2799 spin_lock_init(&chip
->controller
->lock
);
2800 init_waitqueue_head(&chip
->controller
->wq
);
2806 * sanitize ONFI strings so we can safely print them
2808 static void sanitize_string(uint8_t *s
, size_t len
)
2812 /* null terminate */
2815 /* remove non printable chars */
2816 for (i
= 0; i
< len
- 1; i
++) {
2817 if (s
[i
] < ' ' || s
[i
] > 127)
2821 /* remove trailing spaces */
2825 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2830 for (i
= 0; i
< 8; i
++)
2831 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2838 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2840 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2843 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2847 /* try ONFI for unknow chip or LP */
2848 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2849 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2850 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2853 printk(KERN_INFO
"ONFI flash detected\n");
2854 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2855 for (i
= 0; i
< 3; i
++) {
2856 chip
->read_buf(mtd
, (uint8_t *)p
, sizeof(*p
));
2857 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2858 le16_to_cpu(p
->crc
)) {
2859 printk(KERN_INFO
"ONFI param page %d valid\n", i
);
2868 val
= le16_to_cpu(p
->revision
);
2870 chip
->onfi_version
= 23;
2871 else if (val
& (1 << 4))
2872 chip
->onfi_version
= 22;
2873 else if (val
& (1 << 3))
2874 chip
->onfi_version
= 21;
2875 else if (val
& (1 << 2))
2876 chip
->onfi_version
= 20;
2877 else if (val
& (1 << 1))
2878 chip
->onfi_version
= 10;
2880 chip
->onfi_version
= 0;
2882 if (!chip
->onfi_version
) {
2883 printk(KERN_INFO
"%s: unsupported ONFI version: %d\n",
2888 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2889 sanitize_string(p
->model
, sizeof(p
->model
));
2891 mtd
->name
= p
->model
;
2892 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
2893 mtd
->erasesize
= le32_to_cpu(p
->pages_per_block
) * mtd
->writesize
;
2894 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
2895 chip
->chipsize
= (uint64_t)le32_to_cpu(p
->blocks_per_lun
) * mtd
->erasesize
;
2897 if (le16_to_cpu(p
->features
) & 1)
2898 busw
= NAND_BUSWIDTH_16
;
2900 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
2901 chip
->options
|= (NAND_NO_READRDY
|
2902 NAND_NO_AUTOINCR
) & NAND_CHIPOPTIONS_MSK
;
2908 * Get the flash and manufacturer id and lookup if the type is supported
2910 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
2911 struct nand_chip
*chip
,
2913 int *maf_id
, int *dev_id
,
2914 struct nand_flash_dev
*type
)
2920 /* Select the device */
2921 chip
->select_chip(mtd
, 0);
2924 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2927 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2929 /* Send the command for reading device ID */
2930 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2932 /* Read manufacturer and device IDs */
2933 *maf_id
= chip
->read_byte(mtd
);
2934 *dev_id
= chip
->read_byte(mtd
);
2936 /* Try again to make sure, as some systems the bus-hold or other
2937 * interface concerns can cause random data which looks like a
2938 * possibly credible NAND flash to appear. If the two results do
2939 * not match, ignore the device completely.
2942 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2944 for (i
= 0; i
< 2; i
++)
2945 id_data
[i
] = chip
->read_byte(mtd
);
2947 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
2948 printk(KERN_INFO
"%s: second ID read did not match "
2949 "%02x,%02x against %02x,%02x\n", __func__
,
2950 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
2951 return ERR_PTR(-ENODEV
);
2955 type
= nand_flash_ids
;
2957 for (; type
->name
!= NULL
; type
++)
2958 if (*dev_id
== type
->id
)
2961 chip
->onfi_version
= 0;
2962 if (!type
->name
|| !type
->pagesize
) {
2963 /* Check is chip is ONFI compliant */
2964 ret
= nand_flash_detect_onfi(mtd
, chip
, busw
);
2969 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2971 /* Read entire ID string */
2973 for (i
= 0; i
< 8; i
++)
2974 id_data
[i
] = chip
->read_byte(mtd
);
2977 return ERR_PTR(-ENODEV
);
2980 mtd
->name
= type
->name
;
2982 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
2984 if (!type
->pagesize
&& chip
->init_size
) {
2985 /* set the pagesize, oobsize, erasesize by the driver*/
2986 busw
= chip
->init_size(mtd
, chip
, id_data
);
2987 } else if (!type
->pagesize
) {
2989 /* The 3rd id byte holds MLC / multichip data */
2990 chip
->cellinfo
= id_data
[2];
2991 /* The 4th id byte is the important one */
2995 * Field definitions are in the following datasheets:
2996 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2997 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2999 * Check for wraparound + Samsung ID + nonzero 6th byte
3000 * to decide what to do.
3002 if (id_data
[0] == id_data
[6] && id_data
[1] == id_data
[7] &&
3003 id_data
[0] == NAND_MFR_SAMSUNG
&&
3004 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3005 id_data
[5] != 0x00) {
3007 mtd
->writesize
= 2048 << (extid
& 0x03);
3010 switch (extid
& 0x03) {
3025 /* Calc blocksize */
3026 mtd
->erasesize
= (128 * 1024) <<
3027 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3031 mtd
->writesize
= 1024 << (extid
& 0x03);
3034 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3035 (mtd
->writesize
>> 9);
3037 /* Calc blocksize. Blocksize is multiples of 64KiB */
3038 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3040 /* Get buswidth information */
3041 busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3045 * Old devices have chip data hardcoded in the device id table
3047 mtd
->erasesize
= type
->erasesize
;
3048 mtd
->writesize
= type
->pagesize
;
3049 mtd
->oobsize
= mtd
->writesize
/ 32;
3050 busw
= type
->options
& NAND_BUSWIDTH_16
;
3053 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3054 * some Spansion chips have erasesize that conflicts with size
3055 * listed in nand_ids table
3056 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3058 if (*maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 &&
3059 id_data
[5] == 0x00 && id_data
[6] == 0x00 &&
3060 id_data
[7] == 0x00 && mtd
->writesize
== 512) {
3061 mtd
->erasesize
= 128 * 1024;
3062 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3065 /* Get chip options, preserve non chip based options */
3066 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
3067 chip
->options
|= type
->options
& NAND_CHIPOPTIONS_MSK
;
3069 /* Check if chip is a not a samsung device. Do not clear the
3070 * options for chips which are not having an extended id.
3072 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3073 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3077 * Set chip as a default. Board drivers can override it, if necessary
3079 chip
->options
|= NAND_NO_AUTOINCR
;
3081 /* Try to identify manufacturer */
3082 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3083 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3088 * Check, if buswidth is correct. Hardware drivers should set
3091 if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3092 printk(KERN_INFO
"NAND device: Manufacturer ID:"
3093 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
,
3094 *dev_id
, nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3095 printk(KERN_WARNING
"NAND bus width %d instead %d bit\n",
3096 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3098 return ERR_PTR(-EINVAL
);
3101 /* Calculate the address shift from the page size */
3102 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3103 /* Convert chipsize to number of pages per chip -1. */
3104 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3106 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3107 ffs(mtd
->erasesize
) - 1;
3108 if (chip
->chipsize
& 0xffffffff)
3109 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3111 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3112 chip
->chip_shift
+= 32 - 1;
3115 /* Set the bad block position */
3116 if (mtd
->writesize
> 512 || (busw
& NAND_BUSWIDTH_16
))
3117 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3119 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3122 * Bad block marker is stored in the last page of each block
3123 * on Samsung and Hynix MLC devices; stored in first two pages
3124 * of each block on Micron devices with 2KiB pages and on
3125 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3126 * only the first page.
3128 if ((chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3129 (*maf_id
== NAND_MFR_SAMSUNG
||
3130 *maf_id
== NAND_MFR_HYNIX
))
3131 chip
->options
|= NAND_BBT_SCANLASTPAGE
;
3132 else if ((!(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3133 (*maf_id
== NAND_MFR_SAMSUNG
||
3134 *maf_id
== NAND_MFR_HYNIX
||
3135 *maf_id
== NAND_MFR_TOSHIBA
||
3136 *maf_id
== NAND_MFR_AMD
)) ||
3137 (mtd
->writesize
== 2048 &&
3138 *maf_id
== NAND_MFR_MICRON
))
3139 chip
->options
|= NAND_BBT_SCAN2NDPAGE
;
3142 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3144 if (!(busw
& NAND_BUSWIDTH_16
) &&
3145 *maf_id
== NAND_MFR_STMICRO
&&
3146 mtd
->writesize
== 2048) {
3147 chip
->options
|= NAND_BBT_SCANBYTE1AND6
;
3148 chip
->badblockpos
= 0;
3151 /* Check for AND chips with 4 page planes */
3152 if (chip
->options
& NAND_4PAGE_ARRAY
)
3153 chip
->erase_cmd
= multi_erase_cmd
;
3155 chip
->erase_cmd
= single_erase_cmd
;
3157 /* Do not replace user supplied command function ! */
3158 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3159 chip
->cmdfunc
= nand_command_lp
;
3161 /* TODO onfi flash name */
3162 printk(KERN_INFO
"NAND device: Manufacturer ID:"
3163 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
, *dev_id
,
3164 nand_manuf_ids
[maf_idx
].name
,
3165 chip
->onfi_version
? chip
->onfi_params
.model
: type
->name
);
3171 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3172 * @mtd: MTD device structure
3173 * @maxchips: Number of chips to scan for
3174 * @table: Alternative NAND ID table
3176 * This is the first phase of the normal nand_scan() function. It
3177 * reads the flash ID and sets up MTD fields accordingly.
3179 * The mtd->owner field must be set to the module of the caller.
3181 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3182 struct nand_flash_dev
*table
)
3184 int i
, busw
, nand_maf_id
, nand_dev_id
;
3185 struct nand_chip
*chip
= mtd
->priv
;
3186 struct nand_flash_dev
*type
;
3188 /* Get buswidth to select the correct functions */
3189 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3190 /* Set the default functions */
3191 nand_set_defaults(chip
, busw
);
3193 /* Read the flash type */
3194 type
= nand_get_flash_type(mtd
, chip
, busw
,
3195 &nand_maf_id
, &nand_dev_id
, table
);
3198 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3199 printk(KERN_WARNING
"No NAND device found.\n");
3200 chip
->select_chip(mtd
, -1);
3201 return PTR_ERR(type
);
3204 /* Check for a chip array */
3205 for (i
= 1; i
< maxchips
; i
++) {
3206 chip
->select_chip(mtd
, i
);
3207 /* See comment in nand_get_flash_type for reset */
3208 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3209 /* Send the command for reading device ID */
3210 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3211 /* Read manufacturer and device IDs */
3212 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3213 nand_dev_id
!= chip
->read_byte(mtd
))
3217 printk(KERN_INFO
"%d NAND chips detected\n", i
);
3219 /* Store the number of chips and calc total size for mtd */
3221 mtd
->size
= i
* chip
->chipsize
;
3225 EXPORT_SYMBOL(nand_scan_ident
);
3229 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3230 * @mtd: MTD device structure
3232 * This is the second phase of the normal nand_scan() function. It
3233 * fills out all the uninitialized function pointers with the defaults
3234 * and scans for a bad block table if appropriate.
3236 int nand_scan_tail(struct mtd_info
*mtd
)
3239 struct nand_chip
*chip
= mtd
->priv
;
3241 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3242 chip
->buffers
= kmalloc(sizeof(*chip
->buffers
), GFP_KERNEL
);
3246 /* Set the internal oob buffer location, just after the page data */
3247 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3250 * If no default placement scheme is given, select an appropriate one
3252 if (!chip
->ecc
.layout
&& (chip
->ecc
.mode
!= NAND_ECC_SOFT_BCH
)) {
3253 switch (mtd
->oobsize
) {
3255 chip
->ecc
.layout
= &nand_oob_8
;
3258 chip
->ecc
.layout
= &nand_oob_16
;
3261 chip
->ecc
.layout
= &nand_oob_64
;
3264 chip
->ecc
.layout
= &nand_oob_128
;
3267 printk(KERN_WARNING
"No oob scheme defined for "
3268 "oobsize %d\n", mtd
->oobsize
);
3273 if (!chip
->write_page
)
3274 chip
->write_page
= nand_write_page
;
3277 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3278 * selected and we have 256 byte pagesize fallback to software ECC
3281 switch (chip
->ecc
.mode
) {
3282 case NAND_ECC_HW_OOB_FIRST
:
3283 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3284 if (!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3286 printk(KERN_WARNING
"No ECC functions supplied; "
3287 "Hardware ECC not possible\n");
3290 if (!chip
->ecc
.read_page
)
3291 chip
->ecc
.read_page
= nand_read_page_hwecc_oob_first
;
3294 /* Use standard hwecc read page function ? */
3295 if (!chip
->ecc
.read_page
)
3296 chip
->ecc
.read_page
= nand_read_page_hwecc
;
3297 if (!chip
->ecc
.write_page
)
3298 chip
->ecc
.write_page
= nand_write_page_hwecc
;
3299 if (!chip
->ecc
.read_page_raw
)
3300 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3301 if (!chip
->ecc
.write_page_raw
)
3302 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3303 if (!chip
->ecc
.read_oob
)
3304 chip
->ecc
.read_oob
= nand_read_oob_std
;
3305 if (!chip
->ecc
.write_oob
)
3306 chip
->ecc
.write_oob
= nand_write_oob_std
;
3308 case NAND_ECC_HW_SYNDROME
:
3309 if ((!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3310 !chip
->ecc
.hwctl
) &&
3311 (!chip
->ecc
.read_page
||
3312 chip
->ecc
.read_page
== nand_read_page_hwecc
||
3313 !chip
->ecc
.write_page
||
3314 chip
->ecc
.write_page
== nand_write_page_hwecc
)) {
3315 printk(KERN_WARNING
"No ECC functions supplied; "
3316 "Hardware ECC not possible\n");
3319 /* Use standard syndrome read/write page function ? */
3320 if (!chip
->ecc
.read_page
)
3321 chip
->ecc
.read_page
= nand_read_page_syndrome
;
3322 if (!chip
->ecc
.write_page
)
3323 chip
->ecc
.write_page
= nand_write_page_syndrome
;
3324 if (!chip
->ecc
.read_page_raw
)
3325 chip
->ecc
.read_page_raw
= nand_read_page_raw_syndrome
;
3326 if (!chip
->ecc
.write_page_raw
)
3327 chip
->ecc
.write_page_raw
= nand_write_page_raw_syndrome
;
3328 if (!chip
->ecc
.read_oob
)
3329 chip
->ecc
.read_oob
= nand_read_oob_syndrome
;
3330 if (!chip
->ecc
.write_oob
)
3331 chip
->ecc
.write_oob
= nand_write_oob_syndrome
;
3333 if (mtd
->writesize
>= chip
->ecc
.size
)
3335 printk(KERN_WARNING
"%d byte HW ECC not possible on "
3336 "%d byte page size, fallback to SW ECC\n",
3337 chip
->ecc
.size
, mtd
->writesize
);
3338 chip
->ecc
.mode
= NAND_ECC_SOFT
;
3341 chip
->ecc
.calculate
= nand_calculate_ecc
;
3342 chip
->ecc
.correct
= nand_correct_data
;
3343 chip
->ecc
.read_page
= nand_read_page_swecc
;
3344 chip
->ecc
.read_subpage
= nand_read_subpage
;
3345 chip
->ecc
.write_page
= nand_write_page_swecc
;
3346 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3347 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3348 chip
->ecc
.read_oob
= nand_read_oob_std
;
3349 chip
->ecc
.write_oob
= nand_write_oob_std
;
3350 if (!chip
->ecc
.size
)
3351 chip
->ecc
.size
= 256;
3352 chip
->ecc
.bytes
= 3;
3355 case NAND_ECC_SOFT_BCH
:
3356 if (!mtd_nand_has_bch()) {
3357 printk(KERN_WARNING
"CONFIG_MTD_ECC_BCH not enabled\n");
3360 chip
->ecc
.calculate
= nand_bch_calculate_ecc
;
3361 chip
->ecc
.correct
= nand_bch_correct_data
;
3362 chip
->ecc
.read_page
= nand_read_page_swecc
;
3363 chip
->ecc
.read_subpage
= nand_read_subpage
;
3364 chip
->ecc
.write_page
= nand_write_page_swecc
;
3365 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3366 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3367 chip
->ecc
.read_oob
= nand_read_oob_std
;
3368 chip
->ecc
.write_oob
= nand_write_oob_std
;
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
3373 * Otherwise, default to 4 bits for large page devices
3375 if (!chip
->ecc
.size
&& (mtd
->oobsize
>= 64)) {
3376 chip
->ecc
.size
= 512;
3377 chip
->ecc
.bytes
= 7;
3379 chip
->ecc
.priv
= nand_bch_init(mtd
,
3383 if (!chip
->ecc
.priv
) {
3384 printk(KERN_WARNING
"BCH ECC initialization failed!\n");
3390 printk(KERN_WARNING
"NAND_ECC_NONE selected by board driver. "
3391 "This is not recommended !!\n");
3392 chip
->ecc
.read_page
= nand_read_page_raw
;
3393 chip
->ecc
.write_page
= nand_write_page_raw
;
3394 chip
->ecc
.read_oob
= nand_read_oob_std
;
3395 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3396 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3397 chip
->ecc
.write_oob
= nand_write_oob_std
;
3398 chip
->ecc
.size
= mtd
->writesize
;
3399 chip
->ecc
.bytes
= 0;
3403 printk(KERN_WARNING
"Invalid NAND_ECC_MODE %d\n",
3409 * The number of bytes available for a client to place data into
3410 * the out of band area
3412 chip
->ecc
.layout
->oobavail
= 0;
3413 for (i
= 0; chip
->ecc
.layout
->oobfree
[i
].length
3414 && i
< ARRAY_SIZE(chip
->ecc
.layout
->oobfree
); i
++)
3415 chip
->ecc
.layout
->oobavail
+=
3416 chip
->ecc
.layout
->oobfree
[i
].length
;
3417 mtd
->oobavail
= chip
->ecc
.layout
->oobavail
;
3420 * Set the number of read / write steps for one page depending on ECC
3423 chip
->ecc
.steps
= mtd
->writesize
/ chip
->ecc
.size
;
3424 if (chip
->ecc
.steps
* chip
->ecc
.size
!= mtd
->writesize
) {
3425 printk(KERN_WARNING
"Invalid ecc parameters\n");
3428 chip
->ecc
.total
= chip
->ecc
.steps
* chip
->ecc
.bytes
;
3431 * Allow subpage writes up to ecc.steps. Not possible for MLC
3434 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
3435 !(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3436 switch (chip
->ecc
.steps
) {
3438 mtd
->subpage_sft
= 1;
3443 mtd
->subpage_sft
= 2;
3447 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3449 /* Initialize state */
3450 chip
->state
= FL_READY
;
3452 /* De-select the device */
3453 chip
->select_chip(mtd
, -1);
3455 /* Invalidate the pagebuffer reference */
3458 /* Fill in remaining MTD driver data */
3459 mtd
->type
= MTD_NANDFLASH
;
3460 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3462 mtd
->erase
= nand_erase
;
3464 mtd
->unpoint
= NULL
;
3465 mtd
->read
= nand_read
;
3466 mtd
->write
= nand_write
;
3467 mtd
->panic_write
= panic_nand_write
;
3468 mtd
->read_oob
= nand_read_oob
;
3469 mtd
->write_oob
= nand_write_oob
;
3470 mtd
->sync
= nand_sync
;
3473 mtd
->suspend
= nand_suspend
;
3474 mtd
->resume
= nand_resume
;
3475 mtd
->block_isbad
= nand_block_isbad
;
3476 mtd
->block_markbad
= nand_block_markbad
;
3477 mtd
->writebufsize
= mtd
->writesize
;
3479 /* propagate ecc.layout to mtd_info */
3480 mtd
->ecclayout
= chip
->ecc
.layout
;
3482 /* Check, if we should skip the bad block table scan */
3483 if (chip
->options
& NAND_SKIP_BBTSCAN
)
3486 /* Build bad block table */
3487 return chip
->scan_bbt(mtd
);
3489 EXPORT_SYMBOL(nand_scan_tail
);
3491 /* is_module_text_address() isn't exported, and it's mostly a pointless
3492 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3493 * to call us from in-kernel code if the core NAND support is modular. */
3495 #define caller_is_module() (1)
3497 #define caller_is_module() \
3498 is_module_text_address((unsigned long)__builtin_return_address(0))
3502 * nand_scan - [NAND Interface] Scan for the NAND device
3503 * @mtd: MTD device structure
3504 * @maxchips: Number of chips to scan for
3506 * This fills out all the uninitialized function pointers
3507 * with the defaults.
3508 * The flash ID is read and the mtd/chip structures are
3509 * filled with the appropriate values.
3510 * The mtd->owner field must be set to the module of the caller
3513 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
3517 /* Many callers got this wrong, so check for it for a while... */
3518 if (!mtd
->owner
&& caller_is_module()) {
3519 printk(KERN_CRIT
"%s called with NULL mtd->owner!\n",
3524 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
3526 ret
= nand_scan_tail(mtd
);
3529 EXPORT_SYMBOL(nand_scan
);
3532 * nand_release - [NAND Interface] Free resources held by the NAND device
3533 * @mtd: MTD device structure
3535 void nand_release(struct mtd_info
*mtd
)
3537 struct nand_chip
*chip
= mtd
->priv
;
3539 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
3540 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
3542 #ifdef CONFIG_MTD_PARTITIONS
3543 /* Deregister partitions */
3544 del_mtd_partitions(mtd
);
3546 /* Deregister the device */
3547 del_mtd_device(mtd
);
3549 /* Free bad block table memory */
3551 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3552 kfree(chip
->buffers
);
3554 /* Free bad block descriptor memory */
3555 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
3556 & NAND_BBT_DYNAMICSTRUCT
)
3557 kfree(chip
->badblock_pattern
);
3559 EXPORT_SYMBOL_GPL(nand_release
);
3561 static int __init
nand_base_init(void)
3563 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
3567 static void __exit
nand_base_exit(void)
3569 led_trigger_unregister_simple(nand_led_trigger
);
3572 module_init(nand_base_init
);
3573 module_exit(nand_base_exit
);
3575 MODULE_LICENSE("GPL");
3576 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3577 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3578 MODULE_DESCRIPTION("Generic NAND flash driver code");