drivers/mtd/nand/txx9ndfmc.c

   1 /*
   2  * TXx9 NAND flash memory controller driver
   3  * Based on RBTX49xx patch from CELF patch archive.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * (C) Copyright TOSHIBA CORPORATION 2004-2007
  10  * All Rights Reserved.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/nand_ecc.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/io.h>
  22 #include <asm/txx9/ndfmc.h>
  23
  24 /* TXX9 NDFMC Registers */
  25 #define TXX9_NDFDTR     0x00
  26 #define TXX9_NDFMCR     0x04
  27 #define TXX9_NDFSR      0x08
  28 #define TXX9_NDFISR     0x0c
  29 #define TXX9_NDFIMR     0x10
  30 #define TXX9_NDFSPR     0x14
  31 #define TXX9_NDFRSTR    0x18    /* not TX4939 */
  32
  33 /* NDFMCR : NDFMC Mode Control */
  34 #define TXX9_NDFMCR_WE  0x80
  35 #define TXX9_NDFMCR_ECC_ALL     0x60
  36 #define TXX9_NDFMCR_ECC_RESET   0x60
  37 #define TXX9_NDFMCR_ECC_READ    0x40
  38 #define TXX9_NDFMCR_ECC_ON      0x20
  39 #define TXX9_NDFMCR_ECC_OFF     0x00
  40 #define TXX9_NDFMCR_CE  0x10
  41 #define TXX9_NDFMCR_BSPRT       0x04    /* TX4925/TX4926 only */
  42 #define TXX9_NDFMCR_ALE 0x02
  43 #define TXX9_NDFMCR_CLE 0x01
  44 /* TX4939 only */
  45 #define TXX9_NDFMCR_X16 0x0400
  46 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
  47 #define TXX9_NDFMCR_DMAREQ_NODMA        0x0000
  48 #define TXX9_NDFMCR_DMAREQ_128  0x0100
  49 #define TXX9_NDFMCR_DMAREQ_256  0x0200
  50 #define TXX9_NDFMCR_DMAREQ_512  0x0300
  51 #define TXX9_NDFMCR_CS_MASK     0x0c
  52 #define TXX9_NDFMCR_CS(ch)      ((ch) << 2)
  53
  54 /* NDFMCR : NDFMC Status */
  55 #define TXX9_NDFSR_BUSY 0x80
  56 /* TX4939 only */
  57 #define TXX9_NDFSR_DMARUN       0x40
  58
  59 /* NDFMCR : NDFMC Reset */
  60 #define TXX9_NDFRSTR_RST        0x01
  61
  62 struct txx9ndfmc_priv {
  63         struct platform_device *dev;
  64         struct nand_chip chip;
  65         struct mtd_info mtd;
  66         int cs;
  67         const char *mtdname;
  68 };
  69
  70 #define MAX_TXX9NDFMC_DEV       4
  71 struct txx9ndfmc_drvdata {
  72         struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
  73         void __iomem *base;
  74         unsigned char hold;     /* in gbusclock */
  75         unsigned char spw;      /* in gbusclock */
  76         struct nand_hw_control hw_control;
  77 #ifdef CONFIG_MTD_PARTITIONS
  78         struct mtd_partition *parts[MAX_TXX9NDFMC_DEV];
  79 #endif
  80 };
  81
  82 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
  83 {
  84         struct nand_chip *chip = mtd->priv;
  85         struct txx9ndfmc_priv *txx9_priv = chip->priv;
  86         return txx9_priv->dev;
  87 }
  88
  89 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
  90 {
  91         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
  92         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
  93
  94         return drvdata->base + (reg << plat->shift);
  95 }
  96
  97 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
  98 {
  99         return __raw_readl(ndregaddr(dev, reg));
 100 }
 101
 102 static void txx9ndfmc_write(struct platform_device *dev,
 103                             u32 val, unsigned int reg)
 104 {
 105         __raw_writel(val, ndregaddr(dev, reg));
 106 }
 107
 108 static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
 109 {
 110         struct platform_device *dev = mtd_to_platdev(mtd);
 111
 112         return txx9ndfmc_read(dev, TXX9_NDFDTR);
 113 }
 114
 115 static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 116                                 int len)
 117 {
 118         struct platform_device *dev = mtd_to_platdev(mtd);
 119         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 120         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 121
 122         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
 123         while (len--)
 124                 __raw_writel(*buf++, ndfdtr);
 125         txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
 126 }
 127
 128 static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 129 {
 130         struct platform_device *dev = mtd_to_platdev(mtd);
 131         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 132
 133         while (len--)
 134                 *buf++ = __raw_readl(ndfdtr);
 135 }
 136
 137 static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
 138                                 int len)
 139 {
 140         struct platform_device *dev = mtd_to_platdev(mtd);
 141         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 142
 143         while (len--)
 144                 if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
 145                         return -EFAULT;
 146         return 0;
 147 }
 148
 149 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 150                                unsigned int ctrl)
 151 {
 152         struct nand_chip *chip = mtd->priv;
 153         struct txx9ndfmc_priv *txx9_priv = chip->priv;
 154         struct platform_device *dev = txx9_priv->dev;
 155         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 156
 157         if (ctrl & NAND_CTRL_CHANGE) {
 158                 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 159
 160                 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
 161                 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
 162                 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
 163                 /* TXX9_NDFMCR_CE bit is 0:high 1:low */
 164                 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
 165                 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
 166                         mcr &= ~TXX9_NDFMCR_CS_MASK;
 167                         mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
 168                 }
 169                 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
 170         }
 171         if (cmd != NAND_CMD_NONE)
 172                 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
 173         if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
 174                 /* dummy write to update external latch */
 175                 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
 176                         txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
 177         }
 178         mmiowb();
 179 }
 180
 181 static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
 182 {
 183         struct platform_device *dev = mtd_to_platdev(mtd);
 184
 185         return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
 186 }
 187
 188 static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 189                                    uint8_t *ecc_code)
 190 {
 191         struct platform_device *dev = mtd_to_platdev(mtd);
 192         struct nand_chip *chip = mtd->priv;
 193         int eccbytes;
 194         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 195
 196         mcr &= ~TXX9_NDFMCR_ECC_ALL;
 197         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 198         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
 199         for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
 200                 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 201                 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 202                 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 203                 ecc_code += 3;
 204         }
 205         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 206         return 0;
 207 }
 208
 209 static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
 210                 unsigned char *read_ecc, unsigned char *calc_ecc)
 211 {
 212         struct nand_chip *chip = mtd->priv;
 213         int eccsize;
 214         int corrected = 0;
 215         int stat;
 216
 217         for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
 218                 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
 219                 if (stat < 0)
 220                         return stat;
 221                 corrected += stat;
 222                 buf += 256;
 223                 read_ecc += 3;
 224                 calc_ecc += 3;
 225         }
 226         return corrected;
 227 }
 228
 229 static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
 230 {
 231         struct platform_device *dev = mtd_to_platdev(mtd);
 232         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 233
 234         mcr &= ~TXX9_NDFMCR_ECC_ALL;
 235         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
 236         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 237         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
 238 }
 239
 240 static void txx9ndfmc_initialize(struct platform_device *dev)
 241 {
 242         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 243         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
 244         int tmout = 100;
 245
 246         if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
 247                 ; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
 248         else {
 249                 /* reset NDFMC */
 250                 txx9ndfmc_write(dev,
 251                                 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
 252                                 TXX9_NDFRSTR_RST,
 253                                 TXX9_NDFRSTR);
 254                 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
 255                         if (--tmout == 0) {
 256                                 dev_err(&dev->dev, "reset failed.\n");
 257                                 break;
 258                         }
 259                         udelay(1);
 260                 }
 261         }
 262         /* setup Hold Time, Strobe Pulse Width */
 263         txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
 264         txx9ndfmc_write(dev,
 265                         (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
 266                         TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
 267 }
 268
 269 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
 270         DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
 271
 272 static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
 273 {
 274         struct nand_chip *chip = mtd->priv;
 275         int ret;
 276
 277         ret = nand_scan_ident(mtd, 1, NULL);
 278         if (!ret) {
 279                 if (mtd->writesize >= 512) {
 280                         /* Hardware ECC 6 byte ECC per 512 Byte data */
 281                         chip->ecc.size = 512;
 282                         chip->ecc.bytes = 6;
 283                 }
 284                 ret = nand_scan_tail(mtd);
 285         }
 286         return ret;
 287 }
 288
 289 static int __init txx9ndfmc_probe(struct platform_device *dev)
 290 {
 291         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 292 #ifdef CONFIG_MTD_PARTITIONS
 293         static const char *probes[] = { "cmdlinepart", NULL };
 294 #endif
 295         int hold, spw;
 296         int i;
 297         struct txx9ndfmc_drvdata *drvdata;
 298         unsigned long gbusclk = plat->gbus_clock;
 299         struct resource *res;
 300
 301         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 302         if (!res)
 303                 return -ENODEV;
 304         drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
 305         if (!drvdata)
 306                 return -ENOMEM;
 307         if (!devm_request_mem_region(&dev->dev, res->start,
 308                                      resource_size(res), dev_name(&dev->dev)))
 309                 return -EBUSY;
 310         drvdata->base = devm_ioremap(&dev->dev, res->start,
 311                                      resource_size(res));
 312         if (!drvdata->base)
 313                 return -EBUSY;
 314
 315         hold = plat->hold ?: 20; /* tDH */
 316         spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
 317
 318         hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
 319         spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
 320         if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
 321                 hold -= 2;      /* actual hold time : (HOLD + 2) BUSCLK */
 322         spw -= 1;       /* actual wait time : (SPW + 1) BUSCLK */
 323         hold = clamp(hold, 1, 15);
 324         drvdata->hold = hold;
 325         spw = clamp(spw, 1, 15);
 326         drvdata->spw = spw;
 327         dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
 328                  (gbusclk + 500000) / 1000000, hold, spw);
 329
 330         spin_lock_init(&drvdata->hw_control.lock);
 331         init_waitqueue_head(&drvdata->hw_control.wq);
 332
 333         platform_set_drvdata(dev, drvdata);
 334         txx9ndfmc_initialize(dev);
 335
 336         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
 337                 struct txx9ndfmc_priv *txx9_priv;
 338                 struct nand_chip *chip;
 339                 struct mtd_info *mtd;
 340 #ifdef CONFIG_MTD_PARTITIONS
 341                 int nr_parts;
 342 #endif
 343
 344                 if (!(plat->ch_mask & (1 << i)))
 345                         continue;
 346                 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
 347                                     GFP_KERNEL);
 348                 if (!txx9_priv) {
 349                         dev_err(&dev->dev, "Unable to allocate "
 350                                 "TXx9 NDFMC MTD device structure.\n");
 351                         continue;
 352                 }
 353                 chip = &txx9_priv->chip;
 354                 mtd = &txx9_priv->mtd;
 355                 mtd->owner = THIS_MODULE;
 356
 357                 mtd->priv = chip;
 358
 359                 chip->read_byte = txx9ndfmc_read_byte;
 360                 chip->read_buf = txx9ndfmc_read_buf;
 361                 chip->write_buf = txx9ndfmc_write_buf;
 362                 chip->verify_buf = txx9ndfmc_verify_buf;
 363                 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
 364                 chip->dev_ready = txx9ndfmc_dev_ready;
 365                 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
 366                 chip->ecc.correct = txx9ndfmc_correct_data;
 367                 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
 368                 chip->ecc.mode = NAND_ECC_HW;
 369                 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
 370                 chip->ecc.size = 256;
 371                 chip->ecc.bytes = 3;
 372                 chip->chip_delay = 100;
 373                 chip->controller = &drvdata->hw_control;
 374
 375                 chip->priv = txx9_priv;
 376                 txx9_priv->dev = dev;
 377
 378                 if (plat->ch_mask != 1) {
 379                         txx9_priv->cs = i;
 380                         txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
 381                                                        dev_name(&dev->dev), i);
 382                 } else {
 383                         txx9_priv->cs = -1;
 384                         txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
 385                                                      GFP_KERNEL);
 386                 }
 387                 if (!txx9_priv->mtdname) {
 388                         kfree(txx9_priv);
 389                         dev_err(&dev->dev, "Unable to allocate MTD name.\n");
 390                         continue;
 391                 }
 392                 if (plat->wide_mask & (1 << i))
 393                         chip->options |= NAND_BUSWIDTH_16;
 394
 395                 if (txx9ndfmc_nand_scan(mtd)) {
 396                         kfree(txx9_priv->mtdname);
 397                         kfree(txx9_priv);
 398                         continue;
 399                 }
 400                 mtd->name = txx9_priv->mtdname;
 401
 402 #ifdef CONFIG_MTD_PARTITIONS
 403                 nr_parts = parse_mtd_partitions(mtd, probes,
 404                                                 &drvdata->parts[i], 0);
 405                 if (nr_parts > 0)
 406                         add_mtd_partitions(mtd, drvdata->parts[i], nr_parts);
 407 #endif
 408                 add_mtd_device(mtd);
 409                 drvdata->mtds[i] = mtd;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int __exit txx9ndfmc_remove(struct platform_device *dev)
 416 {
 417         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
 418         int i;
 419
 420         platform_set_drvdata(dev, NULL);
 421         if (!drvdata)
 422                 return 0;
 423         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
 424                 struct mtd_info *mtd = drvdata->mtds[i];
 425                 struct nand_chip *chip;
 426                 struct txx9ndfmc_priv *txx9_priv;
 427
 428                 if (!mtd)
 429                         continue;
 430                 chip = mtd->priv;
 431                 txx9_priv = chip->priv;
 432
 433                 nand_release(mtd);
 434 #ifdef CONFIG_MTD_PARTITIONS
 435                 kfree(drvdata->parts[i]);
 436 #endif
 437                 kfree(txx9_priv->mtdname);
 438                 kfree(txx9_priv);
 439         }
 440         return 0;
 441 }
 442
 443 #ifdef CONFIG_PM
 444 static int txx9ndfmc_resume(struct platform_device *dev)
 445 {
 446         if (platform_get_drvdata(dev))
 447                 txx9ndfmc_initialize(dev);
 448         return 0;
 449 }
 450 #else
 451 #define txx9ndfmc_resume NULL
 452 #endif
 453
 454 static struct platform_driver txx9ndfmc_driver = {
 455         .remove         = __exit_p(txx9ndfmc_remove),
 456         .resume         = txx9ndfmc_resume,
 457         .driver         = {
 458                 .name   = "txx9ndfmc",
 459                 .owner  = THIS_MODULE,
 460         },
 461 };
 462
 463 static int __init txx9ndfmc_init(void)
 464 {
 465         return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
 466 }
 467
 468 static void __exit txx9ndfmc_exit(void)
 469 {
 470         platform_driver_unregister(&txx9ndfmc_driver);
 471 }
 472
 473 module_init(txx9ndfmc_init);
 474 module_exit(txx9ndfmc_exit);
 475
 476 MODULE_LICENSE("GPL");
 477 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
 478 MODULE_ALIAS("platform:txx9ndfmc");