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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / net / atlx / atl1.c
blob67f40b9c16edb0a15f70f3af6d0efbf57a55c56b
1 /*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
32 * This version is adapted from the Attansic reference driver.
33 *
34 * TODO:
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
47 #include <asm/atomic.h>
48 #include <asm/byteorder.h>
49
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
58 #include <linux/in.h>
59 #include <linux/interrupt.h>
60 #include <linux/ip.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
71 #include <linux/pm.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
80
81 #include <net/checksum.h>
82
83 #include "atl1.h"
84
85 #define ATLX_DRIVER_VERSION "2.1.3"
86 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
87 Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
88 MODULE_LICENSE("GPL");
89 MODULE_VERSION(ATLX_DRIVER_VERSION);
90
91 /* Temporary hack for merging atl1 and atl2 */
92 #include "atlx.c"
93
94 static const struct ethtool_ops atl1_ethtool_ops;
95
96 /*
97 * This is the only thing that needs to be changed to adjust the
98 * maximum number of ports that the driver can manage.
99 */
100 #define ATL1_MAX_NIC 4
101
102 #define OPTION_UNSET -1
103 #define OPTION_DISABLED 0
104 #define OPTION_ENABLED 1
105
106 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
107
108 /*
109 * Interrupt Moderate Timer in units of 2 us
110 *
111 * Valid Range: 10-65535
112 *
113 * Default Value: 100 (200us)
114 */
115 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
116 static unsigned int num_int_mod_timer;
117 module_param_array_named(int_mod_timer, int_mod_timer, int,
118 &num_int_mod_timer, 0);
119 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
120
121 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
122 #define MAX_INT_MOD_CNT 65000
123 #define MIN_INT_MOD_CNT 50
124
125 struct atl1_option {
126 enum { enable_option, range_option, list_option } type;
127 char *name;
128 char *err;
129 int def;
130 union {
131 struct { /* range_option info */
132 int min;
133 int max;
134 } r;
135 struct { /* list_option info */
136 int nr;
137 struct atl1_opt_list {
138 int i;
139 char *str;
140 } *p;
141 } l;
142 } arg;
143 };
144
145 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
146 struct pci_dev *pdev)
147 {
148 if (*value == OPTION_UNSET) {
149 *value = opt->def;
150 return 0;
151 }
152
153 switch (opt->type) {
154 case enable_option:
155 switch (*value) {
156 case OPTION_ENABLED:
157 dev_info(&pdev->dev, "%s enabled\n", opt->name);
158 return 0;
159 case OPTION_DISABLED:
160 dev_info(&pdev->dev, "%s disabled\n", opt->name);
161 return 0;
162 }
163 break;
164 case range_option:
165 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
166 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
167 *value);
168 return 0;
169 }
170 break;
171 case list_option:{
172 int i;
173 struct atl1_opt_list *ent;
174
175 for (i = 0; i < opt->arg.l.nr; i++) {
176 ent = &opt->arg.l.p[i];
177 if (*value == ent->i) {
178 if (ent->str[0] != '\0')
179 dev_info(&pdev->dev, "%s\n",
180 ent->str);
181 return 0;
182 }
183 }
184 }
185 break;
186
187 default:
188 break;
189 }
190
191 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
192 opt->name, *value, opt->err);
193 *value = opt->def;
194 return -1;
195 }
196
197 /*
198 * atl1_check_options - Range Checking for Command Line Parameters
199 * @adapter: board private structure
200 *
201 * This routine checks all command line parameters for valid user
202 * input. If an invalid value is given, or if no user specified
203 * value exists, a default value is used. The final value is stored
204 * in a variable in the adapter structure.
205 */
206 static void __devinit atl1_check_options(struct atl1_adapter *adapter)
207 {
208 struct pci_dev *pdev = adapter->pdev;
209 int bd = adapter->bd_number;
210 if (bd >= ATL1_MAX_NIC) {
211 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
212 dev_notice(&pdev->dev, "using defaults for all values\n");
213 }
214 { /* Interrupt Moderate Timer */
215 struct atl1_option opt = {
216 .type = range_option,
217 .name = "Interrupt Moderator Timer",
218 .err = "using default of "
219 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
220 .def = DEFAULT_INT_MOD_CNT,
221 .arg = {.r = {.min = MIN_INT_MOD_CNT,
222 .max = MAX_INT_MOD_CNT} }
223 };
224 int val;
225 if (num_int_mod_timer > bd) {
226 val = int_mod_timer[bd];
227 atl1_validate_option(&val, &opt, pdev);
228 adapter->imt = (u16) val;
229 } else
230 adapter->imt = (u16) (opt.def);
231 }
232 }
233
234 /*
235 * atl1_pci_tbl - PCI Device ID Table
236 */
237 static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
238 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
239 /* required last entry */
240 {0,}
241 };
242 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
243
244 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
245 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
246
247 static int debug = -1;
248 module_param(debug, int, 0);
249 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
250
251 /*
252 * Reset the transmit and receive units; mask and clear all interrupts.
253 * hw - Struct containing variables accessed by shared code
254 * return : 0 or idle status (if error)
255 */
256 static s32 atl1_reset_hw(struct atl1_hw *hw)
257 {
258 struct pci_dev *pdev = hw->back->pdev;
259 struct atl1_adapter *adapter = hw->back;
260 u32 icr;
261 int i;
262
263 /*
264 * Clear Interrupt mask to stop board from generating
265 * interrupts & Clear any pending interrupt events
266 */
267 /*
268 * iowrite32(0, hw->hw_addr + REG_IMR);
269 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
270 */
271
272 /*
273 * Issue Soft Reset to the MAC. This will reset the chip's
274 * transmit, receive, DMA. It will not effect
275 * the current PCI configuration. The global reset bit is self-
276 * clearing, and should clear within a microsecond.
277 */
278 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
279 ioread32(hw->hw_addr + REG_MASTER_CTRL);
280
281 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
282 ioread16(hw->hw_addr + REG_PHY_ENABLE);
283
284 /* delay about 1ms */
285 msleep(1);
286
287 /* Wait at least 10ms for All module to be Idle */
288 for (i = 0; i < 10; i++) {
289 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
290 if (!icr)
291 break;
292 /* delay 1 ms */
293 msleep(1);
294 /* FIXME: still the right way to do this? */
295 cpu_relax();
296 }
297
298 if (icr) {
299 if (netif_msg_hw(adapter))
300 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
301 return icr;
302 }
303
304 return 0;
305 }
306
307 /* function about EEPROM
308 *
309 * check_eeprom_exist
310 * return 0 if eeprom exist
311 */
312 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
313 {
314 u32 value;
315 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
316 if (value & SPI_FLASH_CTRL_EN_VPD) {
317 value &= ~SPI_FLASH_CTRL_EN_VPD;
318 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
319 }
320
321 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
322 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
323 }
324
325 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
326 {
327 int i;
328 u32 control;
329
330 if (offset & 3)
331 /* address do not align */
332 return false;
333
334 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
335 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
336 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
337 ioread32(hw->hw_addr + REG_VPD_CAP);
338
339 for (i = 0; i < 10; i++) {
340 msleep(2);
341 control = ioread32(hw->hw_addr + REG_VPD_CAP);
342 if (control & VPD_CAP_VPD_FLAG)
343 break;
344 }
345 if (control & VPD_CAP_VPD_FLAG) {
346 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
347 return true;
348 }
349 /* timeout */
350 return false;
351 }
352
353 /*
354 * Reads the value from a PHY register
355 * hw - Struct containing variables accessed by shared code
356 * reg_addr - address of the PHY register to read
357 */
358 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
359 {
360 u32 val;
361 int i;
362
363 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
364 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
365 MDIO_CLK_SEL_SHIFT;
366 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
367 ioread32(hw->hw_addr + REG_MDIO_CTRL);
368
369 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
370 udelay(2);
371 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
372 if (!(val & (MDIO_START | MDIO_BUSY)))
373 break;
374 }
375 if (!(val & (MDIO_START | MDIO_BUSY))) {
376 *phy_data = (u16) val;
377 return 0;
378 }
379 return ATLX_ERR_PHY;
380 }
381
382 #define CUSTOM_SPI_CS_SETUP 2
383 #define CUSTOM_SPI_CLK_HI 2
384 #define CUSTOM_SPI_CLK_LO 2
385 #define CUSTOM_SPI_CS_HOLD 2
386 #define CUSTOM_SPI_CS_HI 3
387
388 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
389 {
390 int i;
391 u32 value;
392
393 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
394 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
395
396 value = SPI_FLASH_CTRL_WAIT_READY |
397 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
398 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
399 SPI_FLASH_CTRL_CLK_HI_MASK) <<
400 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
401 SPI_FLASH_CTRL_CLK_LO_MASK) <<
402 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
403 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
404 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
405 SPI_FLASH_CTRL_CS_HI_MASK) <<
406 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
407 SPI_FLASH_CTRL_INS_SHIFT;
408
409 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
410
411 value |= SPI_FLASH_CTRL_START;
412 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
413 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
414
415 for (i = 0; i < 10; i++) {
416 msleep(1);
417 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
418 if (!(value & SPI_FLASH_CTRL_START))
419 break;
420 }
421
422 if (value & SPI_FLASH_CTRL_START)
423 return false;
424
425 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
426
427 return true;
428 }
429
430 /*
431 * get_permanent_address
432 * return 0 if get valid mac address,
433 */
434 static int atl1_get_permanent_address(struct atl1_hw *hw)
435 {
436 u32 addr[2];
437 u32 i, control;
438 u16 reg;
439 u8 eth_addr[ETH_ALEN];
440 bool key_valid;
441
442 if (is_valid_ether_addr(hw->perm_mac_addr))
443 return 0;
444
445 /* init */
446 addr[0] = addr[1] = 0;
447
448 if (!atl1_check_eeprom_exist(hw)) {
449 reg = 0;
450 key_valid = false;
451 /* Read out all EEPROM content */
452 i = 0;
453 while (1) {
454 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
455 if (key_valid) {
456 if (reg == REG_MAC_STA_ADDR)
457 addr[0] = control;
458 else if (reg == (REG_MAC_STA_ADDR + 4))
459 addr[1] = control;
460 key_valid = false;
461 } else if ((control & 0xff) == 0x5A) {
462 key_valid = true;
463 reg = (u16) (control >> 16);
464 } else
465 break;
466 } else
467 /* read error */
468 break;
469 i += 4;
470 }
471
472 *(u32 *) &eth_addr[2] = swab32(addr[0]);
473 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
474 if (is_valid_ether_addr(eth_addr)) {
475 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
476 return 0;
477 }
478 }
479
480 /* see if SPI FLAGS exist ? */
481 addr[0] = addr[1] = 0;
482 reg = 0;
483 key_valid = false;
484 i = 0;
485 while (1) {
486 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
487 if (key_valid) {
488 if (reg == REG_MAC_STA_ADDR)
489 addr[0] = control;
490 else if (reg == (REG_MAC_STA_ADDR + 4))
491 addr[1] = control;
492 key_valid = false;
493 } else if ((control & 0xff) == 0x5A) {
494 key_valid = true;
495 reg = (u16) (control >> 16);
496 } else
497 /* data end */
498 break;
499 } else
500 /* read error */
501 break;
502 i += 4;
503 }
504
505 *(u32 *) &eth_addr[2] = swab32(addr[0]);
506 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
507 if (is_valid_ether_addr(eth_addr)) {
508 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
509 return 0;
510 }
511
512 /*
513 * On some motherboards, the MAC address is written by the
514 * BIOS directly to the MAC register during POST, and is
515 * not stored in eeprom. If all else thus far has failed
516 * to fetch the permanent MAC address, try reading it directly.
517 */
518 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
519 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
520 *(u32 *) &eth_addr[2] = swab32(addr[0]);
521 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
522 if (is_valid_ether_addr(eth_addr)) {
523 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
524 return 0;
525 }
526
527 return 1;
528 }
529
530 /*
531 * Reads the adapter's MAC address from the EEPROM
532 * hw - Struct containing variables accessed by shared code
533 */
534 static s32 atl1_read_mac_addr(struct atl1_hw *hw)
535 {
536 u16 i;
537
538 if (atl1_get_permanent_address(hw))
539 random_ether_addr(hw->perm_mac_addr);
540
541 for (i = 0; i < ETH_ALEN; i++)
542 hw->mac_addr[i] = hw->perm_mac_addr[i];
543 return 0;
544 }
545
546 /*
547 * Hashes an address to determine its location in the multicast table
548 * hw - Struct containing variables accessed by shared code
549 * mc_addr - the multicast address to hash
550 *
551 * atl1_hash_mc_addr
552 * purpose
553 * set hash value for a multicast address
554 * hash calcu processing :
555 * 1. calcu 32bit CRC for multicast address
556 * 2. reverse crc with MSB to LSB
557 */
558 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
559 {
560 u32 crc32, value = 0;
561 int i;
562
563 crc32 = ether_crc_le(6, mc_addr);
564 for (i = 0; i < 32; i++)
565 value |= (((crc32 >> i) & 1) << (31 - i));
566
567 return value;
568 }
569
570 /*
571 * Sets the bit in the multicast table corresponding to the hash value.
572 * hw - Struct containing variables accessed by shared code
573 * hash_value - Multicast address hash value
574 */
575 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
576 {
577 u32 hash_bit, hash_reg;
578 u32 mta;
579
580 /*
581 * The HASH Table is a register array of 2 32-bit registers.
582 * It is treated like an array of 64 bits. We want to set
583 * bit BitArray[hash_value]. So we figure out what register
584 * the bit is in, read it, OR in the new bit, then write
585 * back the new value. The register is determined by the
586 * upper 7 bits of the hash value and the bit within that
587 * register are determined by the lower 5 bits of the value.
588 */
589 hash_reg = (hash_value >> 31) & 0x1;
590 hash_bit = (hash_value >> 26) & 0x1F;
591 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
592 mta |= (1 << hash_bit);
593 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
594 }
595
596 /*
597 * Writes a value to a PHY register
598 * hw - Struct containing variables accessed by shared code
599 * reg_addr - address of the PHY register to write
600 * data - data to write to the PHY
601 */
602 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
603 {
604 int i;
605 u32 val;
606
607 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
608 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
609 MDIO_SUP_PREAMBLE |
610 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
611 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
612 ioread32(hw->hw_addr + REG_MDIO_CTRL);
613
614 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
615 udelay(2);
616 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
617 if (!(val & (MDIO_START | MDIO_BUSY)))
618 break;
619 }
620
621 if (!(val & (MDIO_START | MDIO_BUSY)))
622 return 0;
623
624 return ATLX_ERR_PHY;
625 }
626
627 /*
628 * Make L001's PHY out of Power Saving State (bug)
629 * hw - Struct containing variables accessed by shared code
630 * when power on, L001's PHY always on Power saving State
631 * (Gigabit Link forbidden)
632 */
633 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
634 {
635 s32 ret;
636 ret = atl1_write_phy_reg(hw, 29, 0x0029);
637 if (ret)
638 return ret;
639 return atl1_write_phy_reg(hw, 30, 0);
640 }
641
642 /*
643 * Resets the PHY and make all config validate
644 * hw - Struct containing variables accessed by shared code
645 *
646 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
647 */
648 static s32 atl1_phy_reset(struct atl1_hw *hw)
649 {
650 struct pci_dev *pdev = hw->back->pdev;
651 struct atl1_adapter *adapter = hw->back;
652 s32 ret_val;
653 u16 phy_data;
654
655 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
656 hw->media_type == MEDIA_TYPE_1000M_FULL)
657 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
658 else {
659 switch (hw->media_type) {
660 case MEDIA_TYPE_100M_FULL:
661 phy_data =
662 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
663 MII_CR_RESET;
664 break;
665 case MEDIA_TYPE_100M_HALF:
666 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
667 break;
668 case MEDIA_TYPE_10M_FULL:
669 phy_data =
670 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
671 break;
672 default:
673 /* MEDIA_TYPE_10M_HALF: */
674 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
675 break;
676 }
677 }
678
679 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
680 if (ret_val) {
681 u32 val;
682 int i;
683 /* pcie serdes link may be down! */
684 if (netif_msg_hw(adapter))
685 dev_dbg(&pdev->dev, "pcie phy link down\n");
686
687 for (i = 0; i < 25; i++) {
688 msleep(1);
689 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
690 if (!(val & (MDIO_START | MDIO_BUSY)))
691 break;
692 }
693
694 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
695 if (netif_msg_hw(adapter))
696 dev_warn(&pdev->dev,
697 "pcie link down at least 25ms\n");
698 return ret_val;
699 }
700 }
701 return 0;
702 }
703
704 /*
705 * Configures PHY autoneg and flow control advertisement settings
706 * hw - Struct containing variables accessed by shared code
707 */
708 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
709 {
710 s32 ret_val;
711 s16 mii_autoneg_adv_reg;
712 s16 mii_1000t_ctrl_reg;
713
714 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
715 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
716
717 /* Read the MII 1000Base-T Control Register (Address 9). */
718 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
719
720 /*
721 * First we clear all the 10/100 mb speed bits in the Auto-Neg
722 * Advertisement Register (Address 4) and the 1000 mb speed bits in
723 * the 1000Base-T Control Register (Address 9).
724 */
725 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
726 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
727
728 /*
729 * Need to parse media_type and set up
730 * the appropriate PHY registers.
731 */
732 switch (hw->media_type) {
733 case MEDIA_TYPE_AUTO_SENSOR:
734 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
735 MII_AR_10T_FD_CAPS |
736 MII_AR_100TX_HD_CAPS |
737 MII_AR_100TX_FD_CAPS);
738 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
739 break;
740
741 case MEDIA_TYPE_1000M_FULL:
742 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
743 break;
744
745 case MEDIA_TYPE_100M_FULL:
746 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
747 break;
748
749 case MEDIA_TYPE_100M_HALF:
750 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
751 break;
752
753 case MEDIA_TYPE_10M_FULL:
754 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
755 break;
756
757 default:
758 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
759 break;
760 }
761
762 /* flow control fixed to enable all */
763 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
764
765 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
766 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
767
768 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
769 if (ret_val)
770 return ret_val;
771
772 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
773 if (ret_val)
774 return ret_val;
775
776 return 0;
777 }
778
779 /*
780 * Configures link settings.
781 * hw - Struct containing variables accessed by shared code
782 * Assumes the hardware has previously been reset and the
783 * transmitter and receiver are not enabled.
784 */
785 static s32 atl1_setup_link(struct atl1_hw *hw)
786 {
787 struct pci_dev *pdev = hw->back->pdev;
788 struct atl1_adapter *adapter = hw->back;
789 s32 ret_val;
790
791 /*
792 * Options:
793 * PHY will advertise value(s) parsed from
794 * autoneg_advertised and fc
795 * no matter what autoneg is , We will not wait link result.
796 */
797 ret_val = atl1_phy_setup_autoneg_adv(hw);
798 if (ret_val) {
799 if (netif_msg_link(adapter))
800 dev_dbg(&pdev->dev,
801 "error setting up autonegotiation\n");
802 return ret_val;
803 }
804 /* SW.Reset , En-Auto-Neg if needed */
805 ret_val = atl1_phy_reset(hw);
806 if (ret_val) {
807 if (netif_msg_link(adapter))
808 dev_dbg(&pdev->dev, "error resetting phy\n");
809 return ret_val;
810 }
811 hw->phy_configured = true;
812 return ret_val;
813 }
814
815 static void atl1_init_flash_opcode(struct atl1_hw *hw)
816 {
817 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
818 /* Atmel */
819 hw->flash_vendor = 0;
820
821 /* Init OP table */
822 iowrite8(flash_table[hw->flash_vendor].cmd_program,
823 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
824 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
825 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
826 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
827 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
828 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
829 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
830 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
831 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
832 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
833 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
834 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
835 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
836 iowrite8(flash_table[hw->flash_vendor].cmd_read,
837 hw->hw_addr + REG_SPI_FLASH_OP_READ);
838 }
839
840 /*
841 * Performs basic configuration of the adapter.
842 * hw - Struct containing variables accessed by shared code
843 * Assumes that the controller has previously been reset and is in a
844 * post-reset uninitialized state. Initializes multicast table,
845 * and Calls routines to setup link
846 * Leaves the transmit and receive units disabled and uninitialized.
847 */
848 static s32 atl1_init_hw(struct atl1_hw *hw)
849 {
850 u32 ret_val = 0;
851
852 /* Zero out the Multicast HASH table */
853 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
854 /* clear the old settings from the multicast hash table */
855 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
856
857 atl1_init_flash_opcode(hw);
858
859 if (!hw->phy_configured) {
860 /* enable GPHY LinkChange Interrrupt */
861 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
862 if (ret_val)
863 return ret_val;
864 /* make PHY out of power-saving state */
865 ret_val = atl1_phy_leave_power_saving(hw);
866 if (ret_val)
867 return ret_val;
868 /* Call a subroutine to configure the link */
869 ret_val = atl1_setup_link(hw);
870 }
871 return ret_val;
872 }
873
874 /*
875 * Detects the current speed and duplex settings of the hardware.
876 * hw - Struct containing variables accessed by shared code
877 * speed - Speed of the connection
878 * duplex - Duplex setting of the connection
879 */
880 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
881 {
882 struct pci_dev *pdev = hw->back->pdev;
883 struct atl1_adapter *adapter = hw->back;
884 s32 ret_val;
885 u16 phy_data;
886
887 /* ; --- Read PHY Specific Status Register (17) */
888 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
889 if (ret_val)
890 return ret_val;
891
892 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
893 return ATLX_ERR_PHY_RES;
894
895 switch (phy_data & MII_ATLX_PSSR_SPEED) {
896 case MII_ATLX_PSSR_1000MBS:
897 *speed = SPEED_1000;
898 break;
899 case MII_ATLX_PSSR_100MBS:
900 *speed = SPEED_100;
901 break;
902 case MII_ATLX_PSSR_10MBS:
903 *speed = SPEED_10;
904 break;
905 default:
906 if (netif_msg_hw(adapter))
907 dev_dbg(&pdev->dev, "error getting speed\n");
908 return ATLX_ERR_PHY_SPEED;
909 break;
910 }
911 if (phy_data & MII_ATLX_PSSR_DPLX)
912 *duplex = FULL_DUPLEX;
913 else
914 *duplex = HALF_DUPLEX;
915
916 return 0;
917 }
918
919 static void atl1_set_mac_addr(struct atl1_hw *hw)
920 {
921 u32 value;
922 /*
923 * 00-0B-6A-F6-00-DC
924 * 0: 6AF600DC 1: 000B
925 * low dword
926 */
927 value = (((u32) hw->mac_addr[2]) << 24) |
928 (((u32) hw->mac_addr[3]) << 16) |
929 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
930 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
931 /* high dword */
932 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
933 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
934 }
935
936 /*
937 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
938 * @adapter: board private structure to initialize
939 *
940 * atl1_sw_init initializes the Adapter private data structure.
941 * Fields are initialized based on PCI device information and
942 * OS network device settings (MTU size).
943 */
944 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
945 {
946 struct atl1_hw *hw = &adapter->hw;
947 struct net_device *netdev = adapter->netdev;
948
949 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
950 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
951
952 adapter->wol = 0;
953 device_set_wakeup_enable(&adapter->pdev->dev, false);
954 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
955 adapter->ict = 50000; /* 100ms */
956 adapter->link_speed = SPEED_0; /* hardware init */
957 adapter->link_duplex = FULL_DUPLEX;
958
959 hw->phy_configured = false;
960 hw->preamble_len = 7;
961 hw->ipgt = 0x60;
962 hw->min_ifg = 0x50;
963 hw->ipgr1 = 0x40;
964 hw->ipgr2 = 0x60;
965 hw->max_retry = 0xf;
966 hw->lcol = 0x37;
967 hw->jam_ipg = 7;
968 hw->rfd_burst = 8;
969 hw->rrd_burst = 8;
970 hw->rfd_fetch_gap = 1;
971 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
972 hw->rx_jumbo_lkah = 1;
973 hw->rrd_ret_timer = 16;
974 hw->tpd_burst = 4;
975 hw->tpd_fetch_th = 16;
976 hw->txf_burst = 0x100;
977 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
978 hw->tpd_fetch_gap = 1;
979 hw->rcb_value = atl1_rcb_64;
980 hw->dma_ord = atl1_dma_ord_enh;
981 hw->dmar_block = atl1_dma_req_256;
982 hw->dmaw_block = atl1_dma_req_256;
983 hw->cmb_rrd = 4;
984 hw->cmb_tpd = 4;
985 hw->cmb_rx_timer = 1; /* about 2us */
986 hw->cmb_tx_timer = 1; /* about 2us */
987 hw->smb_timer = 100000; /* about 200ms */
988
989 spin_lock_init(&adapter->lock);
990 spin_lock_init(&adapter->mb_lock);
991
992 return 0;
993 }
994
995 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
996 {
997 struct atl1_adapter *adapter = netdev_priv(netdev);
998 u16 result;
999
1000 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1001
1002 return result;
1003 }
1004
1005 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1006 int val)
1007 {
1008 struct atl1_adapter *adapter = netdev_priv(netdev);
1009
1010 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1011 }
1012
1013 /*
1014 * atl1_mii_ioctl -
1015 * @netdev:
1016 * @ifreq:
1017 * @cmd:
1018 */
1019 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1020 {
1021 struct atl1_adapter *adapter = netdev_priv(netdev);
1022 unsigned long flags;
1023 int retval;
1024
1025 if (!netif_running(netdev))
1026 return -EINVAL;
1027
1028 spin_lock_irqsave(&adapter->lock, flags);
1029 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1030 spin_unlock_irqrestore(&adapter->lock, flags);
1031
1032 return retval;
1033 }
1034
1035 /*
1036 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1037 * @adapter: board private structure
1038 *
1039 * Return 0 on success, negative on failure
1040 */
1041 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1042 {
1043 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1044 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1045 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1046 struct atl1_ring_header *ring_header = &adapter->ring_header;
1047 struct pci_dev *pdev = adapter->pdev;
1048 int size;
1049 u8 offset = 0;
1050
1051 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1052 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1053 if (unlikely(!tpd_ring->buffer_info)) {
1054 if (netif_msg_drv(adapter))
1055 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1056 size);
1057 goto err_nomem;
1058 }
1059 rfd_ring->buffer_info =
1060 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1061
1062 /*
1063 * real ring DMA buffer
1064 * each ring/block may need up to 8 bytes for alignment, hence the
1065 * additional 40 bytes tacked onto the end.
1066 */
1067 ring_header->size = size =
1068 sizeof(struct tx_packet_desc) * tpd_ring->count
1069 + sizeof(struct rx_free_desc) * rfd_ring->count
1070 + sizeof(struct rx_return_desc) * rrd_ring->count
1071 + sizeof(struct coals_msg_block)
1072 + sizeof(struct stats_msg_block)
1073 + 40;
1074
1075 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1076 &ring_header->dma);
1077 if (unlikely(!ring_header->desc)) {
1078 if (netif_msg_drv(adapter))
1079 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1080 goto err_nomem;
1081 }
1082
1083 memset(ring_header->desc, 0, ring_header->size);
1084
1085 /* init TPD ring */
1086 tpd_ring->dma = ring_header->dma;
1087 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1088 tpd_ring->dma += offset;
1089 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1090 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1091
1092 /* init RFD ring */
1093 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1094 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1095 rfd_ring->dma += offset;
1096 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1097 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1098
1099
1100 /* init RRD ring */
1101 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1102 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1103 rrd_ring->dma += offset;
1104 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1105 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1106
1107
1108 /* init CMB */
1109 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1110 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1111 adapter->cmb.dma += offset;
1112 adapter->cmb.cmb = (struct coals_msg_block *)
1113 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1114
1115 /* init SMB */
1116 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1117 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1118 adapter->smb.dma += offset;
1119 adapter->smb.smb = (struct stats_msg_block *)
1120 ((u8 *) adapter->cmb.cmb +
1121 (sizeof(struct coals_msg_block) + offset));
1122
1123 return 0;
1124
1125 err_nomem:
1126 kfree(tpd_ring->buffer_info);
1127 return -ENOMEM;
1128 }
1129
1130 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1131 {
1132 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1133 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1134 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1135
1136 atomic_set(&tpd_ring->next_to_use, 0);
1137 atomic_set(&tpd_ring->next_to_clean, 0);
1138
1139 rfd_ring->next_to_clean = 0;
1140 atomic_set(&rfd_ring->next_to_use, 0);
1141
1142 rrd_ring->next_to_use = 0;
1143 atomic_set(&rrd_ring->next_to_clean, 0);
1144 }
1145
1146 /*
1147 * atl1_clean_rx_ring - Free RFD Buffers
1148 * @adapter: board private structure
1149 */
1150 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1151 {
1152 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1153 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1154 struct atl1_buffer *buffer_info;
1155 struct pci_dev *pdev = adapter->pdev;
1156 unsigned long size;
1157 unsigned int i;
1158
1159 /* Free all the Rx ring sk_buffs */
1160 for (i = 0; i < rfd_ring->count; i++) {
1161 buffer_info = &rfd_ring->buffer_info[i];
1162 if (buffer_info->dma) {
1163 pci_unmap_page(pdev, buffer_info->dma,
1164 buffer_info->length, PCI_DMA_FROMDEVICE);
1165 buffer_info->dma = 0;
1166 }
1167 if (buffer_info->skb) {
1168 dev_kfree_skb(buffer_info->skb);
1169 buffer_info->skb = NULL;
1170 }
1171 }
1172
1173 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1174 memset(rfd_ring->buffer_info, 0, size);
1175
1176 /* Zero out the descriptor ring */
1177 memset(rfd_ring->desc, 0, rfd_ring->size);
1178
1179 rfd_ring->next_to_clean = 0;
1180 atomic_set(&rfd_ring->next_to_use, 0);
1181
1182 rrd_ring->next_to_use = 0;
1183 atomic_set(&rrd_ring->next_to_clean, 0);
1184 }
1185
1186 /*
1187 * atl1_clean_tx_ring - Free Tx Buffers
1188 * @adapter: board private structure
1189 */
1190 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1191 {
1192 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1193 struct atl1_buffer *buffer_info;
1194 struct pci_dev *pdev = adapter->pdev;
1195 unsigned long size;
1196 unsigned int i;
1197
1198 /* Free all the Tx ring sk_buffs */
1199 for (i = 0; i < tpd_ring->count; i++) {
1200 buffer_info = &tpd_ring->buffer_info[i];
1201 if (buffer_info->dma) {
1202 pci_unmap_page(pdev, buffer_info->dma,
1203 buffer_info->length, PCI_DMA_TODEVICE);
1204 buffer_info->dma = 0;
1205 }
1206 }
1207
1208 for (i = 0; i < tpd_ring->count; i++) {
1209 buffer_info = &tpd_ring->buffer_info[i];
1210 if (buffer_info->skb) {
1211 dev_kfree_skb_any(buffer_info->skb);
1212 buffer_info->skb = NULL;
1213 }
1214 }
1215
1216 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1217 memset(tpd_ring->buffer_info, 0, size);
1218
1219 /* Zero out the descriptor ring */
1220 memset(tpd_ring->desc, 0, tpd_ring->size);
1221
1222 atomic_set(&tpd_ring->next_to_use, 0);
1223 atomic_set(&tpd_ring->next_to_clean, 0);
1224 }
1225
1226 /*
1227 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1228 * @adapter: board private structure
1229 *
1230 * Free all transmit software resources
1231 */
1232 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1233 {
1234 struct pci_dev *pdev = adapter->pdev;
1235 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1236 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1237 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1238 struct atl1_ring_header *ring_header = &adapter->ring_header;
1239
1240 atl1_clean_tx_ring(adapter);
1241 atl1_clean_rx_ring(adapter);
1242
1243 kfree(tpd_ring->buffer_info);
1244 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1245 ring_header->dma);
1246
1247 tpd_ring->buffer_info = NULL;
1248 tpd_ring->desc = NULL;
1249 tpd_ring->dma = 0;
1250
1251 rfd_ring->buffer_info = NULL;
1252 rfd_ring->desc = NULL;
1253 rfd_ring->dma = 0;
1254
1255 rrd_ring->desc = NULL;
1256 rrd_ring->dma = 0;
1257
1258 adapter->cmb.dma = 0;
1259 adapter->cmb.cmb = NULL;
1260
1261 adapter->smb.dma = 0;
1262 adapter->smb.smb = NULL;
1263 }
1264
1265 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1266 {
1267 u32 value;
1268 struct atl1_hw *hw = &adapter->hw;
1269 struct net_device *netdev = adapter->netdev;
1270 /* Config MAC CTRL Register */
1271 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1272 /* duplex */
1273 if (FULL_DUPLEX == adapter->link_duplex)
1274 value |= MAC_CTRL_DUPLX;
1275 /* speed */
1276 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1277 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1278 MAC_CTRL_SPEED_SHIFT);
1279 /* flow control */
1280 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1281 /* PAD & CRC */
1282 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1283 /* preamble length */
1284 value |= (((u32) adapter->hw.preamble_len
1285 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1286 /* vlan */
1287 if (adapter->vlgrp)
1288 value |= MAC_CTRL_RMV_VLAN;
1289 /* rx checksum
1290 if (adapter->rx_csum)
1291 value |= MAC_CTRL_RX_CHKSUM_EN;
1292 */
1293 /* filter mode */
1294 value |= MAC_CTRL_BC_EN;
1295 if (netdev->flags & IFF_PROMISC)
1296 value |= MAC_CTRL_PROMIS_EN;
1297 else if (netdev->flags & IFF_ALLMULTI)
1298 value |= MAC_CTRL_MC_ALL_EN;
1299 /* value |= MAC_CTRL_LOOPBACK; */
1300 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1301 }
1302
1303 static u32 atl1_check_link(struct atl1_adapter *adapter)
1304 {
1305 struct atl1_hw *hw = &adapter->hw;
1306 struct net_device *netdev = adapter->netdev;
1307 u32 ret_val;
1308 u16 speed, duplex, phy_data;
1309 int reconfig = 0;
1310
1311 /* MII_BMSR must read twice */
1312 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1313 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1314 if (!(phy_data & BMSR_LSTATUS)) {
1315 /* link down */
1316 if (netif_carrier_ok(netdev)) {
1317 /* old link state: Up */
1318 if (netif_msg_link(adapter))
1319 dev_info(&adapter->pdev->dev, "link is down\n");
1320 adapter->link_speed = SPEED_0;
1321 netif_carrier_off(netdev);
1322 }
1323 return 0;
1324 }
1325
1326 /* Link Up */
1327 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1328 if (ret_val)
1329 return ret_val;
1330
1331 switch (hw->media_type) {
1332 case MEDIA_TYPE_1000M_FULL:
1333 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1334 reconfig = 1;
1335 break;
1336 case MEDIA_TYPE_100M_FULL:
1337 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1338 reconfig = 1;
1339 break;
1340 case MEDIA_TYPE_100M_HALF:
1341 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1342 reconfig = 1;
1343 break;
1344 case MEDIA_TYPE_10M_FULL:
1345 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1346 reconfig = 1;
1347 break;
1348 case MEDIA_TYPE_10M_HALF:
1349 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1350 reconfig = 1;
1351 break;
1352 }
1353
1354 /* link result is our setting */
1355 if (!reconfig) {
1356 if (adapter->link_speed != speed ||
1357 adapter->link_duplex != duplex) {
1358 adapter->link_speed = speed;
1359 adapter->link_duplex = duplex;
1360 atl1_setup_mac_ctrl(adapter);
1361 if (netif_msg_link(adapter))
1362 dev_info(&adapter->pdev->dev,
1363 "%s link is up %d Mbps %s\n",
1364 netdev->name, adapter->link_speed,
1365 adapter->link_duplex == FULL_DUPLEX ?
1366 "full duplex" : "half duplex");
1367 }
1368 if (!netif_carrier_ok(netdev)) {
1369 /* Link down -> Up */
1370 netif_carrier_on(netdev);
1371 }
1372 return 0;
1373 }
1374
1375 /* change original link status */
1376 if (netif_carrier_ok(netdev)) {
1377 adapter->link_speed = SPEED_0;
1378 netif_carrier_off(netdev);
1379 netif_stop_queue(netdev);
1380 }
1381
1382 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1383 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1384 switch (hw->media_type) {
1385 case MEDIA_TYPE_100M_FULL:
1386 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1387 MII_CR_RESET;
1388 break;
1389 case MEDIA_TYPE_100M_HALF:
1390 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1391 break;
1392 case MEDIA_TYPE_10M_FULL:
1393 phy_data =
1394 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1395 break;
1396 default:
1397 /* MEDIA_TYPE_10M_HALF: */
1398 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1399 break;
1400 }
1401 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1402 return 0;
1403 }
1404
1405 /* auto-neg, insert timer to re-config phy */
1406 if (!adapter->phy_timer_pending) {
1407 adapter->phy_timer_pending = true;
1408 mod_timer(&adapter->phy_config_timer,
1409 round_jiffies(jiffies + 3 * HZ));
1410 }
1411
1412 return 0;
1413 }
1414
1415 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1416 {
1417 u32 hi, lo, value;
1418
1419 /* RFD Flow Control */
1420 value = adapter->rfd_ring.count;
1421 hi = value / 16;
1422 if (hi < 2)
1423 hi = 2;
1424 lo = value * 7 / 8;
1425
1426 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1427 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1428 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1429
1430 /* RRD Flow Control */
1431 value = adapter->rrd_ring.count;
1432 lo = value / 16;
1433 hi = value * 7 / 8;
1434 if (lo < 2)
1435 lo = 2;
1436 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1437 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1438 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1439 }
1440
1441 static void set_flow_ctrl_new(struct atl1_hw *hw)
1442 {
1443 u32 hi, lo, value;
1444
1445 /* RXF Flow Control */
1446 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1447 lo = value / 16;
1448 if (lo < 192)
1449 lo = 192;
1450 hi = value * 7 / 8;
1451 if (hi < lo)
1452 hi = lo + 16;
1453 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1454 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1455 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1456
1457 /* RRD Flow Control */
1458 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1459 lo = value / 8;
1460 hi = value * 7 / 8;
1461 if (lo < 2)
1462 lo = 2;
1463 if (hi < lo)
1464 hi = lo + 3;
1465 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1466 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1467 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1468 }
1469
1470 /*
1471 * atl1_configure - Configure Transmit&Receive Unit after Reset
1472 * @adapter: board private structure
1473 *
1474 * Configure the Tx /Rx unit of the MAC after a reset.
1475 */
1476 static u32 atl1_configure(struct atl1_adapter *adapter)
1477 {
1478 struct atl1_hw *hw = &adapter->hw;
1479 u32 value;
1480
1481 /* clear interrupt status */
1482 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1483
1484 /* set MAC Address */
1485 value = (((u32) hw->mac_addr[2]) << 24) |
1486 (((u32) hw->mac_addr[3]) << 16) |
1487 (((u32) hw->mac_addr[4]) << 8) |
1488 (((u32) hw->mac_addr[5]));
1489 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1490 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1491 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1492
1493 /* tx / rx ring */
1494
1495 /* HI base address */
1496 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1497 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1498 /* LO base address */
1499 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1500 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1501 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1502 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1503 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1504 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1505 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1506 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1507 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1508 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1509
1510 /* element count */
1511 value = adapter->rrd_ring.count;
1512 value <<= 16;
1513 value += adapter->rfd_ring.count;
1514 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1515 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1516 REG_DESC_TPD_RING_SIZE);
1517
1518 /* Load Ptr */
1519 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1520
1521 /* config Mailbox */
1522 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1523 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1524 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1525 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1526 ((atomic_read(&adapter->rfd_ring.next_to_use)
1527 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1528 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1529
1530 /* config IPG/IFG */
1531 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1532 << MAC_IPG_IFG_IPGT_SHIFT) |
1533 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1534 << MAC_IPG_IFG_MIFG_SHIFT) |
1535 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1536 << MAC_IPG_IFG_IPGR1_SHIFT) |
1537 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1538 << MAC_IPG_IFG_IPGR2_SHIFT);
1539 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1540
1541 /* config Half-Duplex Control */
1542 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1543 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1544 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1545 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1546 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1547 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1548 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1549 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1550
1551 /* set Interrupt Moderator Timer */
1552 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1553 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1554
1555 /* set Interrupt Clear Timer */
1556 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1557
1558 /* set max frame size hw will accept */
1559 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1560
1561 /* jumbo size & rrd retirement timer */
1562 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1563 << RXQ_JMBOSZ_TH_SHIFT) |
1564 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1565 << RXQ_JMBO_LKAH_SHIFT) |
1566 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1567 << RXQ_RRD_TIMER_SHIFT);
1568 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1569
1570 /* Flow Control */
1571 switch (hw->dev_rev) {
1572 case 0x8001:
1573 case 0x9001:
1574 case 0x9002:
1575 case 0x9003:
1576 set_flow_ctrl_old(adapter);
1577 break;
1578 default:
1579 set_flow_ctrl_new(hw);
1580 break;
1581 }
1582
1583 /* config TXQ */
1584 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1585 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1586 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1587 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1588 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1589 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1590 TXQ_CTRL_EN;
1591 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1592
1593 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1594 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1595 << TX_JUMBO_TASK_TH_SHIFT) |
1596 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1597 << TX_TPD_MIN_IPG_SHIFT);
1598 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1599
1600 /* config RXQ */
1601 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1602 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1603 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1604 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1605 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1606 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1607 RXQ_CTRL_EN;
1608 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1609
1610 /* config DMA Engine */
1611 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1612 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1613 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1614 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1615 DMA_CTRL_DMAW_EN;
1616 value |= (u32) hw->dma_ord;
1617 if (atl1_rcb_128 == hw->rcb_value)
1618 value |= DMA_CTRL_RCB_VALUE;
1619 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1620
1621 /* config CMB / SMB */
1622 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1623 hw->cmb_tpd : adapter->tpd_ring.count;
1624 value <<= 16;
1625 value |= hw->cmb_rrd;
1626 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1627 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1628 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1629 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1630
1631 /* --- enable CMB / SMB */
1632 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1633 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1634
1635 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1636 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1637 value = 1; /* config failed */
1638 else
1639 value = 0;
1640
1641 /* clear all interrupt status */
1642 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1643 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1644 return value;
1645 }
1646
1647 /*
1648 * atl1_pcie_patch - Patch for PCIE module
1649 */
1650 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1651 {
1652 u32 value;
1653
1654 /* much vendor magic here */
1655 value = 0x6500;
1656 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1657 /* pcie flow control mode change */
1658 value = ioread32(adapter->hw.hw_addr + 0x1008);
1659 value |= 0x8000;
1660 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1661 }
1662
1663 /*
1664 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1665 * on PCI Command register is disable.
1666 * The function enable this bit.
1667 * Brackett, 2006/03/15
1668 */
1669 static void atl1_via_workaround(struct atl1_adapter *adapter)
1670 {
1671 unsigned long value;
1672
1673 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1674 if (value & PCI_COMMAND_INTX_DISABLE)
1675 value &= ~PCI_COMMAND_INTX_DISABLE;
1676 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1677 }
1678
1679 static void atl1_inc_smb(struct atl1_adapter *adapter)
1680 {
1681 struct net_device *netdev = adapter->netdev;
1682 struct stats_msg_block *smb = adapter->smb.smb;
1683
1684 /* Fill out the OS statistics structure */
1685 adapter->soft_stats.rx_packets += smb->rx_ok;
1686 adapter->soft_stats.tx_packets += smb->tx_ok;
1687 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1688 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1689 adapter->soft_stats.multicast += smb->rx_mcast;
1690 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1691 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1692
1693 /* Rx Errors */
1694 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1695 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1696 smb->rx_rrd_ov + smb->rx_align_err);
1697 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1698 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1699 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1700 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1701 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1702 smb->rx_rxf_ov);
1703
1704 adapter->soft_stats.rx_pause += smb->rx_pause;
1705 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1706 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1707
1708 /* Tx Errors */
1709 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1710 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1711 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1712 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1713 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1714
1715 adapter->soft_stats.excecol += smb->tx_abort_col;
1716 adapter->soft_stats.deffer += smb->tx_defer;
1717 adapter->soft_stats.scc += smb->tx_1_col;
1718 adapter->soft_stats.mcc += smb->tx_2_col;
1719 adapter->soft_stats.latecol += smb->tx_late_col;
1720 adapter->soft_stats.tx_underun += smb->tx_underrun;
1721 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1722 adapter->soft_stats.tx_pause += smb->tx_pause;
1723
1724 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1725 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1726 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1727 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1728 netdev->stats.multicast = adapter->soft_stats.multicast;
1729 netdev->stats.collisions = adapter->soft_stats.collisions;
1730 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1731 netdev->stats.rx_over_errors =
1732 adapter->soft_stats.rx_missed_errors;
1733 netdev->stats.rx_length_errors =
1734 adapter->soft_stats.rx_length_errors;
1735 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1736 netdev->stats.rx_frame_errors =
1737 adapter->soft_stats.rx_frame_errors;
1738 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1739 netdev->stats.rx_missed_errors =
1740 adapter->soft_stats.rx_missed_errors;
1741 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1742 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1743 netdev->stats.tx_aborted_errors =
1744 adapter->soft_stats.tx_aborted_errors;
1745 netdev->stats.tx_window_errors =
1746 adapter->soft_stats.tx_window_errors;
1747 netdev->stats.tx_carrier_errors =
1748 adapter->soft_stats.tx_carrier_errors;
1749 }
1750
1751 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1752 {
1753 unsigned long flags;
1754 u32 tpd_next_to_use;
1755 u32 rfd_next_to_use;
1756 u32 rrd_next_to_clean;
1757 u32 value;
1758
1759 spin_lock_irqsave(&adapter->mb_lock, flags);
1760
1761 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1762 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1763 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1764
1765 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1766 MB_RFD_PROD_INDX_SHIFT) |
1767 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1768 MB_RRD_CONS_INDX_SHIFT) |
1769 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1770 MB_TPD_PROD_INDX_SHIFT);
1771 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1772
1773 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1774 }
1775
1776 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1777 struct rx_return_desc *rrd, u16 offset)
1778 {
1779 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1780
1781 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1782 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1783 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1784 rfd_ring->next_to_clean = 0;
1785 }
1786 }
1787 }
1788
1789 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1790 struct rx_return_desc *rrd)
1791 {
1792 u16 num_buf;
1793
1794 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1795 adapter->rx_buffer_len;
1796 if (rrd->num_buf == num_buf)
1797 /* clean alloc flag for bad rrd */
1798 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1799 }
1800
1801 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1802 struct rx_return_desc *rrd, struct sk_buff *skb)
1803 {
1804 struct pci_dev *pdev = adapter->pdev;
1805
1806 /*
1807 * The L1 hardware contains a bug that erroneously sets the
1808 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1809 * fragmented IP packet is received, even though the packet
1810 * is perfectly valid and its checksum is correct. There's
1811 * no way to distinguish between one of these good packets
1812 * and a packet that actually contains a TCP/UDP checksum
1813 * error, so all we can do is allow it to be handed up to
1814 * the higher layers and let it be sorted out there.
1815 */
1816
1817 skb_checksum_none_assert(skb);
1818
1819 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1820 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1821 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1822 adapter->hw_csum_err++;
1823 if (netif_msg_rx_err(adapter))
1824 dev_printk(KERN_DEBUG, &pdev->dev,
1825 "rx checksum error\n");
1826 return;
1827 }
1828 }
1829
1830 /* not IPv4 */
1831 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1832 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1833 return;
1834
1835 /* IPv4 packet */
1836 if (likely(!(rrd->err_flg &
1837 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1838 skb->ip_summed = CHECKSUM_UNNECESSARY;
1839 adapter->hw_csum_good++;
1840 return;
1841 }
1842 }
1843
1844 /*
1845 * atl1_alloc_rx_buffers - Replace used receive buffers
1846 * @adapter: address of board private structure
1847 */
1848 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1849 {
1850 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1851 struct pci_dev *pdev = adapter->pdev;
1852 struct page *page;
1853 unsigned long offset;
1854 struct atl1_buffer *buffer_info, *next_info;
1855 struct sk_buff *skb;
1856 u16 num_alloc = 0;
1857 u16 rfd_next_to_use, next_next;
1858 struct rx_free_desc *rfd_desc;
1859
1860 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1861 if (++next_next == rfd_ring->count)
1862 next_next = 0;
1863 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1864 next_info = &rfd_ring->buffer_info[next_next];
1865
1866 while (!buffer_info->alloced && !next_info->alloced) {
1867 if (buffer_info->skb) {
1868 buffer_info->alloced = 1;
1869 goto next;
1870 }
1871
1872 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1873
1874 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1875 adapter->rx_buffer_len);
1876 if (unlikely(!skb)) {
1877 /* Better luck next round */
1878 adapter->netdev->stats.rx_dropped++;
1879 break;
1880 }
1881
1882 buffer_info->alloced = 1;
1883 buffer_info->skb = skb;
1884 buffer_info->length = (u16) adapter->rx_buffer_len;
1885 page = virt_to_page(skb->data);
1886 offset = (unsigned long)skb->data & ~PAGE_MASK;
1887 buffer_info->dma = pci_map_page(pdev, page, offset,
1888 adapter->rx_buffer_len,
1889 PCI_DMA_FROMDEVICE);
1890 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1891 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1892 rfd_desc->coalese = 0;
1893
1894 next:
1895 rfd_next_to_use = next_next;
1896 if (unlikely(++next_next == rfd_ring->count))
1897 next_next = 0;
1898
1899 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1900 next_info = &rfd_ring->buffer_info[next_next];
1901 num_alloc++;
1902 }
1903
1904 if (num_alloc) {
1905 /*
1906 * Force memory writes to complete before letting h/w
1907 * know there are new descriptors to fetch. (Only
1908 * applicable for weak-ordered memory model archs,
1909 * such as IA-64).
1910 */
1911 wmb();
1912 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1913 }
1914 return num_alloc;
1915 }
1916
1917 static void atl1_intr_rx(struct atl1_adapter *adapter)
1918 {
1919 int i, count;
1920 u16 length;
1921 u16 rrd_next_to_clean;
1922 u32 value;
1923 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1924 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1925 struct atl1_buffer *buffer_info;
1926 struct rx_return_desc *rrd;
1927 struct sk_buff *skb;
1928
1929 count = 0;
1930
1931 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1932
1933 while (1) {
1934 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1935 i = 1;
1936 if (likely(rrd->xsz.valid)) { /* packet valid */
1937 chk_rrd:
1938 /* check rrd status */
1939 if (likely(rrd->num_buf == 1))
1940 goto rrd_ok;
1941 else if (netif_msg_rx_err(adapter)) {
1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1943 "unexpected RRD buffer count\n");
1944 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1945 "rx_buf_len = %d\n",
1946 adapter->rx_buffer_len);
1947 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1948 "RRD num_buf = %d\n",
1949 rrd->num_buf);
1950 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1951 "RRD pkt_len = %d\n",
1952 rrd->xsz.xsum_sz.pkt_size);
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "RRD pkt_flg = 0x%08X\n",
1955 rrd->pkt_flg);
1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1957 "RRD err_flg = 0x%08X\n",
1958 rrd->err_flg);
1959 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1960 "RRD vlan_tag = 0x%08X\n",
1961 rrd->vlan_tag);
1962 }
1963
1964 /* rrd seems to be bad */
1965 if (unlikely(i-- > 0)) {
1966 /* rrd may not be DMAed completely */
1967 udelay(1);
1968 goto chk_rrd;
1969 }
1970 /* bad rrd */
1971 if (netif_msg_rx_err(adapter))
1972 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1973 "bad RRD\n");
1974 /* see if update RFD index */
1975 if (rrd->num_buf > 1)
1976 atl1_update_rfd_index(adapter, rrd);
1977
1978 /* update rrd */
1979 rrd->xsz.valid = 0;
1980 if (++rrd_next_to_clean == rrd_ring->count)
1981 rrd_next_to_clean = 0;
1982 count++;
1983 continue;
1984 } else { /* current rrd still not be updated */
1985
1986 break;
1987 }
1988 rrd_ok:
1989 /* clean alloc flag for bad rrd */
1990 atl1_clean_alloc_flag(adapter, rrd, 0);
1991
1992 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1993 if (++rfd_ring->next_to_clean == rfd_ring->count)
1994 rfd_ring->next_to_clean = 0;
1995
1996 /* update rrd next to clean */
1997 if (++rrd_next_to_clean == rrd_ring->count)
1998 rrd_next_to_clean = 0;
1999 count++;
2000
2001 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2002 if (!(rrd->err_flg &
2003 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2004 | ERR_FLAG_LEN))) {
2005 /* packet error, don't need upstream */
2006 buffer_info->alloced = 0;
2007 rrd->xsz.valid = 0;
2008 continue;
2009 }
2010 }
2011
2012 /* Good Receive */
2013 pci_unmap_page(adapter->pdev, buffer_info->dma,
2014 buffer_info->length, PCI_DMA_FROMDEVICE);
2015 buffer_info->dma = 0;
2016 skb = buffer_info->skb;
2017 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2018
2019 skb_put(skb, length - ETH_FCS_LEN);
2020
2021 /* Receive Checksum Offload */
2022 atl1_rx_checksum(adapter, rrd, skb);
2023 skb->protocol = eth_type_trans(skb, adapter->netdev);
2024
2025 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2026 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2027 ((rrd->vlan_tag & 7) << 13) |
2028 ((rrd->vlan_tag & 8) << 9);
2029 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2030 } else
2031 netif_rx(skb);
2032
2033 /* let protocol layer free skb */
2034 buffer_info->skb = NULL;
2035 buffer_info->alloced = 0;
2036 rrd->xsz.valid = 0;
2037 }
2038
2039 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2040
2041 atl1_alloc_rx_buffers(adapter);
2042
2043 /* update mailbox ? */
2044 if (count) {
2045 u32 tpd_next_to_use;
2046 u32 rfd_next_to_use;
2047
2048 spin_lock(&adapter->mb_lock);
2049
2050 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2051 rfd_next_to_use =
2052 atomic_read(&adapter->rfd_ring.next_to_use);
2053 rrd_next_to_clean =
2054 atomic_read(&adapter->rrd_ring.next_to_clean);
2055 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2056 MB_RFD_PROD_INDX_SHIFT) |
2057 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2058 MB_RRD_CONS_INDX_SHIFT) |
2059 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2060 MB_TPD_PROD_INDX_SHIFT);
2061 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2062 spin_unlock(&adapter->mb_lock);
2063 }
2064 }
2065
2066 static void atl1_intr_tx(struct atl1_adapter *adapter)
2067 {
2068 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2069 struct atl1_buffer *buffer_info;
2070 u16 sw_tpd_next_to_clean;
2071 u16 cmb_tpd_next_to_clean;
2072
2073 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2074 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2075
2076 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2077 struct tx_packet_desc *tpd;
2078
2079 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2080 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2081 if (buffer_info->dma) {
2082 pci_unmap_page(adapter->pdev, buffer_info->dma,
2083 buffer_info->length, PCI_DMA_TODEVICE);
2084 buffer_info->dma = 0;
2085 }
2086
2087 if (buffer_info->skb) {
2088 dev_kfree_skb_irq(buffer_info->skb);
2089 buffer_info->skb = NULL;
2090 }
2091
2092 if (++sw_tpd_next_to_clean == tpd_ring->count)
2093 sw_tpd_next_to_clean = 0;
2094 }
2095 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2096
2097 if (netif_queue_stopped(adapter->netdev) &&
2098 netif_carrier_ok(adapter->netdev))
2099 netif_wake_queue(adapter->netdev);
2100 }
2101
2102 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2103 {
2104 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2105 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2106 return (next_to_clean > next_to_use) ?
2107 next_to_clean - next_to_use - 1 :
2108 tpd_ring->count + next_to_clean - next_to_use - 1;
2109 }
2110
2111 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2112 struct tx_packet_desc *ptpd)
2113 {
2114 u8 hdr_len, ip_off;
2115 u32 real_len;
2116 int err;
2117
2118 if (skb_shinfo(skb)->gso_size) {
2119 if (skb_header_cloned(skb)) {
2120 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2121 if (unlikely(err))
2122 return -1;
2123 }
2124
2125 if (skb->protocol == htons(ETH_P_IP)) {
2126 struct iphdr *iph = ip_hdr(skb);
2127
2128 real_len = (((unsigned char *)iph - skb->data) +
2129 ntohs(iph->tot_len));
2130 if (real_len < skb->len)
2131 pskb_trim(skb, real_len);
2132 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2133 if (skb->len == hdr_len) {
2134 iph->check = 0;
2135 tcp_hdr(skb)->check =
2136 ~csum_tcpudp_magic(iph->saddr,
2137 iph->daddr, tcp_hdrlen(skb),
2138 IPPROTO_TCP, 0);
2139 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2140 TPD_IPHL_SHIFT;
2141 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2142 TPD_TCPHDRLEN_MASK) <<
2143 TPD_TCPHDRLEN_SHIFT;
2144 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2145 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2146 return 1;
2147 }
2148
2149 iph->check = 0;
2150 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2151 iph->daddr, 0, IPPROTO_TCP, 0);
2152 ip_off = (unsigned char *)iph -
2153 (unsigned char *) skb_network_header(skb);
2154 if (ip_off == 8) /* 802.3-SNAP frame */
2155 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2156 else if (ip_off != 0)
2157 return -2;
2158
2159 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2160 TPD_IPHL_SHIFT;
2161 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2162 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2163 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2164 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2165 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2166 return 3;
2167 }
2168 }
2169 return false;
2170 }
2171
2172 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2173 struct tx_packet_desc *ptpd)
2174 {
2175 u8 css, cso;
2176
2177 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2178 css = skb_checksum_start_offset(skb);
2179 cso = css + (u8) skb->csum_offset;
2180 if (unlikely(css & 0x1)) {
2181 /* L1 hardware requires an even number here */
2182 if (netif_msg_tx_err(adapter))
2183 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2184 "payload offset not an even number\n");
2185 return -1;
2186 }
2187 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2188 TPD_PLOADOFFSET_SHIFT;
2189 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2190 TPD_CCSUMOFFSET_SHIFT;
2191 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2192 return true;
2193 }
2194 return 0;
2195 }
2196
2197 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2198 struct tx_packet_desc *ptpd)
2199 {
2200 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2201 struct atl1_buffer *buffer_info;
2202 u16 buf_len = skb->len;
2203 struct page *page;
2204 unsigned long offset;
2205 unsigned int nr_frags;
2206 unsigned int f;
2207 int retval;
2208 u16 next_to_use;
2209 u16 data_len;
2210 u8 hdr_len;
2211
2212 buf_len -= skb->data_len;
2213 nr_frags = skb_shinfo(skb)->nr_frags;
2214 next_to_use = atomic_read(&tpd_ring->next_to_use);
2215 buffer_info = &tpd_ring->buffer_info[next_to_use];
2216 BUG_ON(buffer_info->skb);
2217 /* put skb in last TPD */
2218 buffer_info->skb = NULL;
2219
2220 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2221 if (retval) {
2222 /* TSO */
2223 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2224 buffer_info->length = hdr_len;
2225 page = virt_to_page(skb->data);
2226 offset = (unsigned long)skb->data & ~PAGE_MASK;
2227 buffer_info->dma = pci_map_page(adapter->pdev, page,
2228 offset, hdr_len,
2229 PCI_DMA_TODEVICE);
2230
2231 if (++next_to_use == tpd_ring->count)
2232 next_to_use = 0;
2233
2234 if (buf_len > hdr_len) {
2235 int i, nseg;
2236
2237 data_len = buf_len - hdr_len;
2238 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2239 ATL1_MAX_TX_BUF_LEN;
2240 for (i = 0; i < nseg; i++) {
2241 buffer_info =
2242 &tpd_ring->buffer_info[next_to_use];
2243 buffer_info->skb = NULL;
2244 buffer_info->length =
2245 (ATL1_MAX_TX_BUF_LEN >=
2246 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2247 data_len -= buffer_info->length;
2248 page = virt_to_page(skb->data +
2249 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2250 offset = (unsigned long)(skb->data +
2251 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2252 ~PAGE_MASK;
2253 buffer_info->dma = pci_map_page(adapter->pdev,
2254 page, offset, buffer_info->length,
2255 PCI_DMA_TODEVICE);
2256 if (++next_to_use == tpd_ring->count)
2257 next_to_use = 0;
2258 }
2259 }
2260 } else {
2261 /* not TSO */
2262 buffer_info->length = buf_len;
2263 page = virt_to_page(skb->data);
2264 offset = (unsigned long)skb->data & ~PAGE_MASK;
2265 buffer_info->dma = pci_map_page(adapter->pdev, page,
2266 offset, buf_len, PCI_DMA_TODEVICE);
2267 if (++next_to_use == tpd_ring->count)
2268 next_to_use = 0;
2269 }
2270
2271 for (f = 0; f < nr_frags; f++) {
2272 struct skb_frag_struct *frag;
2273 u16 i, nseg;
2274
2275 frag = &skb_shinfo(skb)->frags[f];
2276 buf_len = frag->size;
2277
2278 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2279 ATL1_MAX_TX_BUF_LEN;
2280 for (i = 0; i < nseg; i++) {
2281 buffer_info = &tpd_ring->buffer_info[next_to_use];
2282 BUG_ON(buffer_info->skb);
2283
2284 buffer_info->skb = NULL;
2285 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2286 ATL1_MAX_TX_BUF_LEN : buf_len;
2287 buf_len -= buffer_info->length;
2288 buffer_info->dma = pci_map_page(adapter->pdev,
2289 frag->page,
2290 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2291 buffer_info->length, PCI_DMA_TODEVICE);
2292
2293 if (++next_to_use == tpd_ring->count)
2294 next_to_use = 0;
2295 }
2296 }
2297
2298 /* last tpd's buffer-info */
2299 buffer_info->skb = skb;
2300 }
2301
2302 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2303 struct tx_packet_desc *ptpd)
2304 {
2305 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2306 struct atl1_buffer *buffer_info;
2307 struct tx_packet_desc *tpd;
2308 u16 j;
2309 u32 val;
2310 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2311
2312 for (j = 0; j < count; j++) {
2313 buffer_info = &tpd_ring->buffer_info[next_to_use];
2314 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2315 if (tpd != ptpd)
2316 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2317 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2318 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2319 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2320 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2321
2322 /*
2323 * if this is the first packet in a TSO chain, set
2324 * TPD_HDRFLAG, otherwise, clear it.
2325 */
2326 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2327 TPD_SEGMENT_EN_MASK;
2328 if (val) {
2329 if (!j)
2330 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2331 else
2332 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2333 }
2334
2335 if (j == (count - 1))
2336 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2337
2338 if (++next_to_use == tpd_ring->count)
2339 next_to_use = 0;
2340 }
2341 /*
2342 * Force memory writes to complete before letting h/w
2343 * know there are new descriptors to fetch. (Only
2344 * applicable for weak-ordered memory model archs,
2345 * such as IA-64).
2346 */
2347 wmb();
2348
2349 atomic_set(&tpd_ring->next_to_use, next_to_use);
2350 }
2351
2352 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2353 struct net_device *netdev)
2354 {
2355 struct atl1_adapter *adapter = netdev_priv(netdev);
2356 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2357 int len;
2358 int tso;
2359 int count = 1;
2360 int ret_val;
2361 struct tx_packet_desc *ptpd;
2362 u16 frag_size;
2363 u16 vlan_tag;
2364 unsigned int nr_frags = 0;
2365 unsigned int mss = 0;
2366 unsigned int f;
2367 unsigned int proto_hdr_len;
2368
2369 len = skb_headlen(skb);
2370
2371 if (unlikely(skb->len <= 0)) {
2372 dev_kfree_skb_any(skb);
2373 return NETDEV_TX_OK;
2374 }
2375
2376 nr_frags = skb_shinfo(skb)->nr_frags;
2377 for (f = 0; f < nr_frags; f++) {
2378 frag_size = skb_shinfo(skb)->frags[f].size;
2379 if (frag_size)
2380 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2381 ATL1_MAX_TX_BUF_LEN;
2382 }
2383
2384 mss = skb_shinfo(skb)->gso_size;
2385 if (mss) {
2386 if (skb->protocol == htons(ETH_P_IP)) {
2387 proto_hdr_len = (skb_transport_offset(skb) +
2388 tcp_hdrlen(skb));
2389 if (unlikely(proto_hdr_len > len)) {
2390 dev_kfree_skb_any(skb);
2391 return NETDEV_TX_OK;
2392 }
2393 /* need additional TPD ? */
2394 if (proto_hdr_len != len)
2395 count += (len - proto_hdr_len +
2396 ATL1_MAX_TX_BUF_LEN - 1) /
2397 ATL1_MAX_TX_BUF_LEN;
2398 }
2399 }
2400
2401 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2402 /* not enough descriptors */
2403 netif_stop_queue(netdev);
2404 if (netif_msg_tx_queued(adapter))
2405 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2406 "tx busy\n");
2407 return NETDEV_TX_BUSY;
2408 }
2409
2410 ptpd = ATL1_TPD_DESC(tpd_ring,
2411 (u16) atomic_read(&tpd_ring->next_to_use));
2412 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2413
2414 if (vlan_tx_tag_present(skb)) {
2415 vlan_tag = vlan_tx_tag_get(skb);
2416 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2417 ((vlan_tag >> 9) & 0x8);
2418 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2419 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2420 TPD_VLANTAG_SHIFT;
2421 }
2422
2423 tso = atl1_tso(adapter, skb, ptpd);
2424 if (tso < 0) {
2425 dev_kfree_skb_any(skb);
2426 return NETDEV_TX_OK;
2427 }
2428
2429 if (!tso) {
2430 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2431 if (ret_val < 0) {
2432 dev_kfree_skb_any(skb);
2433 return NETDEV_TX_OK;
2434 }
2435 }
2436
2437 atl1_tx_map(adapter, skb, ptpd);
2438 atl1_tx_queue(adapter, count, ptpd);
2439 atl1_update_mailbox(adapter);
2440 mmiowb();
2441 return NETDEV_TX_OK;
2442 }
2443
2444 /*
2445 * atl1_intr - Interrupt Handler
2446 * @irq: interrupt number
2447 * @data: pointer to a network interface device structure
2448 * @pt_regs: CPU registers structure
2449 */
2450 static irqreturn_t atl1_intr(int irq, void *data)
2451 {
2452 struct atl1_adapter *adapter = netdev_priv(data);
2453 u32 status;
2454 int max_ints = 10;
2455
2456 status = adapter->cmb.cmb->int_stats;
2457 if (!status)
2458 return IRQ_NONE;
2459
2460 do {
2461 /* clear CMB interrupt status at once */
2462 adapter->cmb.cmb->int_stats = 0;
2463
2464 if (status & ISR_GPHY) /* clear phy status */
2465 atlx_clear_phy_int(adapter);
2466
2467 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2468 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2469
2470 /* check if SMB intr */
2471 if (status & ISR_SMB)
2472 atl1_inc_smb(adapter);
2473
2474 /* check if PCIE PHY Link down */
2475 if (status & ISR_PHY_LINKDOWN) {
2476 if (netif_msg_intr(adapter))
2477 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2478 "pcie phy link down %x\n", status);
2479 if (netif_running(adapter->netdev)) { /* reset MAC */
2480 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2481 schedule_work(&adapter->pcie_dma_to_rst_task);
2482 return IRQ_HANDLED;
2483 }
2484 }
2485
2486 /* check if DMA read/write error ? */
2487 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2488 if (netif_msg_intr(adapter))
2489 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2490 "pcie DMA r/w error (status = 0x%x)\n",
2491 status);
2492 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2493 schedule_work(&adapter->pcie_dma_to_rst_task);
2494 return IRQ_HANDLED;
2495 }
2496
2497 /* link event */
2498 if (status & ISR_GPHY) {
2499 adapter->soft_stats.tx_carrier_errors++;
2500 atl1_check_for_link(adapter);
2501 }
2502
2503 /* transmit event */
2504 if (status & ISR_CMB_TX)
2505 atl1_intr_tx(adapter);
2506
2507 /* rx exception */
2508 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2509 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2510 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2511 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2512 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2513 ISR_HOST_RRD_OV))
2514 if (netif_msg_intr(adapter))
2515 dev_printk(KERN_DEBUG,
2516 &adapter->pdev->dev,
2517 "rx exception, ISR = 0x%x\n",
2518 status);
2519 atl1_intr_rx(adapter);
2520 }
2521
2522 if (--max_ints < 0)
2523 break;
2524
2525 } while ((status = adapter->cmb.cmb->int_stats));
2526
2527 /* re-enable Interrupt */
2528 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2529 return IRQ_HANDLED;
2530 }
2531
2532
2533 /*
2534 * atl1_phy_config - Timer Call-back
2535 * @data: pointer to netdev cast into an unsigned long
2536 */
2537 static void atl1_phy_config(unsigned long data)
2538 {
2539 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2540 struct atl1_hw *hw = &adapter->hw;
2541 unsigned long flags;
2542
2543 spin_lock_irqsave(&adapter->lock, flags);
2544 adapter->phy_timer_pending = false;
2545 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2546 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2547 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2548 spin_unlock_irqrestore(&adapter->lock, flags);
2549 }
2550
2551 /*
2552 * Orphaned vendor comment left intact here:
2553 * <vendor comment>
2554 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2555 * will assert. We do soft reset <0x1400=1> according
2556 * with the SPEC. BUT, it seemes that PCIE or DMA
2557 * state-machine will not be reset. DMAR_TO_INT will
2558 * assert again and again.
2559 * </vendor comment>
2560 */
2561
2562 static int atl1_reset(struct atl1_adapter *adapter)
2563 {
2564 int ret;
2565 ret = atl1_reset_hw(&adapter->hw);
2566 if (ret)
2567 return ret;
2568 return atl1_init_hw(&adapter->hw);
2569 }
2570
2571 static s32 atl1_up(struct atl1_adapter *adapter)
2572 {
2573 struct net_device *netdev = adapter->netdev;
2574 int err;
2575 int irq_flags = IRQF_SAMPLE_RANDOM;
2576
2577 /* hardware has been reset, we need to reload some things */
2578 atlx_set_multi(netdev);
2579 atl1_init_ring_ptrs(adapter);
2580 atlx_restore_vlan(adapter);
2581 err = atl1_alloc_rx_buffers(adapter);
2582 if (unlikely(!err))
2583 /* no RX BUFFER allocated */
2584 return -ENOMEM;
2585
2586 if (unlikely(atl1_configure(adapter))) {
2587 err = -EIO;
2588 goto err_up;
2589 }
2590
2591 err = pci_enable_msi(adapter->pdev);
2592 if (err) {
2593 if (netif_msg_ifup(adapter))
2594 dev_info(&adapter->pdev->dev,
2595 "Unable to enable MSI: %d\n", err);
2596 irq_flags |= IRQF_SHARED;
2597 }
2598
2599 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
2600 netdev->name, netdev);
2601 if (unlikely(err))
2602 goto err_up;
2603
2604 atlx_irq_enable(adapter);
2605 atl1_check_link(adapter);
2606 netif_start_queue(netdev);
2607 return 0;
2608
2609 err_up:
2610 pci_disable_msi(adapter->pdev);
2611 /* free rx_buffers */
2612 atl1_clean_rx_ring(adapter);
2613 return err;
2614 }
2615
2616 static void atl1_down(struct atl1_adapter *adapter)
2617 {
2618 struct net_device *netdev = adapter->netdev;
2619
2620 netif_stop_queue(netdev);
2621 del_timer_sync(&adapter->phy_config_timer);
2622 adapter->phy_timer_pending = false;
2623
2624 atlx_irq_disable(adapter);
2625 free_irq(adapter->pdev->irq, netdev);
2626 pci_disable_msi(adapter->pdev);
2627 atl1_reset_hw(&adapter->hw);
2628 adapter->cmb.cmb->int_stats = 0;
2629
2630 adapter->link_speed = SPEED_0;
2631 adapter->link_duplex = -1;
2632 netif_carrier_off(netdev);
2633
2634 atl1_clean_tx_ring(adapter);
2635 atl1_clean_rx_ring(adapter);
2636 }
2637
2638 static void atl1_tx_timeout_task(struct work_struct *work)
2639 {
2640 struct atl1_adapter *adapter =
2641 container_of(work, struct atl1_adapter, tx_timeout_task);
2642 struct net_device *netdev = adapter->netdev;
2643
2644 netif_device_detach(netdev);
2645 atl1_down(adapter);
2646 atl1_up(adapter);
2647 netif_device_attach(netdev);
2648 }
2649
2650 /*
2651 * atl1_change_mtu - Change the Maximum Transfer Unit
2652 * @netdev: network interface device structure
2653 * @new_mtu: new value for maximum frame size
2654 *
2655 * Returns 0 on success, negative on failure
2656 */
2657 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2658 {
2659 struct atl1_adapter *adapter = netdev_priv(netdev);
2660 int old_mtu = netdev->mtu;
2661 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2662
2663 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2664 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2665 if (netif_msg_link(adapter))
2666 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2667 return -EINVAL;
2668 }
2669
2670 adapter->hw.max_frame_size = max_frame;
2671 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2672 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2673 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2674
2675 netdev->mtu = new_mtu;
2676 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2677 atl1_down(adapter);
2678 atl1_up(adapter);
2679 }
2680
2681 return 0;
2682 }
2683
2684 /*
2685 * atl1_open - Called when a network interface is made active
2686 * @netdev: network interface device structure
2687 *
2688 * Returns 0 on success, negative value on failure
2689 *
2690 * The open entry point is called when a network interface is made
2691 * active by the system (IFF_UP). At this point all resources needed
2692 * for transmit and receive operations are allocated, the interrupt
2693 * handler is registered with the OS, the watchdog timer is started,
2694 * and the stack is notified that the interface is ready.
2695 */
2696 static int atl1_open(struct net_device *netdev)
2697 {
2698 struct atl1_adapter *adapter = netdev_priv(netdev);
2699 int err;
2700
2701 netif_carrier_off(netdev);
2702
2703 /* allocate transmit descriptors */
2704 err = atl1_setup_ring_resources(adapter);
2705 if (err)
2706 return err;
2707
2708 err = atl1_up(adapter);
2709 if (err)
2710 goto err_up;
2711
2712 return 0;
2713
2714 err_up:
2715 atl1_reset(adapter);
2716 return err;
2717 }
2718
2719 /*
2720 * atl1_close - Disables a network interface
2721 * @netdev: network interface device structure
2722 *
2723 * Returns 0, this is not allowed to fail
2724 *
2725 * The close entry point is called when an interface is de-activated
2726 * by the OS. The hardware is still under the drivers control, but
2727 * needs to be disabled. A global MAC reset is issued to stop the
2728 * hardware, and all transmit and receive resources are freed.
2729 */
2730 static int atl1_close(struct net_device *netdev)
2731 {
2732 struct atl1_adapter *adapter = netdev_priv(netdev);
2733 atl1_down(adapter);
2734 atl1_free_ring_resources(adapter);
2735 return 0;
2736 }
2737
2738 #ifdef CONFIG_PM
2739 static int atl1_suspend(struct device *dev)
2740 {
2741 struct pci_dev *pdev = to_pci_dev(dev);
2742 struct net_device *netdev = pci_get_drvdata(pdev);
2743 struct atl1_adapter *adapter = netdev_priv(netdev);
2744 struct atl1_hw *hw = &adapter->hw;
2745 u32 ctrl = 0;
2746 u32 wufc = adapter->wol;
2747 u32 val;
2748 u16 speed;
2749 u16 duplex;
2750
2751 netif_device_detach(netdev);
2752 if (netif_running(netdev))
2753 atl1_down(adapter);
2754
2755 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2756 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2757 val = ctrl & BMSR_LSTATUS;
2758 if (val)
2759 wufc &= ~ATLX_WUFC_LNKC;
2760 if (!wufc)
2761 goto disable_wol;
2762
2763 if (val) {
2764 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2765 if (val) {
2766 if (netif_msg_ifdown(adapter))
2767 dev_printk(KERN_DEBUG, &pdev->dev,
2768 "error getting speed/duplex\n");
2769 goto disable_wol;
2770 }
2771
2772 ctrl = 0;
2773
2774 /* enable magic packet WOL */
2775 if (wufc & ATLX_WUFC_MAG)
2776 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2777 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2778 ioread32(hw->hw_addr + REG_WOL_CTRL);
2779
2780 /* configure the mac */
2781 ctrl = MAC_CTRL_RX_EN;
2782 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2783 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2784 if (duplex == FULL_DUPLEX)
2785 ctrl |= MAC_CTRL_DUPLX;
2786 ctrl |= (((u32)adapter->hw.preamble_len &
2787 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2788 if (adapter->vlgrp)
2789 ctrl |= MAC_CTRL_RMV_VLAN;
2790 if (wufc & ATLX_WUFC_MAG)
2791 ctrl |= MAC_CTRL_BC_EN;
2792 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2793 ioread32(hw->hw_addr + REG_MAC_CTRL);
2794
2795 /* poke the PHY */
2796 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2797 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2798 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2799 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2800 } else {
2801 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2802 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2803 ioread32(hw->hw_addr + REG_WOL_CTRL);
2804 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2805 ioread32(hw->hw_addr + REG_MAC_CTRL);
2806 hw->phy_configured = false;
2807 }
2808
2809 return 0;
2810
2811 disable_wol:
2812 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2813 ioread32(hw->hw_addr + REG_WOL_CTRL);
2814 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2815 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2816 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2817 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2818 hw->phy_configured = false;
2819
2820 return 0;
2821 }
2822
2823 static int atl1_resume(struct device *dev)
2824 {
2825 struct pci_dev *pdev = to_pci_dev(dev);
2826 struct net_device *netdev = pci_get_drvdata(pdev);
2827 struct atl1_adapter *adapter = netdev_priv(netdev);
2828
2829 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2830
2831 atl1_reset_hw(&adapter->hw);
2832
2833 if (netif_running(netdev)) {
2834 adapter->cmb.cmb->int_stats = 0;
2835 atl1_up(adapter);
2836 }
2837 netif_device_attach(netdev);
2838
2839 return 0;
2840 }
2841
2842 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume);
2843 #define ATL1_PM_OPS (&atl1_pm_ops)
2844
2845 #else
2846
2847 static int atl1_suspend(struct device *dev) { return 0; }
2848
2849 #define ATL1_PM_OPS NULL
2850 #endif
2851
2852 static void atl1_shutdown(struct pci_dev *pdev)
2853 {
2854 struct net_device *netdev = pci_get_drvdata(pdev);
2855 struct atl1_adapter *adapter = netdev_priv(netdev);
2856
2857 atl1_suspend(&pdev->dev);
2858 pci_wake_from_d3(pdev, adapter->wol);
2859 pci_set_power_state(pdev, PCI_D3hot);
2860 }
2861
2862 #ifdef CONFIG_NET_POLL_CONTROLLER
2863 static void atl1_poll_controller(struct net_device *netdev)
2864 {
2865 disable_irq(netdev->irq);
2866 atl1_intr(netdev->irq, netdev);
2867 enable_irq(netdev->irq);
2868 }
2869 #endif
2870
2871 static const struct net_device_ops atl1_netdev_ops = {
2872 .ndo_open = atl1_open,
2873 .ndo_stop = atl1_close,
2874 .ndo_start_xmit = atl1_xmit_frame,
2875 .ndo_set_multicast_list = atlx_set_multi,
2876 .ndo_validate_addr = eth_validate_addr,
2877 .ndo_set_mac_address = atl1_set_mac,
2878 .ndo_change_mtu = atl1_change_mtu,
2879 .ndo_do_ioctl = atlx_ioctl,
2880 .ndo_tx_timeout = atlx_tx_timeout,
2881 .ndo_vlan_rx_register = atlx_vlan_rx_register,
2882 #ifdef CONFIG_NET_POLL_CONTROLLER
2883 .ndo_poll_controller = atl1_poll_controller,
2884 #endif
2885 };
2886
2887 /*
2888 * atl1_probe - Device Initialization Routine
2889 * @pdev: PCI device information struct
2890 * @ent: entry in atl1_pci_tbl
2891 *
2892 * Returns 0 on success, negative on failure
2893 *
2894 * atl1_probe initializes an adapter identified by a pci_dev structure.
2895 * The OS initialization, configuring of the adapter private structure,
2896 * and a hardware reset occur.
2897 */
2898 static int __devinit atl1_probe(struct pci_dev *pdev,
2899 const struct pci_device_id *ent)
2900 {
2901 struct net_device *netdev;
2902 struct atl1_adapter *adapter;
2903 static int cards_found = 0;
2904 int err;
2905
2906 err = pci_enable_device(pdev);
2907 if (err)
2908 return err;
2909
2910 /*
2911 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2912 * shared register for the high 32 bits, so only a single, aligned,
2913 * 4 GB physical address range can be used at a time.
2914 *
2915 * Supporting 64-bit DMA on this hardware is more trouble than it's
2916 * worth. It is far easier to limit to 32-bit DMA than update
2917 * various kernel subsystems to support the mechanics required by a
2918 * fixed-high-32-bit system.
2919 */
2920 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2921 if (err) {
2922 dev_err(&pdev->dev, "no usable DMA configuration\n");
2923 goto err_dma;
2924 }
2925 /*
2926 * Mark all PCI regions associated with PCI device
2927 * pdev as being reserved by owner atl1_driver_name
2928 */
2929 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2930 if (err)
2931 goto err_request_regions;
2932
2933 /*
2934 * Enables bus-mastering on the device and calls
2935 * pcibios_set_master to do the needed arch specific settings
2936 */
2937 pci_set_master(pdev);
2938
2939 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2940 if (!netdev) {
2941 err = -ENOMEM;
2942 goto err_alloc_etherdev;
2943 }
2944 SET_NETDEV_DEV(netdev, &pdev->dev);
2945
2946 pci_set_drvdata(pdev, netdev);
2947 adapter = netdev_priv(netdev);
2948 adapter->netdev = netdev;
2949 adapter->pdev = pdev;
2950 adapter->hw.back = adapter;
2951 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2952
2953 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2954 if (!adapter->hw.hw_addr) {
2955 err = -EIO;
2956 goto err_pci_iomap;
2957 }
2958 /* get device revision number */
2959 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2960 (REG_MASTER_CTRL + 2));
2961 if (netif_msg_probe(adapter))
2962 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
2963
2964 /* set default ring resource counts */
2965 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2966 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2967
2968 adapter->mii.dev = netdev;
2969 adapter->mii.mdio_read = mdio_read;
2970 adapter->mii.mdio_write = mdio_write;
2971 adapter->mii.phy_id_mask = 0x1f;
2972 adapter->mii.reg_num_mask = 0x1f;
2973
2974 netdev->netdev_ops = &atl1_netdev_ops;
2975 netdev->watchdog_timeo = 5 * HZ;
2976
2977 netdev->ethtool_ops = &atl1_ethtool_ops;
2978 adapter->bd_number = cards_found;
2979
2980 /* setup the private structure */
2981 err = atl1_sw_init(adapter);
2982 if (err)
2983 goto err_common;
2984
2985 netdev->features = NETIF_F_HW_CSUM;
2986 netdev->features |= NETIF_F_SG;
2987 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2988
2989 /*
2990 * patch for some L1 of old version,
2991 * the final version of L1 may not need these
2992 * patches
2993 */
2994 /* atl1_pcie_patch(adapter); */
2995
2996 /* really reset GPHY core */
2997 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
2998
2999 /*
3000 * reset the controller to
3001 * put the device in a known good starting state
3002 */
3003 if (atl1_reset_hw(&adapter->hw)) {
3004 err = -EIO;
3005 goto err_common;
3006 }
3007
3008 /* copy the MAC address out of the EEPROM */
3009 atl1_read_mac_addr(&adapter->hw);
3010 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3011
3012 if (!is_valid_ether_addr(netdev->dev_addr)) {
3013 err = -EIO;
3014 goto err_common;
3015 }
3016
3017 atl1_check_options(adapter);
3018
3019 /* pre-init the MAC, and setup link */
3020 err = atl1_init_hw(&adapter->hw);
3021 if (err) {
3022 err = -EIO;
3023 goto err_common;
3024 }
3025
3026 atl1_pcie_patch(adapter);
3027 /* assume we have no link for now */
3028 netif_carrier_off(netdev);
3029
3030 setup_timer(&adapter->phy_config_timer, atl1_phy_config,
3031 (unsigned long)adapter);
3032 adapter->phy_timer_pending = false;
3033
3034 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3035
3036 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3037
3038 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3039
3040 err = register_netdev(netdev);
3041 if (err)
3042 goto err_common;
3043
3044 cards_found++;
3045 atl1_via_workaround(adapter);
3046 return 0;
3047
3048 err_common:
3049 pci_iounmap(pdev, adapter->hw.hw_addr);
3050 err_pci_iomap:
3051 free_netdev(netdev);
3052 err_alloc_etherdev:
3053 pci_release_regions(pdev);
3054 err_dma:
3055 err_request_regions:
3056 pci_disable_device(pdev);
3057 return err;
3058 }
3059
3060 /*
3061 * atl1_remove - Device Removal Routine
3062 * @pdev: PCI device information struct
3063 *
3064 * atl1_remove is called by the PCI subsystem to alert the driver
3065 * that it should release a PCI device. The could be caused by a
3066 * Hot-Plug event, or because the driver is going to be removed from
3067 * memory.
3068 */
3069 static void __devexit atl1_remove(struct pci_dev *pdev)
3070 {
3071 struct net_device *netdev = pci_get_drvdata(pdev);
3072 struct atl1_adapter *adapter;
3073 /* Device not available. Return. */
3074 if (!netdev)
3075 return;
3076
3077 adapter = netdev_priv(netdev);
3078
3079 /*
3080 * Some atl1 boards lack persistent storage for their MAC, and get it
3081 * from the BIOS during POST. If we've been messing with the MAC
3082 * address, we need to save the permanent one.
3083 */
3084 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3085 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3086 ETH_ALEN);
3087 atl1_set_mac_addr(&adapter->hw);
3088 }
3089
3090 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3091 unregister_netdev(netdev);
3092 pci_iounmap(pdev, adapter->hw.hw_addr);
3093 pci_release_regions(pdev);
3094 free_netdev(netdev);
3095 pci_disable_device(pdev);
3096 }
3097
3098 static struct pci_driver atl1_driver = {
3099 .name = ATLX_DRIVER_NAME,
3100 .id_table = atl1_pci_tbl,
3101 .probe = atl1_probe,
3102 .remove = __devexit_p(atl1_remove),
3103 .shutdown = atl1_shutdown,
3104 .driver.pm = ATL1_PM_OPS,
3105 };
3106
3107 /*
3108 * atl1_exit_module - Driver Exit Cleanup Routine
3109 *
3110 * atl1_exit_module is called just before the driver is removed
3111 * from memory.
3112 */
3113 static void __exit atl1_exit_module(void)
3114 {
3115 pci_unregister_driver(&atl1_driver);
3116 }
3117
3118 /*
3119 * atl1_init_module - Driver Registration Routine
3120 *
3121 * atl1_init_module is the first routine called when the driver is
3122 * loaded. All it does is register with the PCI subsystem.
3123 */
3124 static int __init atl1_init_module(void)
3125 {
3126 return pci_register_driver(&atl1_driver);
3127 }
3128
3129 module_init(atl1_init_module);
3130 module_exit(atl1_exit_module);
3131
3132 struct atl1_stats {
3133 char stat_string[ETH_GSTRING_LEN];
3134 int sizeof_stat;
3135 int stat_offset;
3136 };
3137
3138 #define ATL1_STAT(m) \
3139 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3140
3141 static struct atl1_stats atl1_gstrings_stats[] = {
3142 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3143 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3144 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3145 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3146 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3147 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3148 {"multicast", ATL1_STAT(soft_stats.multicast)},
3149 {"collisions", ATL1_STAT(soft_stats.collisions)},
3150 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3151 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3152 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3153 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3154 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3155 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3156 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3157 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3158 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3159 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3160 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3161 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3162 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3163 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3164 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3165 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3166 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3167 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3168 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3169 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3170 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3171 };
3172
3173 static void atl1_get_ethtool_stats(struct net_device *netdev,
3174 struct ethtool_stats *stats, u64 *data)
3175 {
3176 struct atl1_adapter *adapter = netdev_priv(netdev);
3177 int i;
3178 char *p;
3179
3180 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3181 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3182 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3183 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3184 }
3185
3186 }
3187
3188 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3189 {
3190 switch (sset) {
3191 case ETH_SS_STATS:
3192 return ARRAY_SIZE(atl1_gstrings_stats);
3193 default:
3194 return -EOPNOTSUPP;
3195 }
3196 }
3197
3198 static int atl1_get_settings(struct net_device *netdev,
3199 struct ethtool_cmd *ecmd)
3200 {
3201 struct atl1_adapter *adapter = netdev_priv(netdev);
3202 struct atl1_hw *hw = &adapter->hw;
3203
3204 ecmd->supported = (SUPPORTED_10baseT_Half |
3205 SUPPORTED_10baseT_Full |
3206 SUPPORTED_100baseT_Half |
3207 SUPPORTED_100baseT_Full |
3208 SUPPORTED_1000baseT_Full |
3209 SUPPORTED_Autoneg | SUPPORTED_TP);
3210 ecmd->advertising = ADVERTISED_TP;
3211 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3212 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3213 ecmd->advertising |= ADVERTISED_Autoneg;
3214 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3215 ecmd->advertising |= ADVERTISED_Autoneg;
3216 ecmd->advertising |=
3217 (ADVERTISED_10baseT_Half |
3218 ADVERTISED_10baseT_Full |
3219 ADVERTISED_100baseT_Half |
3220 ADVERTISED_100baseT_Full |
3221 ADVERTISED_1000baseT_Full);
3222 } else
3223 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3224 }
3225 ecmd->port = PORT_TP;
3226 ecmd->phy_address = 0;
3227 ecmd->transceiver = XCVR_INTERNAL;
3228
3229 if (netif_carrier_ok(adapter->netdev)) {
3230 u16 link_speed, link_duplex;
3231 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3232 ecmd->speed = link_speed;
3233 if (link_duplex == FULL_DUPLEX)
3234 ecmd->duplex = DUPLEX_FULL;
3235 else
3236 ecmd->duplex = DUPLEX_HALF;
3237 } else {
3238 ecmd->speed = -1;
3239 ecmd->duplex = -1;
3240 }
3241 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3242 hw->media_type == MEDIA_TYPE_1000M_FULL)
3243 ecmd->autoneg = AUTONEG_ENABLE;
3244 else
3245 ecmd->autoneg = AUTONEG_DISABLE;
3246
3247 return 0;
3248 }
3249
3250 static int atl1_set_settings(struct net_device *netdev,
3251 struct ethtool_cmd *ecmd)
3252 {
3253 struct atl1_adapter *adapter = netdev_priv(netdev);
3254 struct atl1_hw *hw = &adapter->hw;
3255 u16 phy_data;
3256 int ret_val = 0;
3257 u16 old_media_type = hw->media_type;
3258
3259 if (netif_running(adapter->netdev)) {
3260 if (netif_msg_link(adapter))
3261 dev_dbg(&adapter->pdev->dev,
3262 "ethtool shutting down adapter\n");
3263 atl1_down(adapter);
3264 }
3265
3266 if (ecmd->autoneg == AUTONEG_ENABLE)
3267 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3268 else {
3269 if (ecmd->speed == SPEED_1000) {
3270 if (ecmd->duplex != DUPLEX_FULL) {
3271 if (netif_msg_link(adapter))
3272 dev_warn(&adapter->pdev->dev,
3273 "1000M half is invalid\n");
3274 ret_val = -EINVAL;
3275 goto exit_sset;
3276 }
3277 hw->media_type = MEDIA_TYPE_1000M_FULL;
3278 } else if (ecmd->speed == SPEED_100) {
3279 if (ecmd->duplex == DUPLEX_FULL)
3280 hw->media_type = MEDIA_TYPE_100M_FULL;
3281 else
3282 hw->media_type = MEDIA_TYPE_100M_HALF;
3283 } else {
3284 if (ecmd->duplex == DUPLEX_FULL)
3285 hw->media_type = MEDIA_TYPE_10M_FULL;
3286 else
3287 hw->media_type = MEDIA_TYPE_10M_HALF;
3288 }
3289 }
3290 switch (hw->media_type) {
3291 case MEDIA_TYPE_AUTO_SENSOR:
3292 ecmd->advertising =
3293 ADVERTISED_10baseT_Half |
3294 ADVERTISED_10baseT_Full |
3295 ADVERTISED_100baseT_Half |
3296 ADVERTISED_100baseT_Full |
3297 ADVERTISED_1000baseT_Full |
3298 ADVERTISED_Autoneg | ADVERTISED_TP;
3299 break;
3300 case MEDIA_TYPE_1000M_FULL:
3301 ecmd->advertising =
3302 ADVERTISED_1000baseT_Full |
3303 ADVERTISED_Autoneg | ADVERTISED_TP;
3304 break;
3305 default:
3306 ecmd->advertising = 0;
3307 break;
3308 }
3309 if (atl1_phy_setup_autoneg_adv(hw)) {
3310 ret_val = -EINVAL;
3311 if (netif_msg_link(adapter))
3312 dev_warn(&adapter->pdev->dev,
3313 "invalid ethtool speed/duplex setting\n");
3314 goto exit_sset;
3315 }
3316 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3317 hw->media_type == MEDIA_TYPE_1000M_FULL)
3318 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3319 else {
3320 switch (hw->media_type) {
3321 case MEDIA_TYPE_100M_FULL:
3322 phy_data =
3323 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3324 MII_CR_RESET;
3325 break;
3326 case MEDIA_TYPE_100M_HALF:
3327 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3328 break;
3329 case MEDIA_TYPE_10M_FULL:
3330 phy_data =
3331 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3332 break;
3333 default:
3334 /* MEDIA_TYPE_10M_HALF: */
3335 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3336 break;
3337 }
3338 }
3339 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3340 exit_sset:
3341 if (ret_val)
3342 hw->media_type = old_media_type;
3343
3344 if (netif_running(adapter->netdev)) {
3345 if (netif_msg_link(adapter))
3346 dev_dbg(&adapter->pdev->dev,
3347 "ethtool starting adapter\n");
3348 atl1_up(adapter);
3349 } else if (!ret_val) {
3350 if (netif_msg_link(adapter))
3351 dev_dbg(&adapter->pdev->dev,
3352 "ethtool resetting adapter\n");
3353 atl1_reset(adapter);
3354 }
3355 return ret_val;
3356 }
3357
3358 static void atl1_get_drvinfo(struct net_device *netdev,
3359 struct ethtool_drvinfo *drvinfo)
3360 {
3361 struct atl1_adapter *adapter = netdev_priv(netdev);
3362
3363 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3364 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
3365 sizeof(drvinfo->version));
3366 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3367 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
3368 sizeof(drvinfo->bus_info));
3369 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3370 }
3371
3372 static void atl1_get_wol(struct net_device *netdev,
3373 struct ethtool_wolinfo *wol)
3374 {
3375 struct atl1_adapter *adapter = netdev_priv(netdev);
3376
3377 wol->supported = WAKE_MAGIC;
3378 wol->wolopts = 0;
3379 if (adapter->wol & ATLX_WUFC_MAG)
3380 wol->wolopts |= WAKE_MAGIC;
3381 }
3382
3383 static int atl1_set_wol(struct net_device *netdev,
3384 struct ethtool_wolinfo *wol)
3385 {
3386 struct atl1_adapter *adapter = netdev_priv(netdev);
3387
3388 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3389 WAKE_ARP | WAKE_MAGICSECURE))
3390 return -EOPNOTSUPP;
3391 adapter->wol = 0;
3392 if (wol->wolopts & WAKE_MAGIC)
3393 adapter->wol |= ATLX_WUFC_MAG;
3394
3395 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
3396
3397 return 0;
3398 }
3399
3400 static u32 atl1_get_msglevel(struct net_device *netdev)
3401 {
3402 struct atl1_adapter *adapter = netdev_priv(netdev);
3403 return adapter->msg_enable;
3404 }
3405
3406 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3407 {
3408 struct atl1_adapter *adapter = netdev_priv(netdev);
3409 adapter->msg_enable = value;
3410 }
3411
3412 static int atl1_get_regs_len(struct net_device *netdev)
3413 {
3414 return ATL1_REG_COUNT * sizeof(u32);
3415 }
3416
3417 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3418 void *p)
3419 {
3420 struct atl1_adapter *adapter = netdev_priv(netdev);
3421 struct atl1_hw *hw = &adapter->hw;
3422 unsigned int i;
3423 u32 *regbuf = p;
3424
3425 for (i = 0; i < ATL1_REG_COUNT; i++) {
3426 /*
3427 * This switch statement avoids reserved regions
3428 * of register space.
3429 */
3430 switch (i) {
3431 case 6 ... 9:
3432 case 14:
3433 case 29 ... 31:
3434 case 34 ... 63:
3435 case 75 ... 127:
3436 case 136 ... 1023:
3437 case 1027 ... 1087:
3438 case 1091 ... 1151:
3439 case 1194 ... 1195:
3440 case 1200 ... 1201:
3441 case 1206 ... 1213:
3442 case 1216 ... 1279:
3443 case 1290 ... 1311:
3444 case 1323 ... 1343:
3445 case 1358 ... 1359:
3446 case 1368 ... 1375:
3447 case 1378 ... 1383:
3448 case 1388 ... 1391:
3449 case 1393 ... 1395:
3450 case 1402 ... 1403:
3451 case 1410 ... 1471:
3452 case 1522 ... 1535:
3453 /* reserved region; don't read it */
3454 regbuf[i] = 0;
3455 break;
3456 default:
3457 /* unreserved region */
3458 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3459 }
3460 }
3461 }
3462
3463 static void atl1_get_ringparam(struct net_device *netdev,
3464 struct ethtool_ringparam *ring)
3465 {
3466 struct atl1_adapter *adapter = netdev_priv(netdev);
3467 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3468 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3469
3470 ring->rx_max_pending = ATL1_MAX_RFD;
3471 ring->tx_max_pending = ATL1_MAX_TPD;
3472 ring->rx_mini_max_pending = 0;
3473 ring->rx_jumbo_max_pending = 0;
3474 ring->rx_pending = rxdr->count;
3475 ring->tx_pending = txdr->count;
3476 ring->rx_mini_pending = 0;
3477 ring->rx_jumbo_pending = 0;
3478 }
3479
3480 static int atl1_set_ringparam(struct net_device *netdev,
3481 struct ethtool_ringparam *ring)
3482 {
3483 struct atl1_adapter *adapter = netdev_priv(netdev);
3484 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3485 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3486 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3487
3488 struct atl1_tpd_ring tpd_old, tpd_new;
3489 struct atl1_rfd_ring rfd_old, rfd_new;
3490 struct atl1_rrd_ring rrd_old, rrd_new;
3491 struct atl1_ring_header rhdr_old, rhdr_new;
3492 struct atl1_smb smb;
3493 struct atl1_cmb cmb;
3494 int err;
3495
3496 tpd_old = adapter->tpd_ring;
3497 rfd_old = adapter->rfd_ring;
3498 rrd_old = adapter->rrd_ring;
3499 rhdr_old = adapter->ring_header;
3500
3501 if (netif_running(adapter->netdev))
3502 atl1_down(adapter);
3503
3504 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3505 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3506 rfdr->count;
3507 rfdr->count = (rfdr->count + 3) & ~3;
3508 rrdr->count = rfdr->count;
3509
3510 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3511 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3512 tpdr->count;
3513 tpdr->count = (tpdr->count + 3) & ~3;
3514
3515 if (netif_running(adapter->netdev)) {
3516 /* try to get new resources before deleting old */
3517 err = atl1_setup_ring_resources(adapter);
3518 if (err)
3519 goto err_setup_ring;
3520
3521 /*
3522 * save the new, restore the old in order to free it,
3523 * then restore the new back again
3524 */
3525
3526 rfd_new = adapter->rfd_ring;
3527 rrd_new = adapter->rrd_ring;
3528 tpd_new = adapter->tpd_ring;
3529 rhdr_new = adapter->ring_header;
3530 adapter->rfd_ring = rfd_old;
3531 adapter->rrd_ring = rrd_old;
3532 adapter->tpd_ring = tpd_old;
3533 adapter->ring_header = rhdr_old;
3534 /*
3535 * Save SMB and CMB, since atl1_free_ring_resources
3536 * will clear them.
3537 */
3538 smb = adapter->smb;
3539 cmb = adapter->cmb;
3540 atl1_free_ring_resources(adapter);
3541 adapter->rfd_ring = rfd_new;
3542 adapter->rrd_ring = rrd_new;
3543 adapter->tpd_ring = tpd_new;
3544 adapter->ring_header = rhdr_new;
3545 adapter->smb = smb;
3546 adapter->cmb = cmb;
3547
3548 err = atl1_up(adapter);
3549 if (err)
3550 return err;
3551 }
3552 return 0;
3553
3554 err_setup_ring:
3555 adapter->rfd_ring = rfd_old;
3556 adapter->rrd_ring = rrd_old;
3557 adapter->tpd_ring = tpd_old;
3558 adapter->ring_header = rhdr_old;
3559 atl1_up(adapter);
3560 return err;
3561 }
3562
3563 static void atl1_get_pauseparam(struct net_device *netdev,
3564 struct ethtool_pauseparam *epause)
3565 {
3566 struct atl1_adapter *adapter = netdev_priv(netdev);
3567 struct atl1_hw *hw = &adapter->hw;
3568
3569 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3570 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3571 epause->autoneg = AUTONEG_ENABLE;
3572 } else {
3573 epause->autoneg = AUTONEG_DISABLE;
3574 }
3575 epause->rx_pause = 1;
3576 epause->tx_pause = 1;
3577 }
3578
3579 static int atl1_set_pauseparam(struct net_device *netdev,
3580 struct ethtool_pauseparam *epause)
3581 {
3582 struct atl1_adapter *adapter = netdev_priv(netdev);
3583 struct atl1_hw *hw = &adapter->hw;
3584
3585 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3586 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3587 epause->autoneg = AUTONEG_ENABLE;
3588 } else {
3589 epause->autoneg = AUTONEG_DISABLE;
3590 }
3591
3592 epause->rx_pause = 1;
3593 epause->tx_pause = 1;
3594
3595 return 0;
3596 }
3597
3598 /* FIXME: is this right? -- CHS */
3599 static u32 atl1_get_rx_csum(struct net_device *netdev)
3600 {
3601 return 1;
3602 }
3603
3604 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3605 u8 *data)
3606 {
3607 u8 *p = data;
3608 int i;
3609
3610 switch (stringset) {
3611 case ETH_SS_STATS:
3612 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3613 memcpy(p, atl1_gstrings_stats[i].stat_string,
3614 ETH_GSTRING_LEN);
3615 p += ETH_GSTRING_LEN;
3616 }
3617 break;
3618 }
3619 }
3620
3621 static int atl1_nway_reset(struct net_device *netdev)
3622 {
3623 struct atl1_adapter *adapter = netdev_priv(netdev);
3624 struct atl1_hw *hw = &adapter->hw;
3625
3626 if (netif_running(netdev)) {
3627 u16 phy_data;
3628 atl1_down(adapter);
3629
3630 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3631 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3632 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3633 } else {
3634 switch (hw->media_type) {
3635 case MEDIA_TYPE_100M_FULL:
3636 phy_data = MII_CR_FULL_DUPLEX |
3637 MII_CR_SPEED_100 | MII_CR_RESET;
3638 break;
3639 case MEDIA_TYPE_100M_HALF:
3640 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3641 break;
3642 case MEDIA_TYPE_10M_FULL:
3643 phy_data = MII_CR_FULL_DUPLEX |
3644 MII_CR_SPEED_10 | MII_CR_RESET;
3645 break;
3646 default:
3647 /* MEDIA_TYPE_10M_HALF */
3648 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3649 }
3650 }
3651 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3652 atl1_up(adapter);
3653 }
3654 return 0;
3655 }
3656
3657 static const struct ethtool_ops atl1_ethtool_ops = {
3658 .get_settings = atl1_get_settings,
3659 .set_settings = atl1_set_settings,
3660 .get_drvinfo = atl1_get_drvinfo,
3661 .get_wol = atl1_get_wol,
3662 .set_wol = atl1_set_wol,
3663 .get_msglevel = atl1_get_msglevel,
3664 .set_msglevel = atl1_set_msglevel,
3665 .get_regs_len = atl1_get_regs_len,
3666 .get_regs = atl1_get_regs,
3667 .get_ringparam = atl1_get_ringparam,
3668 .set_ringparam = atl1_set_ringparam,
3669 .get_pauseparam = atl1_get_pauseparam,
3670 .set_pauseparam = atl1_set_pauseparam,
3671 .get_rx_csum = atl1_get_rx_csum,
3672 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3673 .get_link = ethtool_op_get_link,
3674 .set_sg = ethtool_op_set_sg,
3675 .get_strings = atl1_get_strings,
3676 .nway_reset = atl1_nway_reset,
3677 .get_ethtool_stats = atl1_get_ethtool_stats,
3678 .get_sset_count = atl1_get_sset_count,
3679 .set_tso = ethtool_op_set_tso,
3680 };
Mirror of the linux-mips.org kernel tree