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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / net / bnx2x / bnx2x.h
blobe0fca701d2f3c141dc2a1b6a7b7820c9ab5f8c92
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/types.h>
18
19 /* compilation time flags */
20
21 /* define this to make the driver freeze on error to allow getting debug info
22 * (you will need to reboot afterwards) */
23 /* #define BNX2X_STOP_ON_ERROR */
24
25 #define DRV_MODULE_VERSION "1.62.11-0"
26 #define DRV_MODULE_RELDATE "2011/01/31"
27 #define BNX2X_BC_VER 0x040200
28
29 #define BNX2X_MULTI_QUEUE
30
31 #define BNX2X_NEW_NAPI
32
33 #if defined(CONFIG_DCB)
34 #define BCM_DCBNL
35 #endif
36 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
37 #define BCM_CNIC 1
38 #include "../cnic_if.h"
39 #endif
40
41 #ifdef BCM_CNIC
42 #define BNX2X_MIN_MSIX_VEC_CNT 3
43 #define BNX2X_MSIX_VEC_FP_START 2
44 #else
45 #define BNX2X_MIN_MSIX_VEC_CNT 2
46 #define BNX2X_MSIX_VEC_FP_START 1
47 #endif
48
49 #include <linux/mdio.h>
50 #include <linux/pci.h>
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_hsi.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_dcb.h"
56 #include "bnx2x_stats.h"
57
58 /* error/debug prints */
59
60 #define DRV_MODULE_NAME "bnx2x"
61
62 /* for messages that are currently off */
63 #define BNX2X_MSG_OFF 0
64 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
66 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
68 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
69 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
70
71 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
72
73 /* regular debug print */
74 #define DP(__mask, __fmt, __args...) \
75 do { \
76 if (bp->msg_enable & (__mask)) \
77 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
78 __func__, __LINE__, \
79 bp->dev ? (bp->dev->name) : "?", \
80 ##__args); \
81 } while (0)
82
83 /* errors debug print */
84 #define BNX2X_DBG_ERR(__fmt, __args...) \
85 do { \
86 if (netif_msg_probe(bp)) \
87 pr_err("[%s:%d(%s)]" __fmt, \
88 __func__, __LINE__, \
89 bp->dev ? (bp->dev->name) : "?", \
90 ##__args); \
91 } while (0)
92
93 /* for errors (never masked) */
94 #define BNX2X_ERR(__fmt, __args...) \
95 do { \
96 pr_err("[%s:%d(%s)]" __fmt, \
97 __func__, __LINE__, \
98 bp->dev ? (bp->dev->name) : "?", \
99 ##__args); \
100 } while (0)
101
102 #define BNX2X_ERROR(__fmt, __args...) do { \
103 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
104 } while (0)
105
106
107 /* before we have a dev->name use dev_info() */
108 #define BNX2X_DEV_INFO(__fmt, __args...) \
109 do { \
110 if (netif_msg_probe(bp)) \
111 dev_info(&bp->pdev->dev, __fmt, ##__args); \
112 } while (0)
113
114 void bnx2x_panic_dump(struct bnx2x *bp);
115
116 #ifdef BNX2X_STOP_ON_ERROR
117 #define bnx2x_panic() do { \
118 bp->panic = 1; \
119 BNX2X_ERR("driver assert\n"); \
120 bnx2x_int_disable(bp); \
121 bnx2x_panic_dump(bp); \
122 } while (0)
123 #else
124 #define bnx2x_panic() do { \
125 bp->panic = 1; \
126 BNX2X_ERR("driver assert\n"); \
127 bnx2x_panic_dump(bp); \
128 } while (0)
129 #endif
130
131 #define bnx2x_mc_addr(ha) ((ha)->addr)
132 #define bnx2x_uc_addr(ha) ((ha)->addr)
133
134 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
135 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
136 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
137
138
139 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
140
141 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
142 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
143 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
144
145 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
146 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
147 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
148
149 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
150 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
151
152 #define REG_RD_DMAE(bp, offset, valp, len32) \
153 do { \
154 bnx2x_read_dmae(bp, offset, len32);\
155 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
156 } while (0)
157
158 #define REG_WR_DMAE(bp, offset, valp, len32) \
159 do { \
160 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
161 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
162 offset, len32); \
163 } while (0)
164
165 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
166 REG_WR_DMAE(bp, offset, valp, len32)
167
168 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
169 do { \
170 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
171 bnx2x_write_big_buf_wb(bp, addr, len32); \
172 } while (0)
173
174 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
175 offsetof(struct shmem_region, field))
176 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
177 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
178
179 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
180 offsetof(struct shmem2_region, field))
181 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
182 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
183 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
184 offsetof(struct mf_cfg, field))
185 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
186 offsetof(struct mf2_cfg, field))
187
188 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
189 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
190 MF_CFG_ADDR(bp, field), (val))
191 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
192
193 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
194 (SHMEM2_RD((bp), size) > \
195 offsetof(struct shmem2_region, field)))
196
197 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
198 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
199
200 /* SP SB indices */
201
202 /* General SP events - stats query, cfc delete, etc */
203 #define HC_SP_INDEX_ETH_DEF_CONS 3
204
205 /* EQ completions */
206 #define HC_SP_INDEX_EQ_CONS 7
207
208 /* FCoE L2 connection completions */
209 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
210 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
211 /* iSCSI L2 */
212 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
213 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
214
215 /* Special clients parameters */
216
217 /* SB indices */
218 /* FCoE L2 */
219 #define BNX2X_FCOE_L2_RX_INDEX \
220 (&bp->def_status_blk->sp_sb.\
221 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
222
223 #define BNX2X_FCOE_L2_TX_INDEX \
224 (&bp->def_status_blk->sp_sb.\
225 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
226
227 /**
228 * CIDs and CLIDs:
229 * CLIDs below is a CLID for func 0, then the CLID for other
230 * functions will be calculated by the formula:
231 *
232 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
233 *
234 */
235 /* iSCSI L2 */
236 #define BNX2X_ISCSI_ETH_CL_ID 17
237 #define BNX2X_ISCSI_ETH_CID 17
238
239 /* FCoE L2 */
240 #define BNX2X_FCOE_ETH_CL_ID 18
241 #define BNX2X_FCOE_ETH_CID 18
242
243 /** Additional rings budgeting */
244 #ifdef BCM_CNIC
245 #define CNIC_CONTEXT_USE 1
246 #define FCOE_CONTEXT_USE 1
247 #else
248 #define CNIC_CONTEXT_USE 0
249 #define FCOE_CONTEXT_USE 0
250 #endif /* BCM_CNIC */
251 #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE)
252
253 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
254 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
255
256 #define SM_RX_ID 0
257 #define SM_TX_ID 1
258
259 /* fast path */
260
261 struct sw_rx_bd {
262 struct sk_buff *skb;
263 DEFINE_DMA_UNMAP_ADDR(mapping);
264 };
265
266 struct sw_tx_bd {
267 struct sk_buff *skb;
268 u16 first_bd;
269 u8 flags;
270 /* Set on the first BD descriptor when there is a split BD */
271 #define BNX2X_TSO_SPLIT_BD (1<<0)
272 };
273
274 struct sw_rx_page {
275 struct page *page;
276 DEFINE_DMA_UNMAP_ADDR(mapping);
277 };
278
279 union db_prod {
280 struct doorbell_set_prod data;
281 u32 raw;
282 };
283
284
285 /* MC hsi */
286 #define BCM_PAGE_SHIFT 12
287 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
288 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
289 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
290
291 #define PAGES_PER_SGE_SHIFT 0
292 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
293 #define SGE_PAGE_SIZE PAGE_SIZE
294 #define SGE_PAGE_SHIFT PAGE_SHIFT
295 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
296
297 /* SGE ring related macros */
298 #define NUM_RX_SGE_PAGES 2
299 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
300 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
301 /* RX_SGE_CNT is promised to be a power of 2 */
302 #define RX_SGE_MASK (RX_SGE_CNT - 1)
303 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
304 #define MAX_RX_SGE (NUM_RX_SGE - 1)
305 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
306 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
307 #define RX_SGE(x) ((x) & MAX_RX_SGE)
308
309 /* SGE producer mask related macros */
310 /* Number of bits in one sge_mask array element */
311 #define RX_SGE_MASK_ELEM_SZ 64
312 #define RX_SGE_MASK_ELEM_SHIFT 6
313 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
314
315 /* Creates a bitmask of all ones in less significant bits.
316 idx - index of the most significant bit in the created mask */
317 #define RX_SGE_ONES_MASK(idx) \
318 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
319 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
320
321 /* Number of u64 elements in SGE mask array */
322 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
323 RX_SGE_MASK_ELEM_SZ)
324 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
325 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
326
327 union host_hc_status_block {
328 /* pointer to fp status block e1x */
329 struct host_hc_status_block_e1x *e1x_sb;
330 /* pointer to fp status block e2 */
331 struct host_hc_status_block_e2 *e2_sb;
332 };
333
334 struct bnx2x_fastpath {
335
336 #define BNX2X_NAPI_WEIGHT 128
337 struct napi_struct napi;
338 union host_hc_status_block status_blk;
339 /* chip independed shortcuts into sb structure */
340 __le16 *sb_index_values;
341 __le16 *sb_running_index;
342 /* chip independed shortcut into rx_prods_offset memory */
343 u32 ustorm_rx_prods_offset;
344
345 u32 rx_buf_size;
346
347 dma_addr_t status_blk_mapping;
348
349 struct sw_tx_bd *tx_buf_ring;
350
351 union eth_tx_bd_types *tx_desc_ring;
352 dma_addr_t tx_desc_mapping;
353
354 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
355 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
356
357 struct eth_rx_bd *rx_desc_ring;
358 dma_addr_t rx_desc_mapping;
359
360 union eth_rx_cqe *rx_comp_ring;
361 dma_addr_t rx_comp_mapping;
362
363 /* SGE ring */
364 struct eth_rx_sge *rx_sge_ring;
365 dma_addr_t rx_sge_mapping;
366
367 u64 sge_mask[RX_SGE_MASK_LEN];
368
369 int state;
370 #define BNX2X_FP_STATE_CLOSED 0
371 #define BNX2X_FP_STATE_IRQ 0x80000
372 #define BNX2X_FP_STATE_OPENING 0x90000
373 #define BNX2X_FP_STATE_OPEN 0xa0000
374 #define BNX2X_FP_STATE_HALTING 0xb0000
375 #define BNX2X_FP_STATE_HALTED 0xc0000
376 #define BNX2X_FP_STATE_TERMINATING 0xd0000
377 #define BNX2X_FP_STATE_TERMINATED 0xe0000
378
379 u8 index; /* number in fp array */
380 u8 cl_id; /* eth client id */
381 u8 cl_qzone_id;
382 u8 fw_sb_id; /* status block number in FW */
383 u8 igu_sb_id; /* status block number in HW */
384 u32 cid;
385
386 union db_prod tx_db;
387
388 u16 tx_pkt_prod;
389 u16 tx_pkt_cons;
390 u16 tx_bd_prod;
391 u16 tx_bd_cons;
392 __le16 *tx_cons_sb;
393
394 __le16 fp_hc_idx;
395
396 u16 rx_bd_prod;
397 u16 rx_bd_cons;
398 u16 rx_comp_prod;
399 u16 rx_comp_cons;
400 u16 rx_sge_prod;
401 /* The last maximal completed SGE */
402 u16 last_max_sge;
403 __le16 *rx_cons_sb;
404
405 unsigned long tx_pkt,
406 rx_pkt,
407 rx_calls;
408
409 /* TPA related */
410 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
411 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
412 #define BNX2X_TPA_START 1
413 #define BNX2X_TPA_STOP 2
414 u8 disable_tpa;
415 #ifdef BNX2X_STOP_ON_ERROR
416 u64 tpa_queue_used;
417 #endif
418
419 struct tstorm_per_client_stats old_tclient;
420 struct ustorm_per_client_stats old_uclient;
421 struct xstorm_per_client_stats old_xclient;
422 struct bnx2x_eth_q_stats eth_q_stats;
423
424 /* The size is calculated using the following:
425 sizeof name field from netdev structure +
426 4 ('-Xx-' string) +
427 4 (for the digits and to make it DWORD aligned) */
428 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
429 char name[FP_NAME_SIZE];
430 struct bnx2x *bp; /* parent */
431 };
432
433 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
434
435 /* Use 2500 as a mini-jumbo MTU for FCoE */
436 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
437
438 #ifdef BCM_CNIC
439 /* FCoE L2 `fastpath' is right after the eth entries */
440 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
441 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
442 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
443 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
444 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
445 #else
446 #define IS_FCOE_FP(fp) false
447 #define IS_FCOE_IDX(idx) false
448 #endif
449
450
451 /* MC hsi */
452 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
453 #define RX_COPY_THRESH 92
454
455 #define NUM_TX_RINGS 16
456 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
457 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
458 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
459 #define MAX_TX_BD (NUM_TX_BD - 1)
460 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
461 #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
462 #define INIT_TX_RING_SIZE MAX_TX_AVAIL
463 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
464 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
465 #define TX_BD(x) ((x) & MAX_TX_BD)
466 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
467
468 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
469 #define NUM_RX_RINGS 8
470 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
471 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
472 #define RX_DESC_MASK (RX_DESC_CNT - 1)
473 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
474 #define MAX_RX_BD (NUM_RX_BD - 1)
475 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
476 #define MIN_RX_AVAIL 128
477 #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
478 #define INIT_RX_RING_SIZE MAX_RX_AVAIL
479 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
480 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
481 #define RX_BD(x) ((x) & MAX_RX_BD)
482
483 /* As long as CQE is 4 times bigger than BD entry we have to allocate
484 4 times more pages for CQ ring in order to keep it balanced with
485 BD ring */
486 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
487 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
488 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
489 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
490 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
491 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
492 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
493 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
494 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
495
496
497 /* This is needed for determining of last_max */
498 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
499
500 #define __SGE_MASK_SET_BIT(el, bit) \
501 do { \
502 el = ((el) | ((u64)0x1 << (bit))); \
503 } while (0)
504
505 #define __SGE_MASK_CLEAR_BIT(el, bit) \
506 do { \
507 el = ((el) & (~((u64)0x1 << (bit)))); \
508 } while (0)
509
510 #define SGE_MASK_SET_BIT(fp, idx) \
511 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
512 ((idx) & RX_SGE_MASK_ELEM_MASK))
513
514 #define SGE_MASK_CLEAR_BIT(fp, idx) \
515 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
516 ((idx) & RX_SGE_MASK_ELEM_MASK))
517
518
519 /* used on a CID received from the HW */
520 #define SW_CID(x) (le32_to_cpu(x) & \
521 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
522 #define CQE_CMD(x) (le32_to_cpu(x) >> \
523 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
524
525 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
526 le32_to_cpu((bd)->addr_lo))
527 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
528
529 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
530 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
531 #define DPM_TRIGER_TYPE 0x40
532 #define DOORBELL(bp, cid, val) \
533 do { \
534 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
535 DPM_TRIGER_TYPE); \
536 } while (0)
537
538
539 /* TX CSUM helpers */
540 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
541 skb->csum_offset)
542 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
543 skb->csum_offset))
544
545 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
546
547 #define XMIT_PLAIN 0
548 #define XMIT_CSUM_V4 0x1
549 #define XMIT_CSUM_V6 0x2
550 #define XMIT_CSUM_TCP 0x4
551 #define XMIT_GSO_V4 0x8
552 #define XMIT_GSO_V6 0x10
553
554 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
555 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
556
557
558 /* stuff added to make the code fit 80Col */
559
560 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
561
562 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
563 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
564 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
565 (TPA_TYPE_START | TPA_TYPE_END))
566
567 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
568
569 #define BNX2X_IP_CSUM_ERR(cqe) \
570 (!((cqe)->fast_path_cqe.status_flags & \
571 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
572 ((cqe)->fast_path_cqe.type_error_flags & \
573 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
574
575 #define BNX2X_L4_CSUM_ERR(cqe) \
576 (!((cqe)->fast_path_cqe.status_flags & \
577 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
578 ((cqe)->fast_path_cqe.type_error_flags & \
579 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
580
581 #define BNX2X_RX_CSUM_OK(cqe) \
582 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
583
584 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
585 (((le16_to_cpu(flags) & \
586 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
587 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
588 == PRS_FLAG_OVERETH_IPV4)
589 #define BNX2X_RX_SUM_FIX(cqe) \
590 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
591
592 #define U_SB_ETH_RX_CQ_INDEX 1
593 #define U_SB_ETH_RX_BD_INDEX 2
594 #define C_SB_ETH_TX_CQ_INDEX 5
595
596 #define BNX2X_RX_SB_INDEX \
597 (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
598
599 #define BNX2X_TX_SB_INDEX \
600 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
601
602 /* end of fast path */
603
604 /* common */
605
606 struct bnx2x_common {
607
608 u32 chip_id;
609 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
610 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
611
612 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
613 #define CHIP_NUM_57710 0x164e
614 #define CHIP_NUM_57711 0x164f
615 #define CHIP_NUM_57711E 0x1650
616 #define CHIP_NUM_57712 0x1662
617 #define CHIP_NUM_57712E 0x1663
618 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
619 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
620 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
621 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
622 #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E)
623 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
624 CHIP_IS_57711E(bp))
625 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
626 CHIP_IS_57712E(bp))
627 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
628 #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp))
629
630 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
631 #define CHIP_REV_Ax 0x00000000
632 /* assume maximum 5 revisions */
633 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
634 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
635 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
636 !(CHIP_REV(bp) & 0x00001000))
637 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
638 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
639 (CHIP_REV(bp) & 0x00001000))
640
641 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
642 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
643
644 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
645 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
646 #define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
647
648 int flash_size;
649 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
650 #define NVRAM_TIMEOUT_COUNT 30000
651 #define NVRAM_PAGE_SIZE 256
652
653 u32 shmem_base;
654 u32 shmem2_base;
655 u32 mf_cfg_base;
656 u32 mf2_cfg_base;
657
658 u32 hw_config;
659
660 u32 bc_ver;
661
662 u8 int_block;
663 #define INT_BLOCK_HC 0
664 #define INT_BLOCK_IGU 1
665 #define INT_BLOCK_MODE_NORMAL 0
666 #define INT_BLOCK_MODE_BW_COMP 2
667 #define CHIP_INT_MODE_IS_NBC(bp) \
668 (CHIP_IS_E2(bp) && \
669 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
670 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
671
672 u8 chip_port_mode;
673 #define CHIP_4_PORT_MODE 0x0
674 #define CHIP_2_PORT_MODE 0x1
675 #define CHIP_PORT_MODE_NONE 0x2
676 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
677 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
678 };
679
680 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
681 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
682 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
683
684 /* end of common */
685
686 /* port */
687
688 struct bnx2x_port {
689 u32 pmf;
690
691 u32 link_config[LINK_CONFIG_SIZE];
692
693 u32 supported[LINK_CONFIG_SIZE];
694 /* link settings - missing defines */
695 #define SUPPORTED_2500baseX_Full (1 << 15)
696
697 u32 advertising[LINK_CONFIG_SIZE];
698 /* link settings - missing defines */
699 #define ADVERTISED_2500baseX_Full (1 << 15)
700
701 u32 phy_addr;
702
703 /* used to synchronize phy accesses */
704 struct mutex phy_mutex;
705 int need_hw_lock;
706
707 u32 port_stx;
708
709 struct nig_stats old_nig_stats;
710 };
711
712 /* end of port */
713
714 /* e1h Classification CAM line allocations */
715 enum {
716 CAM_ETH_LINE = 0,
717 CAM_ISCSI_ETH_LINE,
718 CAM_FIP_ETH_LINE,
719 CAM_FIP_MCAST_LINE,
720 CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE
721 };
722 /* number of MACs per function in NIG memory - used for SI mode */
723 #define NIG_LLH_FUNC_MEM_SIZE 16
724 /* number of entries in NIG_REG_LLHX_FUNC_MEM */
725 #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8
726
727 #define BNX2X_VF_ID_INVALID 0xFF
728
729 /*
730 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
731 * control by the number of fast-path status blocks supported by the
732 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
733 * status block represents an independent interrupts context that can
734 * serve a regular L2 networking queue. However special L2 queues such
735 * as the FCoE queue do not require a FP-SB and other components like
736 * the CNIC may consume FP-SB reducing the number of possible L2 queues
737 *
738 * If the maximum number of FP-SB available is X then:
739 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
740 * regular L2 queues is Y=X-1
741 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
742 * c. If the FCoE L2 queue is supported the actual number of L2 queues
743 * is Y+1
744 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
745 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
746 * FP interrupt context for the CNIC).
747 * e. The number of HW context (CID count) is always X or X+1 if FCoE
748 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
749 */
750
751 #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
752 #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */
753
754 /*
755 * cid_cnt paramter below refers to the value returned by
756 * 'bnx2x_get_l2_cid_count()' routine
757 */
758
759 /*
760 * The number of FP context allocated by the driver == max number of regular
761 * L2 queues + 1 for the FCoE L2 queue
762 */
763 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
764
765 /*
766 * The number of FP-SB allocated by the driver == max number of regular L2
767 * queues + 1 for the CNIC which also consumes an FP-SB
768 */
769 #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE)
770 #define NUM_IGU_SB_REQUIRED(cid_cnt) \
771 (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
772
773 union cdu_context {
774 struct eth_context eth;
775 char pad[1024];
776 };
777
778 /* CDU host DB constants */
779 #define CDU_ILT_PAGE_SZ_HW 3
780 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
781 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
782
783 #ifdef BCM_CNIC
784 #define CNIC_ISCSI_CID_MAX 256
785 #define CNIC_FCOE_CID_MAX 2048
786 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
787 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
788 #endif
789
790 #define QM_ILT_PAGE_SZ_HW 3
791 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
792 #define QM_CID_ROUND 1024
793
794 #ifdef BCM_CNIC
795 /* TM (timers) host DB constants */
796 #define TM_ILT_PAGE_SZ_HW 2
797 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
798 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
799 #define TM_CONN_NUM 1024
800 #define TM_ILT_SZ (8 * TM_CONN_NUM)
801 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
802
803 /* SRC (Searcher) host DB constants */
804 #define SRC_ILT_PAGE_SZ_HW 3
805 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
806 #define SRC_HASH_BITS 10
807 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
808 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
809 #define SRC_T2_SZ SRC_ILT_SZ
810 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
811 #endif
812
813 #define MAX_DMAE_C 8
814
815 /* DMA memory not used in fastpath */
816 struct bnx2x_slowpath {
817 struct eth_stats_query fw_stats;
818 struct mac_configuration_cmd mac_config;
819 struct mac_configuration_cmd mcast_config;
820 struct mac_configuration_cmd uc_mac_config;
821 struct client_init_ramrod_data client_init_data;
822
823 /* used by dmae command executer */
824 struct dmae_command dmae[MAX_DMAE_C];
825
826 u32 stats_comp;
827 union mac_stats mac_stats;
828 struct nig_stats nig_stats;
829 struct host_port_stats port_stats;
830 struct host_func_stats func_stats;
831 struct host_func_stats func_stats_base;
832
833 u32 wb_comp;
834 u32 wb_data[4];
835 /* pfc configuration for DCBX ramrod */
836 struct flow_control_configuration pfc_config;
837 };
838
839 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
840 #define bnx2x_sp_mapping(bp, var) \
841 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
842
843
844 /* attn group wiring */
845 #define MAX_DYNAMIC_ATTN_GRPS 8
846
847 struct attn_route {
848 u32 sig[5];
849 };
850
851 struct iro {
852 u32 base;
853 u16 m1;
854 u16 m2;
855 u16 m3;
856 u16 size;
857 };
858
859 struct hw_context {
860 union cdu_context *vcxt;
861 dma_addr_t cxt_mapping;
862 size_t size;
863 };
864
865 /* forward */
866 struct bnx2x_ilt;
867
868 typedef enum {
869 BNX2X_RECOVERY_DONE,
870 BNX2X_RECOVERY_INIT,
871 BNX2X_RECOVERY_WAIT,
872 } bnx2x_recovery_state_t;
873
874 /**
875 * Event queue (EQ or event ring) MC hsi
876 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
877 */
878 #define NUM_EQ_PAGES 1
879 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
880 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
881 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
882 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
883 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
884
885 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
886 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
887 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
888
889 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
890 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
891
892 #define BNX2X_EQ_INDEX \
893 (&bp->def_status_blk->sp_sb.\
894 index_values[HC_SP_INDEX_EQ_CONS])
895
896 struct bnx2x {
897 /* Fields used in the tx and intr/napi performance paths
898 * are grouped together in the beginning of the structure
899 */
900 struct bnx2x_fastpath *fp;
901 void __iomem *regview;
902 void __iomem *doorbells;
903 u16 db_size;
904
905 struct net_device *dev;
906 struct pci_dev *pdev;
907
908 struct iro *iro_arr;
909 #define IRO (bp->iro_arr)
910
911 atomic_t intr_sem;
912
913 bnx2x_recovery_state_t recovery_state;
914 int is_leader;
915 struct msix_entry *msix_table;
916 #define INT_MODE_INTx 1
917 #define INT_MODE_MSI 2
918
919 int tx_ring_size;
920
921 u32 rx_csum;
922 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
923 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
924 #define ETH_MIN_PACKET_SIZE 60
925 #define ETH_MAX_PACKET_SIZE 1500
926 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
927
928 /* Max supported alignment is 256 (8 shift) */
929 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
930 L1_CACHE_SHIFT : 8)
931 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
932 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
933
934 struct host_sp_status_block *def_status_blk;
935 #define DEF_SB_IGU_ID 16
936 #define DEF_SB_ID HC_SP_SB_ID
937 __le16 def_idx;
938 __le16 def_att_idx;
939 u32 attn_state;
940 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
941
942 /* slow path ring */
943 struct eth_spe *spq;
944 dma_addr_t spq_mapping;
945 u16 spq_prod_idx;
946 struct eth_spe *spq_prod_bd;
947 struct eth_spe *spq_last_bd;
948 __le16 *dsb_sp_prod;
949 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
950 /* used to synchronize spq accesses */
951 spinlock_t spq_lock;
952
953 /* event queue */
954 union event_ring_elem *eq_ring;
955 dma_addr_t eq_mapping;
956 u16 eq_prod;
957 u16 eq_cons;
958 __le16 *eq_cons_sb;
959 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
960
961 /* Flags for marking that there is a STAT_QUERY or
962 SET_MAC ramrod pending */
963 int stats_pending;
964 int set_mac_pending;
965
966 /* End of fields used in the performance code paths */
967
968 int panic;
969 int msg_enable;
970
971 u32 flags;
972 #define PCIX_FLAG 1
973 #define PCI_32BIT_FLAG 2
974 #define ONE_PORT_FLAG 4
975 #define NO_WOL_FLAG 8
976 #define USING_DAC_FLAG 0x10
977 #define USING_MSIX_FLAG 0x20
978 #define USING_MSI_FLAG 0x40
979
980 #define TPA_ENABLE_FLAG 0x80
981 #define NO_MCP_FLAG 0x100
982 #define DISABLE_MSI_FLAG 0x200
983 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
984 #define MF_FUNC_DIS 0x1000
985 #define FCOE_MACS_SET 0x2000
986 #define NO_FCOE_FLAG 0x4000
987 #define NO_ISCSI_OOO_FLAG 0x8000
988 #define NO_ISCSI_FLAG 0x10000
989
990 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
991 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
992 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
993
994 int pf_num; /* absolute PF number */
995 int pfid; /* per-path PF number */
996 int base_fw_ndsb;
997 #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \
998 0 : (bp->pf_num & 1))
999 #define BP_PORT(bp) (bp->pfid & 1)
1000 #define BP_FUNC(bp) (bp->pfid)
1001 #define BP_ABS_FUNC(bp) (bp->pf_num)
1002 #define BP_E1HVN(bp) (bp->pfid >> 1)
1003 #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \
1004 0 : BP_E1HVN(bp))
1005 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
1006 #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\
1007 BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1))
1008
1009 #ifdef BCM_CNIC
1010 #define BCM_CNIC_CID_START 16
1011 #define BCM_ISCSI_ETH_CL_ID 17
1012 #endif
1013
1014 int pm_cap;
1015 int pcie_cap;
1016 int mrrs;
1017
1018 struct delayed_work sp_task;
1019 struct delayed_work reset_task;
1020 struct timer_list timer;
1021 int current_interval;
1022
1023 u16 fw_seq;
1024 u16 fw_drv_pulse_wr_seq;
1025 u32 func_stx;
1026
1027 struct link_params link_params;
1028 struct link_vars link_vars;
1029 struct mdio_if_info mdio;
1030
1031 struct bnx2x_common common;
1032 struct bnx2x_port port;
1033
1034 struct cmng_struct_per_port cmng;
1035 u32 vn_weight_sum;
1036
1037 u32 mf_config[E1HVN_MAX];
1038 u32 mf2_config[E2_FUNC_MAX];
1039 u16 mf_ov;
1040 u8 mf_mode;
1041 #define IS_MF(bp) (bp->mf_mode != 0)
1042 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1043 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1044
1045 u8 wol;
1046
1047 int rx_ring_size;
1048
1049 u16 tx_quick_cons_trip_int;
1050 u16 tx_quick_cons_trip;
1051 u16 tx_ticks_int;
1052 u16 tx_ticks;
1053
1054 u16 rx_quick_cons_trip_int;
1055 u16 rx_quick_cons_trip;
1056 u16 rx_ticks_int;
1057 u16 rx_ticks;
1058 /* Maximal coalescing timeout in us */
1059 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1060
1061 u32 lin_cnt;
1062
1063 int state;
1064 #define BNX2X_STATE_CLOSED 0
1065 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1066 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1067 #define BNX2X_STATE_OPEN 0x3000
1068 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1069 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1070 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
1071 #define BNX2X_STATE_FUNC_STARTED 0x7000
1072 #define BNX2X_STATE_DIAG 0xe000
1073 #define BNX2X_STATE_ERROR 0xf000
1074
1075 int multi_mode;
1076 int num_queues;
1077 int disable_tpa;
1078 int int_mode;
1079 u32 *rx_indir_table;
1080
1081 struct tstorm_eth_mac_filter_config mac_filters;
1082 #define BNX2X_ACCEPT_NONE 0x0000
1083 #define BNX2X_ACCEPT_UNICAST 0x0001
1084 #define BNX2X_ACCEPT_MULTICAST 0x0002
1085 #define BNX2X_ACCEPT_ALL_UNICAST 0x0004
1086 #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
1087 #define BNX2X_ACCEPT_BROADCAST 0x0010
1088 #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020
1089 #define BNX2X_PROMISCUOUS_MODE 0x10000
1090
1091 u32 rx_mode;
1092 #define BNX2X_RX_MODE_NONE 0
1093 #define BNX2X_RX_MODE_NORMAL 1
1094 #define BNX2X_RX_MODE_ALLMULTI 2
1095 #define BNX2X_RX_MODE_PROMISC 3
1096 #define BNX2X_MAX_MULTICAST 64
1097 #define BNX2X_MAX_EMUL_MULTI 16
1098
1099 u8 igu_dsb_id;
1100 u8 igu_base_sb;
1101 u8 igu_sb_cnt;
1102 dma_addr_t def_status_blk_mapping;
1103
1104 struct bnx2x_slowpath *slowpath;
1105 dma_addr_t slowpath_mapping;
1106 struct hw_context context;
1107
1108 struct bnx2x_ilt *ilt;
1109 #define BP_ILT(bp) ((bp)->ilt)
1110 #define ILT_MAX_LINES 128
1111
1112 int l2_cid_count;
1113 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1114 ILT_PAGE_CIDS))
1115 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1116
1117 int qm_cid_count;
1118
1119 int dropless_fc;
1120
1121 #ifdef BCM_CNIC
1122 u32 cnic_flags;
1123 #define BNX2X_CNIC_FLAG_MAC_SET 1
1124 void *t2;
1125 dma_addr_t t2_mapping;
1126 struct cnic_ops __rcu *cnic_ops;
1127 void *cnic_data;
1128 u32 cnic_tag;
1129 struct cnic_eth_dev cnic_eth_dev;
1130 union host_hc_status_block cnic_sb;
1131 dma_addr_t cnic_sb_mapping;
1132 #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
1133 #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
1134 struct eth_spe *cnic_kwq;
1135 struct eth_spe *cnic_kwq_prod;
1136 struct eth_spe *cnic_kwq_cons;
1137 struct eth_spe *cnic_kwq_last;
1138 u16 cnic_kwq_pending;
1139 u16 cnic_spq_pending;
1140 struct mutex cnic_mutex;
1141 u8 fip_mac[ETH_ALEN];
1142 #endif
1143
1144 int dmae_ready;
1145 /* used to synchronize dmae accesses */
1146 spinlock_t dmae_lock;
1147
1148 /* used to protect the FW mail box */
1149 struct mutex fw_mb_mutex;
1150
1151 /* used to synchronize stats collecting */
1152 int stats_state;
1153
1154 /* used for synchronization of concurrent threads statistics handling */
1155 spinlock_t stats_lock;
1156
1157 /* used by dmae command loader */
1158 struct dmae_command stats_dmae;
1159 int executer_idx;
1160
1161 u16 stats_counter;
1162 struct bnx2x_eth_stats eth_stats;
1163
1164 struct z_stream_s *strm;
1165 void *gunzip_buf;
1166 dma_addr_t gunzip_mapping;
1167 int gunzip_outlen;
1168 #define FW_BUF_SIZE 0x8000
1169 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1170 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1171 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1172
1173 struct raw_op *init_ops;
1174 /* Init blocks offsets inside init_ops */
1175 u16 *init_ops_offsets;
1176 /* Data blob - has 32 bit granularity */
1177 u32 *init_data;
1178 /* Zipped PRAM blobs - raw data */
1179 const u8 *tsem_int_table_data;
1180 const u8 *tsem_pram_data;
1181 const u8 *usem_int_table_data;
1182 const u8 *usem_pram_data;
1183 const u8 *xsem_int_table_data;
1184 const u8 *xsem_pram_data;
1185 const u8 *csem_int_table_data;
1186 const u8 *csem_pram_data;
1187 #define INIT_OPS(bp) (bp->init_ops)
1188 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1189 #define INIT_DATA(bp) (bp->init_data)
1190 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1191 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1192 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1193 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1194 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1195 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1196 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1197 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1198
1199 char fw_ver[32];
1200 const struct firmware *firmware;
1201 /* LLDP params */
1202 struct bnx2x_config_lldp_params lldp_config_params;
1203
1204 /* DCB support on/off */
1205 u16 dcb_state;
1206 #define BNX2X_DCB_STATE_OFF 0
1207 #define BNX2X_DCB_STATE_ON 1
1208
1209 /* DCBX engine mode */
1210 int dcbx_enabled;
1211 #define BNX2X_DCBX_ENABLED_OFF 0
1212 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1213 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1214 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1215
1216 bool dcbx_mode_uset;
1217
1218 struct bnx2x_config_dcbx_params dcbx_config_params;
1219
1220 struct bnx2x_dcbx_port_params dcbx_port_params;
1221 int dcb_version;
1222
1223 /* DCBX Negotiation results */
1224 struct dcbx_features dcbx_local_feat;
1225 u32 dcbx_error;
1226 u32 pending_max;
1227 };
1228
1229 /**
1230 * Init queue/func interface
1231 */
1232 /* queue init flags */
1233 #define QUEUE_FLG_TPA 0x0001
1234 #define QUEUE_FLG_CACHE_ALIGN 0x0002
1235 #define QUEUE_FLG_STATS 0x0004
1236 #define QUEUE_FLG_OV 0x0008
1237 #define QUEUE_FLG_VLAN 0x0010
1238 #define QUEUE_FLG_COS 0x0020
1239 #define QUEUE_FLG_HC 0x0040
1240 #define QUEUE_FLG_DHC 0x0080
1241 #define QUEUE_FLG_OOO 0x0100
1242
1243 #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
1244 #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
1245 #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
1246 #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
1247
1248
1249
1250 /* rss capabilities */
1251 #define RSS_IPV4_CAP 0x0001
1252 #define RSS_IPV4_TCP_CAP 0x0002
1253 #define RSS_IPV6_CAP 0x0004
1254 #define RSS_IPV6_TCP_CAP 0x0008
1255
1256 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1257 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
1258
1259 /* ethtool statistics are displayed for all regular ethernet queues and the
1260 * fcoe L2 queue if not disabled
1261 */
1262 #define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \
1263 (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE))
1264
1265 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1266
1267 #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
1268
1269 #define RSS_IPV4_CAP_MASK \
1270 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1271
1272 #define RSS_IPV4_TCP_CAP_MASK \
1273 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1274
1275 #define RSS_IPV6_CAP_MASK \
1276 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1277
1278 #define RSS_IPV6_TCP_CAP_MASK \
1279 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1280
1281 /* func init flags */
1282 #define FUNC_FLG_STATS 0x0001
1283 #define FUNC_FLG_TPA 0x0002
1284 #define FUNC_FLG_SPQ 0x0004
1285 #define FUNC_FLG_LEADING 0x0008 /* PF only */
1286
1287 struct rxq_pause_params {
1288 u16 bd_th_lo;
1289 u16 bd_th_hi;
1290 u16 rcq_th_lo;
1291 u16 rcq_th_hi;
1292 u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */
1293 u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */
1294 u16 pri_map;
1295 };
1296
1297 struct bnx2x_rxq_init_params {
1298 /* cxt*/
1299 struct eth_context *cxt;
1300
1301 /* dma */
1302 dma_addr_t dscr_map;
1303 dma_addr_t sge_map;
1304 dma_addr_t rcq_map;
1305 dma_addr_t rcq_np_map;
1306
1307 u16 flags;
1308 u16 drop_flags;
1309 u16 mtu;
1310 u16 buf_sz;
1311 u16 fw_sb_id;
1312 u16 cl_id;
1313 u16 spcl_id;
1314 u16 cl_qzone_id;
1315
1316 /* valid iff QUEUE_FLG_STATS */
1317 u16 stat_id;
1318
1319 /* valid iff QUEUE_FLG_TPA */
1320 u16 tpa_agg_sz;
1321 u16 sge_buf_sz;
1322 u16 max_sges_pkt;
1323
1324 /* valid iff QUEUE_FLG_CACHE_ALIGN */
1325 u8 cache_line_log;
1326
1327 u8 sb_cq_index;
1328 u32 cid;
1329
1330 /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
1331 u32 hc_rate;
1332 };
1333
1334 struct bnx2x_txq_init_params {
1335 /* cxt*/
1336 struct eth_context *cxt;
1337
1338 /* dma */
1339 dma_addr_t dscr_map;
1340
1341 u16 flags;
1342 u16 fw_sb_id;
1343 u8 sb_cq_index;
1344 u8 cos; /* valid iff QUEUE_FLG_COS */
1345 u16 stat_id; /* valid iff QUEUE_FLG_STATS */
1346 u16 traffic_type;
1347 u32 cid;
1348 u16 hc_rate; /* desired interrupts per sec.*/
1349 /* valid iff QUEUE_FLG_HC */
1350
1351 };
1352
1353 struct bnx2x_client_ramrod_params {
1354 int *pstate;
1355 int state;
1356 u16 index;
1357 u16 cl_id;
1358 u32 cid;
1359 u8 poll;
1360 #define CLIENT_IS_FCOE 0x01
1361 #define CLIENT_IS_LEADING_RSS 0x02
1362 u8 flags;
1363 };
1364
1365 struct bnx2x_client_init_params {
1366 struct rxq_pause_params pause;
1367 struct bnx2x_rxq_init_params rxq_params;
1368 struct bnx2x_txq_init_params txq_params;
1369 struct bnx2x_client_ramrod_params ramrod_params;
1370 };
1371
1372 struct bnx2x_rss_params {
1373 int mode;
1374 u16 cap;
1375 u16 result_mask;
1376 };
1377
1378 struct bnx2x_func_init_params {
1379
1380 /* rss */
1381 struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */
1382
1383 /* dma */
1384 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1385 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1386
1387 u16 func_flgs;
1388 u16 func_id; /* abs fid */
1389 u16 pf_id;
1390 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1391 };
1392
1393 #define for_each_eth_queue(bp, var) \
1394 for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1395
1396 #define for_each_nondefault_eth_queue(bp, var) \
1397 for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
1398
1399 #define for_each_napi_queue(bp, var) \
1400 for (var = 0; \
1401 var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
1402 if (skip_queue(bp, var)) \
1403 continue; \
1404 else
1405
1406 #define for_each_queue(bp, var) \
1407 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1408 if (skip_queue(bp, var)) \
1409 continue; \
1410 else
1411
1412 #define for_each_rx_queue(bp, var) \
1413 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1414 if (skip_rx_queue(bp, var)) \
1415 continue; \
1416 else
1417
1418 #define for_each_tx_queue(bp, var) \
1419 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
1420 if (skip_tx_queue(bp, var)) \
1421 continue; \
1422 else
1423
1424 #define for_each_nondefault_queue(bp, var) \
1425 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
1426 if (skip_queue(bp, var)) \
1427 continue; \
1428 else
1429
1430 /* skip rx queue
1431 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1432 */
1433 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1434
1435 /* skip tx queue
1436 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1437 */
1438 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1439
1440 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1441
1442 #define WAIT_RAMROD_POLL 0x01
1443 #define WAIT_RAMROD_COMMON 0x02
1444
1445 /* dmae */
1446 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1447 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1448 u32 len32);
1449 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1450 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1451 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1452 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1453 bool with_comp, u8 comp_type);
1454
1455 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1456 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1457 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1458 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
1459
1460 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1461 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1462 u32 data_hi, u32 data_lo, int common);
1463
1464 /* Clears multicast and unicast list configuration in the chip. */
1465 void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp);
1466 void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp);
1467 void bnx2x_invalidate_uc_list(struct bnx2x *bp);
1468
1469 void bnx2x_update_coalesce(struct bnx2x *bp);
1470 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1471
1472 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1473 int wait)
1474 {
1475 u32 val;
1476
1477 do {
1478 val = REG_RD(bp, reg);
1479 if (val == expected)
1480 break;
1481 ms -= wait;
1482 msleep(wait);
1483
1484 } while (ms > 0);
1485
1486 return val;
1487 }
1488
1489 #define BNX2X_ILT_ZALLOC(x, y, size) \
1490 do { \
1491 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1492 if (x) \
1493 memset(x, 0, size); \
1494 } while (0)
1495
1496 #define BNX2X_ILT_FREE(x, y, size) \
1497 do { \
1498 if (x) { \
1499 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1500 x = NULL; \
1501 y = 0; \
1502 } \
1503 } while (0)
1504
1505 #define ILOG2(x) (ilog2((x)))
1506
1507 #define ILT_NUM_PAGE_ENTRIES (3072)
1508 /* In 57710/11 we use whole table since we have 8 func
1509 * In 57712 we have only 4 func, but use same size per func, then only half of
1510 * the table in use
1511 */
1512 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1513
1514 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1515 /*
1516 * the phys address is shifted right 12 bits and has an added
1517 * 1=valid bit added to the 53rd bit
1518 * then since this is a wide register(TM)
1519 * we split it into two 32 bit writes
1520 */
1521 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1522 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1523
1524 /* load/unload mode */
1525 #define LOAD_NORMAL 0
1526 #define LOAD_OPEN 1
1527 #define LOAD_DIAG 2
1528 #define UNLOAD_NORMAL 0
1529 #define UNLOAD_CLOSE 1
1530 #define UNLOAD_RECOVERY 2
1531
1532
1533 /* DMAE command defines */
1534 #define DMAE_TIMEOUT -1
1535 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1536 #define DMAE_NOT_RDY -3
1537 #define DMAE_PCI_ERR_FLAG 0x80000000
1538
1539 #define DMAE_SRC_PCI 0
1540 #define DMAE_SRC_GRC 1
1541
1542 #define DMAE_DST_NONE 0
1543 #define DMAE_DST_PCI 1
1544 #define DMAE_DST_GRC 2
1545
1546 #define DMAE_COMP_PCI 0
1547 #define DMAE_COMP_GRC 1
1548
1549 /* E2 and onward - PCI error handling in the completion */
1550
1551 #define DMAE_COMP_REGULAR 0
1552 #define DMAE_COM_SET_ERR 1
1553
1554 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1555 DMAE_COMMAND_SRC_SHIFT)
1556 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1557 DMAE_COMMAND_SRC_SHIFT)
1558
1559 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1560 DMAE_COMMAND_DST_SHIFT)
1561 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1562 DMAE_COMMAND_DST_SHIFT)
1563
1564 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1565 DMAE_COMMAND_C_DST_SHIFT)
1566 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1567 DMAE_COMMAND_C_DST_SHIFT)
1568
1569 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1570
1571 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1572 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1573 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1574 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1575
1576 #define DMAE_CMD_PORT_0 0
1577 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1578
1579 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1580 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1581 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1582
1583 #define DMAE_SRC_PF 0
1584 #define DMAE_SRC_VF 1
1585
1586 #define DMAE_DST_PF 0
1587 #define DMAE_DST_VF 1
1588
1589 #define DMAE_C_SRC 0
1590 #define DMAE_C_DST 1
1591
1592 #define DMAE_LEN32_RD_MAX 0x80
1593 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1594
1595 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1596 indicates eror */
1597
1598 #define MAX_DMAE_C_PER_PORT 8
1599 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1600 BP_E1HVN(bp))
1601 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1602 E1HVN_MAX)
1603
1604 /* PCIE link and speed */
1605 #define PCICFG_LINK_WIDTH 0x1f00000
1606 #define PCICFG_LINK_WIDTH_SHIFT 20
1607 #define PCICFG_LINK_SPEED 0xf0000
1608 #define PCICFG_LINK_SPEED_SHIFT 16
1609
1610
1611 #define BNX2X_NUM_TESTS 7
1612
1613 #define BNX2X_PHY_LOOPBACK 0
1614 #define BNX2X_MAC_LOOPBACK 1
1615 #define BNX2X_PHY_LOOPBACK_FAILED 1
1616 #define BNX2X_MAC_LOOPBACK_FAILED 2
1617 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1618 BNX2X_PHY_LOOPBACK_FAILED)
1619
1620
1621 #define STROM_ASSERT_ARRAY_SIZE 50
1622
1623
1624 /* must be used on a CID before placing it on a HW ring */
1625 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1626 (BP_E1HVN(bp) << 17) | (x))
1627
1628 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1629 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1630
1631
1632 #define BNX2X_BTR 4
1633 #define MAX_SPQ_PENDING 8
1634
1635 /* CMNG constants, as derived from system spec calculations */
1636 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1637 #define DEF_MIN_RATE 100
1638 /* resolution of the rate shaping timer - 400 usec */
1639 #define RS_PERIODIC_TIMEOUT_USEC 400
1640 /* number of bytes in single QM arbitration cycle -
1641 * coefficient for calculating the fairness timer */
1642 #define QM_ARB_BYTES 160000
1643 /* resolution of Min algorithm 1:100 */
1644 #define MIN_RES 100
1645 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1646 #define MIN_ABOVE_THRESH 32768
1647 /* Fairness algorithm integration time coefficient -
1648 * for calculating the actual Tfair */
1649 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1650 /* Memory of fairness algorithm . 2 cycles */
1651 #define FAIR_MEM 2
1652
1653
1654 #define ATTN_NIG_FOR_FUNC (1L << 8)
1655 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1656 #define GPIO_2_FUNC (1L << 10)
1657 #define GPIO_3_FUNC (1L << 11)
1658 #define GPIO_4_FUNC (1L << 12)
1659 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1660 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1661 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1662 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1663 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1664 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1665
1666 #define ATTN_HARD_WIRED_MASK 0xff00
1667 #define ATTENTION_ID 4
1668
1669
1670 /* stuff added to make the code fit 80Col */
1671
1672 #define BNX2X_PMF_LINK_ASSERT \
1673 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1674
1675 #define BNX2X_MC_ASSERT_BITS \
1676 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1677 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1678 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1679 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1680
1681 #define BNX2X_MCP_ASSERT \
1682 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1683
1684 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1685 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1686 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1687 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1688 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1689 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1690 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1691
1692 #define HW_INTERRUT_ASSERT_SET_0 \
1693 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1694 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1695 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1696 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1697 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1698 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1699 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1700 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1701 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1702 #define HW_INTERRUT_ASSERT_SET_1 \
1703 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1704 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1705 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1706 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1707 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1708 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1709 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1710 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1711 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1712 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1713 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1714 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1715 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1716 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1717 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1718 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1719 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1720 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1721 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1722 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1723 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1724 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1725 #define HW_INTERRUT_ASSERT_SET_2 \
1726 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1727 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1728 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1729 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1730 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1731 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1732 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1733 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1734 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1735 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1736 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1737 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1738
1739 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1740 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1741 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1742 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1743
1744 #define RSS_FLAGS(bp) \
1745 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1746 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1747 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1748 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1749 (bp->multi_mode << \
1750 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1751 #define MULTI_MASK 0x7f
1752
1753 #define BNX2X_SP_DSB_INDEX \
1754 (&bp->def_status_blk->sp_sb.\
1755 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1756
1757 #define SET_FLAG(value, mask, flag) \
1758 do {\
1759 (value) &= ~(mask);\
1760 (value) |= ((flag) << (mask##_SHIFT));\
1761 } while (0)
1762
1763 #define GET_FLAG(value, mask) \
1764 (((value) &= (mask)) >> (mask##_SHIFT))
1765
1766 #define GET_FIELD(value, fname) \
1767 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
1768
1769 #define CAM_IS_INVALID(x) \
1770 (GET_FLAG(x.flags, \
1771 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1772 (T_ETH_MAC_COMMAND_INVALIDATE))
1773
1774 /* Number of u32 elements in MC hash array */
1775 #define MC_HASH_SIZE 8
1776 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1777 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1778
1779
1780 #ifndef PXP2_REG_PXP2_INT_STS
1781 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1782 #endif
1783
1784 #ifndef ETH_MAX_RX_CLIENTS_E2
1785 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
1786 #endif
1787
1788 #define BNX2X_VPD_LEN 128
1789 #define VENDOR_ID_LEN 4
1790
1791 /* Congestion management fairness mode */
1792 #define CMNG_FNS_NONE 0
1793 #define CMNG_FNS_MINMAX 1
1794
1795 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1796 #define HC_SEG_ACCESS_ATTN 4
1797 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1798
1799 #ifdef BNX2X_MAIN
1800 #define BNX2X_EXTERN
1801 #else
1802 #define BNX2X_EXTERN extern
1803 #endif
1804
1805 BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */
1806
1807 extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
1808 void bnx2x_push_indir_table(struct bnx2x *bp);
1809
1810 #endif /* bnx2x.h */
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