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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / net / e1000e / ich8lan.c
blobce1dbfdca112e3533ab89ad7779c12665b9fbe8e
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
57 */
58
59 #include "e1000.h"
60
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
67
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
77
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
80
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
92
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
102
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114 #define E1000_ICH_RAR_ENTRIES 7
115
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
135
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
138
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142
143 /* EMI Registers */
144 #define I82579_EMI_ADDR 0x10
145 #define I82579_EMI_DATA 0x11
146 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
147
148 /* Strapping Option Register - RO */
149 #define E1000_STRAP 0x0000C
150 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
152
153 /* OEM Bits Phy Register */
154 #define HV_OEM_BITS PHY_REG(768, 25)
155 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
156 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
158
159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
160 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
161
162 /* KMRN Mode Control */
163 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
164 #define HV_KMRN_MDIO_SLOW 0x0400
165
166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
167 /* Offset 04h HSFSTS */
168 union ich8_hws_flash_status {
169 struct ich8_hsfsts {
170 u16 flcdone :1; /* bit 0 Flash Cycle Done */
171 u16 flcerr :1; /* bit 1 Flash Cycle Error */
172 u16 dael :1; /* bit 2 Direct Access error Log */
173 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
174 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
175 u16 reserved1 :2; /* bit 13:6 Reserved */
176 u16 reserved2 :6; /* bit 13:6 Reserved */
177 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
178 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
179 } hsf_status;
180 u16 regval;
181 };
182
183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
184 /* Offset 06h FLCTL */
185 union ich8_hws_flash_ctrl {
186 struct ich8_hsflctl {
187 u16 flcgo :1; /* 0 Flash Cycle Go */
188 u16 flcycle :2; /* 2:1 Flash Cycle */
189 u16 reserved :5; /* 7:3 Reserved */
190 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
191 u16 flockdn :6; /* 15:10 Reserved */
192 } hsf_ctrl;
193 u16 regval;
194 };
195
196 /* ICH Flash Region Access Permissions */
197 union ich8_hws_flash_regacc {
198 struct ich8_flracc {
199 u32 grra :8; /* 0:7 GbE region Read Access */
200 u32 grwa :8; /* 8:15 GbE region Write Access */
201 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
202 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
203 } hsf_flregacc;
204 u16 regval;
205 };
206
207 /* ICH Flash Protected Region */
208 union ich8_flash_protected_range {
209 struct ich8_pr {
210 u32 base:13; /* 0:12 Protected Range Base */
211 u32 reserved1:2; /* 13:14 Reserved */
212 u32 rpe:1; /* 15 Read Protection Enable */
213 u32 limit:13; /* 16:28 Protected Range Limit */
214 u32 reserved2:2; /* 29:30 Reserved */
215 u32 wpe:1; /* 31 Write Protection Enable */
216 } range;
217 u32 regval;
218 };
219
220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
225 u32 offset, u8 byte);
226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
227 u8 *data);
228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
229 u16 *data);
230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
231 u8 size, u16 *data);
232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
246 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
252
253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
254 {
255 return readw(hw->flash_address + reg);
256 }
257
258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
259 {
260 return readl(hw->flash_address + reg);
261 }
262
263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
264 {
265 writew(val, hw->flash_address + reg);
266 }
267
268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
269 {
270 writel(val, hw->flash_address + reg);
271 }
272
273 #define er16flash(reg) __er16flash(hw, (reg))
274 #define er32flash(reg) __er32flash(hw, (reg))
275 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
276 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
277
278 /**
279 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
280 * @hw: pointer to the HW structure
281 *
282 * Initialize family-specific PHY parameters and function pointers.
283 **/
284 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
285 {
286 struct e1000_phy_info *phy = &hw->phy;
287 u32 ctrl, fwsm;
288 s32 ret_val = 0;
289
290 phy->addr = 1;
291 phy->reset_delay_us = 100;
292
293 phy->ops.read_reg = e1000_read_phy_reg_hv;
294 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
295 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
296 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
297 phy->ops.write_reg = e1000_write_phy_reg_hv;
298 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
299 phy->ops.power_up = e1000_power_up_phy_copper;
300 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
301 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
302
303 /*
304 * The MAC-PHY interconnect may still be in SMBus mode
305 * after Sx->S0. If the manageability engine (ME) is
306 * disabled, then toggle the LANPHYPC Value bit to force
307 * the interconnect to PCIe mode.
308 */
309 fwsm = er32(FWSM);
310 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
311 ctrl = er32(CTRL);
312 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
313 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
314 ew32(CTRL, ctrl);
315 udelay(10);
316 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
317 ew32(CTRL, ctrl);
318 msleep(50);
319
320 /*
321 * Gate automatic PHY configuration by hardware on
322 * non-managed 82579
323 */
324 if (hw->mac.type == e1000_pch2lan)
325 e1000_gate_hw_phy_config_ich8lan(hw, true);
326 }
327
328 /*
329 * Reset the PHY before any access to it. Doing so, ensures that
330 * the PHY is in a known good state before we read/write PHY registers.
331 * The generic reset is sufficient here, because we haven't determined
332 * the PHY type yet.
333 */
334 ret_val = e1000e_phy_hw_reset_generic(hw);
335 if (ret_val)
336 goto out;
337
338 /* Ungate automatic PHY configuration on non-managed 82579 */
339 if ((hw->mac.type == e1000_pch2lan) &&
340 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
341 msleep(10);
342 e1000_gate_hw_phy_config_ich8lan(hw, false);
343 }
344
345 phy->id = e1000_phy_unknown;
346 switch (hw->mac.type) {
347 default:
348 ret_val = e1000e_get_phy_id(hw);
349 if (ret_val)
350 goto out;
351 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
352 break;
353 /* fall-through */
354 case e1000_pch2lan:
355 /*
356 * In case the PHY needs to be in mdio slow mode,
357 * set slow mode and try to get the PHY id again.
358 */
359 ret_val = e1000_set_mdio_slow_mode_hv(hw);
360 if (ret_val)
361 goto out;
362 ret_val = e1000e_get_phy_id(hw);
363 if (ret_val)
364 goto out;
365 break;
366 }
367 phy->type = e1000e_get_phy_type_from_id(phy->id);
368
369 switch (phy->type) {
370 case e1000_phy_82577:
371 case e1000_phy_82579:
372 phy->ops.check_polarity = e1000_check_polarity_82577;
373 phy->ops.force_speed_duplex =
374 e1000_phy_force_speed_duplex_82577;
375 phy->ops.get_cable_length = e1000_get_cable_length_82577;
376 phy->ops.get_info = e1000_get_phy_info_82577;
377 phy->ops.commit = e1000e_phy_sw_reset;
378 break;
379 case e1000_phy_82578:
380 phy->ops.check_polarity = e1000_check_polarity_m88;
381 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
382 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
383 phy->ops.get_info = e1000e_get_phy_info_m88;
384 break;
385 default:
386 ret_val = -E1000_ERR_PHY;
387 break;
388 }
389
390 out:
391 return ret_val;
392 }
393
394 /**
395 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
396 * @hw: pointer to the HW structure
397 *
398 * Initialize family-specific PHY parameters and function pointers.
399 **/
400 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
401 {
402 struct e1000_phy_info *phy = &hw->phy;
403 s32 ret_val;
404 u16 i = 0;
405
406 phy->addr = 1;
407 phy->reset_delay_us = 100;
408
409 phy->ops.power_up = e1000_power_up_phy_copper;
410 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
411
412 /*
413 * We may need to do this twice - once for IGP and if that fails,
414 * we'll set BM func pointers and try again
415 */
416 ret_val = e1000e_determine_phy_address(hw);
417 if (ret_val) {
418 phy->ops.write_reg = e1000e_write_phy_reg_bm;
419 phy->ops.read_reg = e1000e_read_phy_reg_bm;
420 ret_val = e1000e_determine_phy_address(hw);
421 if (ret_val) {
422 e_dbg("Cannot determine PHY addr. Erroring out\n");
423 return ret_val;
424 }
425 }
426
427 phy->id = 0;
428 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
429 (i++ < 100)) {
430 msleep(1);
431 ret_val = e1000e_get_phy_id(hw);
432 if (ret_val)
433 return ret_val;
434 }
435
436 /* Verify phy id */
437 switch (phy->id) {
438 case IGP03E1000_E_PHY_ID:
439 phy->type = e1000_phy_igp_3;
440 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
441 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
442 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
443 phy->ops.get_info = e1000e_get_phy_info_igp;
444 phy->ops.check_polarity = e1000_check_polarity_igp;
445 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
446 break;
447 case IFE_E_PHY_ID:
448 case IFE_PLUS_E_PHY_ID:
449 case IFE_C_E_PHY_ID:
450 phy->type = e1000_phy_ife;
451 phy->autoneg_mask = E1000_ALL_NOT_GIG;
452 phy->ops.get_info = e1000_get_phy_info_ife;
453 phy->ops.check_polarity = e1000_check_polarity_ife;
454 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
455 break;
456 case BME1000_E_PHY_ID:
457 phy->type = e1000_phy_bm;
458 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
459 phy->ops.read_reg = e1000e_read_phy_reg_bm;
460 phy->ops.write_reg = e1000e_write_phy_reg_bm;
461 phy->ops.commit = e1000e_phy_sw_reset;
462 phy->ops.get_info = e1000e_get_phy_info_m88;
463 phy->ops.check_polarity = e1000_check_polarity_m88;
464 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
465 break;
466 default:
467 return -E1000_ERR_PHY;
468 break;
469 }
470
471 return 0;
472 }
473
474 /**
475 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
476 * @hw: pointer to the HW structure
477 *
478 * Initialize family-specific NVM parameters and function
479 * pointers.
480 **/
481 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
482 {
483 struct e1000_nvm_info *nvm = &hw->nvm;
484 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
485 u32 gfpreg, sector_base_addr, sector_end_addr;
486 u16 i;
487
488 /* Can't read flash registers if the register set isn't mapped. */
489 if (!hw->flash_address) {
490 e_dbg("ERROR: Flash registers not mapped\n");
491 return -E1000_ERR_CONFIG;
492 }
493
494 nvm->type = e1000_nvm_flash_sw;
495
496 gfpreg = er32flash(ICH_FLASH_GFPREG);
497
498 /*
499 * sector_X_addr is a "sector"-aligned address (4096 bytes)
500 * Add 1 to sector_end_addr since this sector is included in
501 * the overall size.
502 */
503 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
504 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
505
506 /* flash_base_addr is byte-aligned */
507 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
508
509 /*
510 * find total size of the NVM, then cut in half since the total
511 * size represents two separate NVM banks.
512 */
513 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
514 << FLASH_SECTOR_ADDR_SHIFT;
515 nvm->flash_bank_size /= 2;
516 /* Adjust to word count */
517 nvm->flash_bank_size /= sizeof(u16);
518
519 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
520
521 /* Clear shadow ram */
522 for (i = 0; i < nvm->word_size; i++) {
523 dev_spec->shadow_ram[i].modified = false;
524 dev_spec->shadow_ram[i].value = 0xFFFF;
525 }
526
527 return 0;
528 }
529
530 /**
531 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
532 * @hw: pointer to the HW structure
533 *
534 * Initialize family-specific MAC parameters and function
535 * pointers.
536 **/
537 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
538 {
539 struct e1000_hw *hw = &adapter->hw;
540 struct e1000_mac_info *mac = &hw->mac;
541
542 /* Set media type function pointer */
543 hw->phy.media_type = e1000_media_type_copper;
544
545 /* Set mta register count */
546 mac->mta_reg_count = 32;
547 /* Set rar entry count */
548 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
549 if (mac->type == e1000_ich8lan)
550 mac->rar_entry_count--;
551 /* FWSM register */
552 mac->has_fwsm = true;
553 /* ARC subsystem not supported */
554 mac->arc_subsystem_valid = false;
555 /* Adaptive IFS supported */
556 mac->adaptive_ifs = true;
557
558 /* LED operations */
559 switch (mac->type) {
560 case e1000_ich8lan:
561 case e1000_ich9lan:
562 case e1000_ich10lan:
563 /* check management mode */
564 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
565 /* ID LED init */
566 mac->ops.id_led_init = e1000e_id_led_init;
567 /* setup LED */
568 mac->ops.setup_led = e1000e_setup_led_generic;
569 /* cleanup LED */
570 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
571 /* turn on/off LED */
572 mac->ops.led_on = e1000_led_on_ich8lan;
573 mac->ops.led_off = e1000_led_off_ich8lan;
574 break;
575 case e1000_pchlan:
576 case e1000_pch2lan:
577 /* check management mode */
578 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
579 /* ID LED init */
580 mac->ops.id_led_init = e1000_id_led_init_pchlan;
581 /* setup LED */
582 mac->ops.setup_led = e1000_setup_led_pchlan;
583 /* cleanup LED */
584 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
585 /* turn on/off LED */
586 mac->ops.led_on = e1000_led_on_pchlan;
587 mac->ops.led_off = e1000_led_off_pchlan;
588 break;
589 default:
590 break;
591 }
592
593 /* Enable PCS Lock-loss workaround for ICH8 */
594 if (mac->type == e1000_ich8lan)
595 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
596
597 /* Gate automatic PHY configuration by hardware on managed 82579 */
598 if ((mac->type == e1000_pch2lan) &&
599 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
600 e1000_gate_hw_phy_config_ich8lan(hw, true);
601
602 return 0;
603 }
604
605 /**
606 * e1000_set_eee_pchlan - Enable/disable EEE support
607 * @hw: pointer to the HW structure
608 *
609 * Enable/disable EEE based on setting in dev_spec structure. The bits in
610 * the LPI Control register will remain set only if/when link is up.
611 **/
612 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
613 {
614 s32 ret_val = 0;
615 u16 phy_reg;
616
617 if (hw->phy.type != e1000_phy_82579)
618 goto out;
619
620 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
621 if (ret_val)
622 goto out;
623
624 if (hw->dev_spec.ich8lan.eee_disable)
625 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
626 else
627 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
628
629 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
630 out:
631 return ret_val;
632 }
633
634 /**
635 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
636 * @hw: pointer to the HW structure
637 *
638 * Checks to see of the link status of the hardware has changed. If a
639 * change in link status has been detected, then we read the PHY registers
640 * to get the current speed/duplex if link exists.
641 **/
642 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
643 {
644 struct e1000_mac_info *mac = &hw->mac;
645 s32 ret_val;
646 bool link;
647
648 /*
649 * We only want to go out to the PHY registers to see if Auto-Neg
650 * has completed and/or if our link status has changed. The
651 * get_link_status flag is set upon receiving a Link Status
652 * Change or Rx Sequence Error interrupt.
653 */
654 if (!mac->get_link_status) {
655 ret_val = 0;
656 goto out;
657 }
658
659 /*
660 * First we want to see if the MII Status Register reports
661 * link. If so, then we want to get the current speed/duplex
662 * of the PHY.
663 */
664 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
665 if (ret_val)
666 goto out;
667
668 if (hw->mac.type == e1000_pchlan) {
669 ret_val = e1000_k1_gig_workaround_hv(hw, link);
670 if (ret_val)
671 goto out;
672 }
673
674 if (!link)
675 goto out; /* No link detected */
676
677 mac->get_link_status = false;
678
679 if (hw->phy.type == e1000_phy_82578) {
680 ret_val = e1000_link_stall_workaround_hv(hw);
681 if (ret_val)
682 goto out;
683 }
684
685 if (hw->mac.type == e1000_pch2lan) {
686 ret_val = e1000_k1_workaround_lv(hw);
687 if (ret_val)
688 goto out;
689 }
690
691 /*
692 * Check if there was DownShift, must be checked
693 * immediately after link-up
694 */
695 e1000e_check_downshift(hw);
696
697 /* Enable/Disable EEE after link up */
698 ret_val = e1000_set_eee_pchlan(hw);
699 if (ret_val)
700 goto out;
701
702 /*
703 * If we are forcing speed/duplex, then we simply return since
704 * we have already determined whether we have link or not.
705 */
706 if (!mac->autoneg) {
707 ret_val = -E1000_ERR_CONFIG;
708 goto out;
709 }
710
711 /*
712 * Auto-Neg is enabled. Auto Speed Detection takes care
713 * of MAC speed/duplex configuration. So we only need to
714 * configure Collision Distance in the MAC.
715 */
716 e1000e_config_collision_dist(hw);
717
718 /*
719 * Configure Flow Control now that Auto-Neg has completed.
720 * First, we need to restore the desired flow control
721 * settings because we may have had to re-autoneg with a
722 * different link partner.
723 */
724 ret_val = e1000e_config_fc_after_link_up(hw);
725 if (ret_val)
726 e_dbg("Error configuring flow control\n");
727
728 out:
729 return ret_val;
730 }
731
732 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
733 {
734 struct e1000_hw *hw = &adapter->hw;
735 s32 rc;
736
737 rc = e1000_init_mac_params_ich8lan(adapter);
738 if (rc)
739 return rc;
740
741 rc = e1000_init_nvm_params_ich8lan(hw);
742 if (rc)
743 return rc;
744
745 switch (hw->mac.type) {
746 case e1000_ich8lan:
747 case e1000_ich9lan:
748 case e1000_ich10lan:
749 rc = e1000_init_phy_params_ich8lan(hw);
750 break;
751 case e1000_pchlan:
752 case e1000_pch2lan:
753 rc = e1000_init_phy_params_pchlan(hw);
754 break;
755 default:
756 break;
757 }
758 if (rc)
759 return rc;
760
761 /*
762 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
763 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
764 */
765 if ((adapter->hw.phy.type == e1000_phy_ife) ||
766 ((adapter->hw.mac.type >= e1000_pch2lan) &&
767 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
768 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
769 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
770 }
771
772 if ((adapter->hw.mac.type == e1000_ich8lan) &&
773 (adapter->hw.phy.type == e1000_phy_igp_3))
774 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
775
776 /* Disable EEE by default until IEEE802.3az spec is finalized */
777 if (adapter->flags2 & FLAG2_HAS_EEE)
778 adapter->hw.dev_spec.ich8lan.eee_disable = true;
779
780 return 0;
781 }
782
783 static DEFINE_MUTEX(nvm_mutex);
784
785 /**
786 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
787 * @hw: pointer to the HW structure
788 *
789 * Acquires the mutex for performing NVM operations.
790 **/
791 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
792 {
793 mutex_lock(&nvm_mutex);
794
795 return 0;
796 }
797
798 /**
799 * e1000_release_nvm_ich8lan - Release NVM mutex
800 * @hw: pointer to the HW structure
801 *
802 * Releases the mutex used while performing NVM operations.
803 **/
804 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
805 {
806 mutex_unlock(&nvm_mutex);
807 }
808
809 static DEFINE_MUTEX(swflag_mutex);
810
811 /**
812 * e1000_acquire_swflag_ich8lan - Acquire software control flag
813 * @hw: pointer to the HW structure
814 *
815 * Acquires the software control flag for performing PHY and select
816 * MAC CSR accesses.
817 **/
818 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
819 {
820 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
821 s32 ret_val = 0;
822
823 mutex_lock(&swflag_mutex);
824
825 while (timeout) {
826 extcnf_ctrl = er32(EXTCNF_CTRL);
827 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
828 break;
829
830 mdelay(1);
831 timeout--;
832 }
833
834 if (!timeout) {
835 e_dbg("SW/FW/HW has locked the resource for too long.\n");
836 ret_val = -E1000_ERR_CONFIG;
837 goto out;
838 }
839
840 timeout = SW_FLAG_TIMEOUT;
841
842 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
843 ew32(EXTCNF_CTRL, extcnf_ctrl);
844
845 while (timeout) {
846 extcnf_ctrl = er32(EXTCNF_CTRL);
847 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
848 break;
849
850 mdelay(1);
851 timeout--;
852 }
853
854 if (!timeout) {
855 e_dbg("Failed to acquire the semaphore.\n");
856 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
857 ew32(EXTCNF_CTRL, extcnf_ctrl);
858 ret_val = -E1000_ERR_CONFIG;
859 goto out;
860 }
861
862 out:
863 if (ret_val)
864 mutex_unlock(&swflag_mutex);
865
866 return ret_val;
867 }
868
869 /**
870 * e1000_release_swflag_ich8lan - Release software control flag
871 * @hw: pointer to the HW structure
872 *
873 * Releases the software control flag for performing PHY and select
874 * MAC CSR accesses.
875 **/
876 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
877 {
878 u32 extcnf_ctrl;
879
880 extcnf_ctrl = er32(EXTCNF_CTRL);
881 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
882 ew32(EXTCNF_CTRL, extcnf_ctrl);
883
884 mutex_unlock(&swflag_mutex);
885 }
886
887 /**
888 * e1000_check_mng_mode_ich8lan - Checks management mode
889 * @hw: pointer to the HW structure
890 *
891 * This checks if the adapter has any manageability enabled.
892 * This is a function pointer entry point only called by read/write
893 * routines for the PHY and NVM parts.
894 **/
895 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
896 {
897 u32 fwsm;
898
899 fwsm = er32(FWSM);
900 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
901 ((fwsm & E1000_FWSM_MODE_MASK) ==
902 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
903 }
904
905 /**
906 * e1000_check_mng_mode_pchlan - Checks management mode
907 * @hw: pointer to the HW structure
908 *
909 * This checks if the adapter has iAMT enabled.
910 * This is a function pointer entry point only called by read/write
911 * routines for the PHY and NVM parts.
912 **/
913 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
914 {
915 u32 fwsm;
916
917 fwsm = er32(FWSM);
918 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
919 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
920 }
921
922 /**
923 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
924 * @hw: pointer to the HW structure
925 *
926 * Checks if firmware is blocking the reset of the PHY.
927 * This is a function pointer entry point only called by
928 * reset routines.
929 **/
930 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
931 {
932 u32 fwsm;
933
934 fwsm = er32(FWSM);
935
936 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
937 }
938
939 /**
940 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
941 * @hw: pointer to the HW structure
942 *
943 * Assumes semaphore already acquired.
944 *
945 **/
946 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
947 {
948 u16 phy_data;
949 u32 strap = er32(STRAP);
950 s32 ret_val = 0;
951
952 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
953
954 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
955 if (ret_val)
956 goto out;
957
958 phy_data &= ~HV_SMB_ADDR_MASK;
959 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
960 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
961 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
962
963 out:
964 return ret_val;
965 }
966
967 /**
968 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
969 * @hw: pointer to the HW structure
970 *
971 * SW should configure the LCD from the NVM extended configuration region
972 * as a workaround for certain parts.
973 **/
974 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
975 {
976 struct e1000_phy_info *phy = &hw->phy;
977 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
978 s32 ret_val = 0;
979 u16 word_addr, reg_data, reg_addr, phy_page = 0;
980
981 /*
982 * Initialize the PHY from the NVM on ICH platforms. This
983 * is needed due to an issue where the NVM configuration is
984 * not properly autoloaded after power transitions.
985 * Therefore, after each PHY reset, we will load the
986 * configuration data out of the NVM manually.
987 */
988 switch (hw->mac.type) {
989 case e1000_ich8lan:
990 if (phy->type != e1000_phy_igp_3)
991 return ret_val;
992
993 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
994 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
995 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
996 break;
997 }
998 /* Fall-thru */
999 case e1000_pchlan:
1000 case e1000_pch2lan:
1001 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1002 break;
1003 default:
1004 return ret_val;
1005 }
1006
1007 ret_val = hw->phy.ops.acquire(hw);
1008 if (ret_val)
1009 return ret_val;
1010
1011 data = er32(FEXTNVM);
1012 if (!(data & sw_cfg_mask))
1013 goto out;
1014
1015 /*
1016 * Make sure HW does not configure LCD from PHY
1017 * extended configuration before SW configuration
1018 */
1019 data = er32(EXTCNF_CTRL);
1020 if (!(hw->mac.type == e1000_pch2lan)) {
1021 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1022 goto out;
1023 }
1024
1025 cnf_size = er32(EXTCNF_SIZE);
1026 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1027 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1028 if (!cnf_size)
1029 goto out;
1030
1031 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1032 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1033
1034 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1035 (hw->mac.type == e1000_pchlan)) ||
1036 (hw->mac.type == e1000_pch2lan)) {
1037 /*
1038 * HW configures the SMBus address and LEDs when the
1039 * OEM and LCD Write Enable bits are set in the NVM.
1040 * When both NVM bits are cleared, SW will configure
1041 * them instead.
1042 */
1043 ret_val = e1000_write_smbus_addr(hw);
1044 if (ret_val)
1045 goto out;
1046
1047 data = er32(LEDCTL);
1048 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1049 (u16)data);
1050 if (ret_val)
1051 goto out;
1052 }
1053
1054 /* Configure LCD from extended configuration region. */
1055
1056 /* cnf_base_addr is in DWORD */
1057 word_addr = (u16)(cnf_base_addr << 1);
1058
1059 for (i = 0; i < cnf_size; i++) {
1060 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1061 &reg_data);
1062 if (ret_val)
1063 goto out;
1064
1065 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1066 1, &reg_addr);
1067 if (ret_val)
1068 goto out;
1069
1070 /* Save off the PHY page for future writes. */
1071 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1072 phy_page = reg_data;
1073 continue;
1074 }
1075
1076 reg_addr &= PHY_REG_MASK;
1077 reg_addr |= phy_page;
1078
1079 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1080 reg_data);
1081 if (ret_val)
1082 goto out;
1083 }
1084
1085 out:
1086 hw->phy.ops.release(hw);
1087 return ret_val;
1088 }
1089
1090 /**
1091 * e1000_k1_gig_workaround_hv - K1 Si workaround
1092 * @hw: pointer to the HW structure
1093 * @link: link up bool flag
1094 *
1095 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1096 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1097 * If link is down, the function will restore the default K1 setting located
1098 * in the NVM.
1099 **/
1100 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1101 {
1102 s32 ret_val = 0;
1103 u16 status_reg = 0;
1104 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1105
1106 if (hw->mac.type != e1000_pchlan)
1107 goto out;
1108
1109 /* Wrap the whole flow with the sw flag */
1110 ret_val = hw->phy.ops.acquire(hw);
1111 if (ret_val)
1112 goto out;
1113
1114 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1115 if (link) {
1116 if (hw->phy.type == e1000_phy_82578) {
1117 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1118 &status_reg);
1119 if (ret_val)
1120 goto release;
1121
1122 status_reg &= BM_CS_STATUS_LINK_UP |
1123 BM_CS_STATUS_RESOLVED |
1124 BM_CS_STATUS_SPEED_MASK;
1125
1126 if (status_reg == (BM_CS_STATUS_LINK_UP |
1127 BM_CS_STATUS_RESOLVED |
1128 BM_CS_STATUS_SPEED_1000))
1129 k1_enable = false;
1130 }
1131
1132 if (hw->phy.type == e1000_phy_82577) {
1133 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1134 &status_reg);
1135 if (ret_val)
1136 goto release;
1137
1138 status_reg &= HV_M_STATUS_LINK_UP |
1139 HV_M_STATUS_AUTONEG_COMPLETE |
1140 HV_M_STATUS_SPEED_MASK;
1141
1142 if (status_reg == (HV_M_STATUS_LINK_UP |
1143 HV_M_STATUS_AUTONEG_COMPLETE |
1144 HV_M_STATUS_SPEED_1000))
1145 k1_enable = false;
1146 }
1147
1148 /* Link stall fix for link up */
1149 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1150 0x0100);
1151 if (ret_val)
1152 goto release;
1153
1154 } else {
1155 /* Link stall fix for link down */
1156 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1157 0x4100);
1158 if (ret_val)
1159 goto release;
1160 }
1161
1162 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1163
1164 release:
1165 hw->phy.ops.release(hw);
1166 out:
1167 return ret_val;
1168 }
1169
1170 /**
1171 * e1000_configure_k1_ich8lan - Configure K1 power state
1172 * @hw: pointer to the HW structure
1173 * @enable: K1 state to configure
1174 *
1175 * Configure the K1 power state based on the provided parameter.
1176 * Assumes semaphore already acquired.
1177 *
1178 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1179 **/
1180 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1181 {
1182 s32 ret_val = 0;
1183 u32 ctrl_reg = 0;
1184 u32 ctrl_ext = 0;
1185 u32 reg = 0;
1186 u16 kmrn_reg = 0;
1187
1188 ret_val = e1000e_read_kmrn_reg_locked(hw,
1189 E1000_KMRNCTRLSTA_K1_CONFIG,
1190 &kmrn_reg);
1191 if (ret_val)
1192 goto out;
1193
1194 if (k1_enable)
1195 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1196 else
1197 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1198
1199 ret_val = e1000e_write_kmrn_reg_locked(hw,
1200 E1000_KMRNCTRLSTA_K1_CONFIG,
1201 kmrn_reg);
1202 if (ret_val)
1203 goto out;
1204
1205 udelay(20);
1206 ctrl_ext = er32(CTRL_EXT);
1207 ctrl_reg = er32(CTRL);
1208
1209 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1210 reg |= E1000_CTRL_FRCSPD;
1211 ew32(CTRL, reg);
1212
1213 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1214 udelay(20);
1215 ew32(CTRL, ctrl_reg);
1216 ew32(CTRL_EXT, ctrl_ext);
1217 udelay(20);
1218
1219 out:
1220 return ret_val;
1221 }
1222
1223 /**
1224 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1225 * @hw: pointer to the HW structure
1226 * @d0_state: boolean if entering d0 or d3 device state
1227 *
1228 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1229 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1230 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1231 **/
1232 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1233 {
1234 s32 ret_val = 0;
1235 u32 mac_reg;
1236 u16 oem_reg;
1237
1238 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1239 return ret_val;
1240
1241 ret_val = hw->phy.ops.acquire(hw);
1242 if (ret_val)
1243 return ret_val;
1244
1245 if (!(hw->mac.type == e1000_pch2lan)) {
1246 mac_reg = er32(EXTCNF_CTRL);
1247 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1248 goto out;
1249 }
1250
1251 mac_reg = er32(FEXTNVM);
1252 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1253 goto out;
1254
1255 mac_reg = er32(PHY_CTRL);
1256
1257 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1258 if (ret_val)
1259 goto out;
1260
1261 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1262
1263 if (d0_state) {
1264 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1265 oem_reg |= HV_OEM_BITS_GBE_DIS;
1266
1267 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1268 oem_reg |= HV_OEM_BITS_LPLU;
1269 } else {
1270 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1271 oem_reg |= HV_OEM_BITS_GBE_DIS;
1272
1273 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1274 oem_reg |= HV_OEM_BITS_LPLU;
1275 }
1276 /* Restart auto-neg to activate the bits */
1277 if (!e1000_check_reset_block(hw))
1278 oem_reg |= HV_OEM_BITS_RESTART_AN;
1279 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1280
1281 out:
1282 hw->phy.ops.release(hw);
1283
1284 return ret_val;
1285 }
1286
1287
1288 /**
1289 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1290 * @hw: pointer to the HW structure
1291 **/
1292 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1293 {
1294 s32 ret_val;
1295 u16 data;
1296
1297 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1298 if (ret_val)
1299 return ret_val;
1300
1301 data |= HV_KMRN_MDIO_SLOW;
1302
1303 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1304
1305 return ret_val;
1306 }
1307
1308 /**
1309 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1310 * done after every PHY reset.
1311 **/
1312 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1313 {
1314 s32 ret_val = 0;
1315 u16 phy_data;
1316
1317 if (hw->mac.type != e1000_pchlan)
1318 return ret_val;
1319
1320 /* Set MDIO slow mode before any other MDIO access */
1321 if (hw->phy.type == e1000_phy_82577) {
1322 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1323 if (ret_val)
1324 goto out;
1325 }
1326
1327 if (((hw->phy.type == e1000_phy_82577) &&
1328 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1329 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1330 /* Disable generation of early preamble */
1331 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1332 if (ret_val)
1333 return ret_val;
1334
1335 /* Preamble tuning for SSC */
1336 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1337 if (ret_val)
1338 return ret_val;
1339 }
1340
1341 if (hw->phy.type == e1000_phy_82578) {
1342 /*
1343 * Return registers to default by doing a soft reset then
1344 * writing 0x3140 to the control register.
1345 */
1346 if (hw->phy.revision < 2) {
1347 e1000e_phy_sw_reset(hw);
1348 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1349 }
1350 }
1351
1352 /* Select page 0 */
1353 ret_val = hw->phy.ops.acquire(hw);
1354 if (ret_val)
1355 return ret_val;
1356
1357 hw->phy.addr = 1;
1358 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1359 hw->phy.ops.release(hw);
1360 if (ret_val)
1361 goto out;
1362
1363 /*
1364 * Configure the K1 Si workaround during phy reset assuming there is
1365 * link so that it disables K1 if link is in 1Gbps.
1366 */
1367 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1368 if (ret_val)
1369 goto out;
1370
1371 /* Workaround for link disconnects on a busy hub in half duplex */
1372 ret_val = hw->phy.ops.acquire(hw);
1373 if (ret_val)
1374 goto out;
1375 ret_val = hw->phy.ops.read_reg_locked(hw,
1376 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1377 &phy_data);
1378 if (ret_val)
1379 goto release;
1380 ret_val = hw->phy.ops.write_reg_locked(hw,
1381 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1382 phy_data & 0x00FF);
1383 release:
1384 hw->phy.ops.release(hw);
1385 out:
1386 return ret_val;
1387 }
1388
1389 /**
1390 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1391 * @hw: pointer to the HW structure
1392 **/
1393 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1394 {
1395 u32 mac_reg;
1396 u16 i;
1397
1398 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1399 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1400 mac_reg = er32(RAL(i));
1401 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1402 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1403 mac_reg = er32(RAH(i));
1404 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1405 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1406 }
1407 }
1408
1409 /**
1410 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1411 * with 82579 PHY
1412 * @hw: pointer to the HW structure
1413 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1414 **/
1415 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1416 {
1417 s32 ret_val = 0;
1418 u16 phy_reg, data;
1419 u32 mac_reg;
1420 u16 i;
1421
1422 if (hw->mac.type != e1000_pch2lan)
1423 goto out;
1424
1425 /* disable Rx path while enabling/disabling workaround */
1426 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1427 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1428 if (ret_val)
1429 goto out;
1430
1431 if (enable) {
1432 /*
1433 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1434 * SHRAL/H) and initial CRC values to the MAC
1435 */
1436 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1437 u8 mac_addr[ETH_ALEN] = {0};
1438 u32 addr_high, addr_low;
1439
1440 addr_high = er32(RAH(i));
1441 if (!(addr_high & E1000_RAH_AV))
1442 continue;
1443 addr_low = er32(RAL(i));
1444 mac_addr[0] = (addr_low & 0xFF);
1445 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1446 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1447 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1448 mac_addr[4] = (addr_high & 0xFF);
1449 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1450
1451 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1452 }
1453
1454 /* Write Rx addresses to the PHY */
1455 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1456
1457 /* Enable jumbo frame workaround in the MAC */
1458 mac_reg = er32(FFLT_DBG);
1459 mac_reg &= ~(1 << 14);
1460 mac_reg |= (7 << 15);
1461 ew32(FFLT_DBG, mac_reg);
1462
1463 mac_reg = er32(RCTL);
1464 mac_reg |= E1000_RCTL_SECRC;
1465 ew32(RCTL, mac_reg);
1466
1467 ret_val = e1000e_read_kmrn_reg(hw,
1468 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1469 &data);
1470 if (ret_val)
1471 goto out;
1472 ret_val = e1000e_write_kmrn_reg(hw,
1473 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1474 data | (1 << 0));
1475 if (ret_val)
1476 goto out;
1477 ret_val = e1000e_read_kmrn_reg(hw,
1478 E1000_KMRNCTRLSTA_HD_CTRL,
1479 &data);
1480 if (ret_val)
1481 goto out;
1482 data &= ~(0xF << 8);
1483 data |= (0xB << 8);
1484 ret_val = e1000e_write_kmrn_reg(hw,
1485 E1000_KMRNCTRLSTA_HD_CTRL,
1486 data);
1487 if (ret_val)
1488 goto out;
1489
1490 /* Enable jumbo frame workaround in the PHY */
1491 e1e_rphy(hw, PHY_REG(769, 23), &data);
1492 data &= ~(0x7F << 5);
1493 data |= (0x37 << 5);
1494 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1495 if (ret_val)
1496 goto out;
1497 e1e_rphy(hw, PHY_REG(769, 16), &data);
1498 data &= ~(1 << 13);
1499 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1500 if (ret_val)
1501 goto out;
1502 e1e_rphy(hw, PHY_REG(776, 20), &data);
1503 data &= ~(0x3FF << 2);
1504 data |= (0x1A << 2);
1505 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1506 if (ret_val)
1507 goto out;
1508 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1509 if (ret_val)
1510 goto out;
1511 e1e_rphy(hw, HV_PM_CTRL, &data);
1512 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1513 if (ret_val)
1514 goto out;
1515 } else {
1516 /* Write MAC register values back to h/w defaults */
1517 mac_reg = er32(FFLT_DBG);
1518 mac_reg &= ~(0xF << 14);
1519 ew32(FFLT_DBG, mac_reg);
1520
1521 mac_reg = er32(RCTL);
1522 mac_reg &= ~E1000_RCTL_SECRC;
1523 ew32(RCTL, mac_reg);
1524
1525 ret_val = e1000e_read_kmrn_reg(hw,
1526 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1527 &data);
1528 if (ret_val)
1529 goto out;
1530 ret_val = e1000e_write_kmrn_reg(hw,
1531 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1532 data & ~(1 << 0));
1533 if (ret_val)
1534 goto out;
1535 ret_val = e1000e_read_kmrn_reg(hw,
1536 E1000_KMRNCTRLSTA_HD_CTRL,
1537 &data);
1538 if (ret_val)
1539 goto out;
1540 data &= ~(0xF << 8);
1541 data |= (0xB << 8);
1542 ret_val = e1000e_write_kmrn_reg(hw,
1543 E1000_KMRNCTRLSTA_HD_CTRL,
1544 data);
1545 if (ret_val)
1546 goto out;
1547
1548 /* Write PHY register values back to h/w defaults */
1549 e1e_rphy(hw, PHY_REG(769, 23), &data);
1550 data &= ~(0x7F << 5);
1551 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1552 if (ret_val)
1553 goto out;
1554 e1e_rphy(hw, PHY_REG(769, 16), &data);
1555 data |= (1 << 13);
1556 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1557 if (ret_val)
1558 goto out;
1559 e1e_rphy(hw, PHY_REG(776, 20), &data);
1560 data &= ~(0x3FF << 2);
1561 data |= (0x8 << 2);
1562 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1563 if (ret_val)
1564 goto out;
1565 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1566 if (ret_val)
1567 goto out;
1568 e1e_rphy(hw, HV_PM_CTRL, &data);
1569 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1570 if (ret_val)
1571 goto out;
1572 }
1573
1574 /* re-enable Rx path after enabling/disabling workaround */
1575 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1576
1577 out:
1578 return ret_val;
1579 }
1580
1581 /**
1582 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1583 * done after every PHY reset.
1584 **/
1585 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1586 {
1587 s32 ret_val = 0;
1588
1589 if (hw->mac.type != e1000_pch2lan)
1590 goto out;
1591
1592 /* Set MDIO slow mode before any other MDIO access */
1593 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1594
1595 out:
1596 return ret_val;
1597 }
1598
1599 /**
1600 * e1000_k1_gig_workaround_lv - K1 Si workaround
1601 * @hw: pointer to the HW structure
1602 *
1603 * Workaround to set the K1 beacon duration for 82579 parts
1604 **/
1605 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1606 {
1607 s32 ret_val = 0;
1608 u16 status_reg = 0;
1609 u32 mac_reg;
1610
1611 if (hw->mac.type != e1000_pch2lan)
1612 goto out;
1613
1614 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1615 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1616 if (ret_val)
1617 goto out;
1618
1619 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1620 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1621 mac_reg = er32(FEXTNVM4);
1622 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1623
1624 if (status_reg & HV_M_STATUS_SPEED_1000)
1625 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1626 else
1627 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1628
1629 ew32(FEXTNVM4, mac_reg);
1630 }
1631
1632 out:
1633 return ret_val;
1634 }
1635
1636 /**
1637 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1638 * @hw: pointer to the HW structure
1639 * @gate: boolean set to true to gate, false to ungate
1640 *
1641 * Gate/ungate the automatic PHY configuration via hardware; perform
1642 * the configuration via software instead.
1643 **/
1644 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1645 {
1646 u32 extcnf_ctrl;
1647
1648 if (hw->mac.type != e1000_pch2lan)
1649 return;
1650
1651 extcnf_ctrl = er32(EXTCNF_CTRL);
1652
1653 if (gate)
1654 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1655 else
1656 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1657
1658 ew32(EXTCNF_CTRL, extcnf_ctrl);
1659 return;
1660 }
1661
1662 /**
1663 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1664 * @hw: pointer to the HW structure
1665 *
1666 * Check the appropriate indication the MAC has finished configuring the
1667 * PHY after a software reset.
1668 **/
1669 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1670 {
1671 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1672
1673 /* Wait for basic configuration completes before proceeding */
1674 do {
1675 data = er32(STATUS);
1676 data &= E1000_STATUS_LAN_INIT_DONE;
1677 udelay(100);
1678 } while ((!data) && --loop);
1679
1680 /*
1681 * If basic configuration is incomplete before the above loop
1682 * count reaches 0, loading the configuration from NVM will
1683 * leave the PHY in a bad state possibly resulting in no link.
1684 */
1685 if (loop == 0)
1686 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1687
1688 /* Clear the Init Done bit for the next init event */
1689 data = er32(STATUS);
1690 data &= ~E1000_STATUS_LAN_INIT_DONE;
1691 ew32(STATUS, data);
1692 }
1693
1694 /**
1695 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1696 * @hw: pointer to the HW structure
1697 **/
1698 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1699 {
1700 s32 ret_val = 0;
1701 u16 reg;
1702
1703 if (e1000_check_reset_block(hw))
1704 goto out;
1705
1706 /* Allow time for h/w to get to quiescent state after reset */
1707 msleep(10);
1708
1709 /* Perform any necessary post-reset workarounds */
1710 switch (hw->mac.type) {
1711 case e1000_pchlan:
1712 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1713 if (ret_val)
1714 goto out;
1715 break;
1716 case e1000_pch2lan:
1717 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1718 if (ret_val)
1719 goto out;
1720 break;
1721 default:
1722 break;
1723 }
1724
1725 /* Dummy read to clear the phy wakeup bit after lcd reset */
1726 if (hw->mac.type >= e1000_pchlan)
1727 e1e_rphy(hw, BM_WUC, &reg);
1728
1729 /* Configure the LCD with the extended configuration region in NVM */
1730 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1731 if (ret_val)
1732 goto out;
1733
1734 /* Configure the LCD with the OEM bits in NVM */
1735 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1736
1737 if (hw->mac.type == e1000_pch2lan) {
1738 /* Ungate automatic PHY configuration on non-managed 82579 */
1739 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1740 msleep(10);
1741 e1000_gate_hw_phy_config_ich8lan(hw, false);
1742 }
1743
1744 /* Set EEE LPI Update Timer to 200usec */
1745 ret_val = hw->phy.ops.acquire(hw);
1746 if (ret_val)
1747 goto out;
1748 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1749 I82579_LPI_UPDATE_TIMER);
1750 if (ret_val)
1751 goto release;
1752 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1753 0x1387);
1754 release:
1755 hw->phy.ops.release(hw);
1756 }
1757
1758 out:
1759 return ret_val;
1760 }
1761
1762 /**
1763 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1764 * @hw: pointer to the HW structure
1765 *
1766 * Resets the PHY
1767 * This is a function pointer entry point called by drivers
1768 * or other shared routines.
1769 **/
1770 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1771 {
1772 s32 ret_val = 0;
1773
1774 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1775 if ((hw->mac.type == e1000_pch2lan) &&
1776 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1777 e1000_gate_hw_phy_config_ich8lan(hw, true);
1778
1779 ret_val = e1000e_phy_hw_reset_generic(hw);
1780 if (ret_val)
1781 goto out;
1782
1783 ret_val = e1000_post_phy_reset_ich8lan(hw);
1784
1785 out:
1786 return ret_val;
1787 }
1788
1789 /**
1790 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1791 * @hw: pointer to the HW structure
1792 * @active: true to enable LPLU, false to disable
1793 *
1794 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1795 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1796 * the phy speed. This function will manually set the LPLU bit and restart
1797 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1798 * since it configures the same bit.
1799 **/
1800 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1801 {
1802 s32 ret_val = 0;
1803 u16 oem_reg;
1804
1805 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1806 if (ret_val)
1807 goto out;
1808
1809 if (active)
1810 oem_reg |= HV_OEM_BITS_LPLU;
1811 else
1812 oem_reg &= ~HV_OEM_BITS_LPLU;
1813
1814 oem_reg |= HV_OEM_BITS_RESTART_AN;
1815 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1816
1817 out:
1818 return ret_val;
1819 }
1820
1821 /**
1822 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1823 * @hw: pointer to the HW structure
1824 * @active: true to enable LPLU, false to disable
1825 *
1826 * Sets the LPLU D0 state according to the active flag. When
1827 * activating LPLU this function also disables smart speed
1828 * and vice versa. LPLU will not be activated unless the
1829 * device autonegotiation advertisement meets standards of
1830 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1831 * This is a function pointer entry point only called by
1832 * PHY setup routines.
1833 **/
1834 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1835 {
1836 struct e1000_phy_info *phy = &hw->phy;
1837 u32 phy_ctrl;
1838 s32 ret_val = 0;
1839 u16 data;
1840
1841 if (phy->type == e1000_phy_ife)
1842 return ret_val;
1843
1844 phy_ctrl = er32(PHY_CTRL);
1845
1846 if (active) {
1847 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1848 ew32(PHY_CTRL, phy_ctrl);
1849
1850 if (phy->type != e1000_phy_igp_3)
1851 return 0;
1852
1853 /*
1854 * Call gig speed drop workaround on LPLU before accessing
1855 * any PHY registers
1856 */
1857 if (hw->mac.type == e1000_ich8lan)
1858 e1000e_gig_downshift_workaround_ich8lan(hw);
1859
1860 /* When LPLU is enabled, we should disable SmartSpeed */
1861 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1862 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1863 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1864 if (ret_val)
1865 return ret_val;
1866 } else {
1867 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1868 ew32(PHY_CTRL, phy_ctrl);
1869
1870 if (phy->type != e1000_phy_igp_3)
1871 return 0;
1872
1873 /*
1874 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1875 * during Dx states where the power conservation is most
1876 * important. During driver activity we should enable
1877 * SmartSpeed, so performance is maintained.
1878 */
1879 if (phy->smart_speed == e1000_smart_speed_on) {
1880 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1881 &data);
1882 if (ret_val)
1883 return ret_val;
1884
1885 data |= IGP01E1000_PSCFR_SMART_SPEED;
1886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1887 data);
1888 if (ret_val)
1889 return ret_val;
1890 } else if (phy->smart_speed == e1000_smart_speed_off) {
1891 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1892 &data);
1893 if (ret_val)
1894 return ret_val;
1895
1896 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1897 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1898 data);
1899 if (ret_val)
1900 return ret_val;
1901 }
1902 }
1903
1904 return 0;
1905 }
1906
1907 /**
1908 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1909 * @hw: pointer to the HW structure
1910 * @active: true to enable LPLU, false to disable
1911 *
1912 * Sets the LPLU D3 state according to the active flag. When
1913 * activating LPLU this function also disables smart speed
1914 * and vice versa. LPLU will not be activated unless the
1915 * device autonegotiation advertisement meets standards of
1916 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1917 * This is a function pointer entry point only called by
1918 * PHY setup routines.
1919 **/
1920 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1921 {
1922 struct e1000_phy_info *phy = &hw->phy;
1923 u32 phy_ctrl;
1924 s32 ret_val;
1925 u16 data;
1926
1927 phy_ctrl = er32(PHY_CTRL);
1928
1929 if (!active) {
1930 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1931 ew32(PHY_CTRL, phy_ctrl);
1932
1933 if (phy->type != e1000_phy_igp_3)
1934 return 0;
1935
1936 /*
1937 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1938 * during Dx states where the power conservation is most
1939 * important. During driver activity we should enable
1940 * SmartSpeed, so performance is maintained.
1941 */
1942 if (phy->smart_speed == e1000_smart_speed_on) {
1943 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1944 &data);
1945 if (ret_val)
1946 return ret_val;
1947
1948 data |= IGP01E1000_PSCFR_SMART_SPEED;
1949 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1950 data);
1951 if (ret_val)
1952 return ret_val;
1953 } else if (phy->smart_speed == e1000_smart_speed_off) {
1954 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1955 &data);
1956 if (ret_val)
1957 return ret_val;
1958
1959 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1960 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1961 data);
1962 if (ret_val)
1963 return ret_val;
1964 }
1965 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1966 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1967 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1968 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1969 ew32(PHY_CTRL, phy_ctrl);
1970
1971 if (phy->type != e1000_phy_igp_3)
1972 return 0;
1973
1974 /*
1975 * Call gig speed drop workaround on LPLU before accessing
1976 * any PHY registers
1977 */
1978 if (hw->mac.type == e1000_ich8lan)
1979 e1000e_gig_downshift_workaround_ich8lan(hw);
1980
1981 /* When LPLU is enabled, we should disable SmartSpeed */
1982 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1983 if (ret_val)
1984 return ret_val;
1985
1986 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1987 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1988 }
1989
1990 return 0;
1991 }
1992
1993 /**
1994 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1995 * @hw: pointer to the HW structure
1996 * @bank: pointer to the variable that returns the active bank
1997 *
1998 * Reads signature byte from the NVM using the flash access registers.
1999 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2000 **/
2001 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2002 {
2003 u32 eecd;
2004 struct e1000_nvm_info *nvm = &hw->nvm;
2005 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2006 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2007 u8 sig_byte = 0;
2008 s32 ret_val = 0;
2009
2010 switch (hw->mac.type) {
2011 case e1000_ich8lan:
2012 case e1000_ich9lan:
2013 eecd = er32(EECD);
2014 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2015 E1000_EECD_SEC1VAL_VALID_MASK) {
2016 if (eecd & E1000_EECD_SEC1VAL)
2017 *bank = 1;
2018 else
2019 *bank = 0;
2020
2021 return 0;
2022 }
2023 e_dbg("Unable to determine valid NVM bank via EEC - "
2024 "reading flash signature\n");
2025 /* fall-thru */
2026 default:
2027 /* set bank to 0 in case flash read fails */
2028 *bank = 0;
2029
2030 /* Check bank 0 */
2031 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2032 &sig_byte);
2033 if (ret_val)
2034 return ret_val;
2035 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2036 E1000_ICH_NVM_SIG_VALUE) {
2037 *bank = 0;
2038 return 0;
2039 }
2040
2041 /* Check bank 1 */
2042 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2043 bank1_offset,
2044 &sig_byte);
2045 if (ret_val)
2046 return ret_val;
2047 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2048 E1000_ICH_NVM_SIG_VALUE) {
2049 *bank = 1;
2050 return 0;
2051 }
2052
2053 e_dbg("ERROR: No valid NVM bank present\n");
2054 return -E1000_ERR_NVM;
2055 }
2056
2057 return 0;
2058 }
2059
2060 /**
2061 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2062 * @hw: pointer to the HW structure
2063 * @offset: The offset (in bytes) of the word(s) to read.
2064 * @words: Size of data to read in words
2065 * @data: Pointer to the word(s) to read at offset.
2066 *
2067 * Reads a word(s) from the NVM using the flash access registers.
2068 **/
2069 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2070 u16 *data)
2071 {
2072 struct e1000_nvm_info *nvm = &hw->nvm;
2073 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2074 u32 act_offset;
2075 s32 ret_val = 0;
2076 u32 bank = 0;
2077 u16 i, word;
2078
2079 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2080 (words == 0)) {
2081 e_dbg("nvm parameter(s) out of bounds\n");
2082 ret_val = -E1000_ERR_NVM;
2083 goto out;
2084 }
2085
2086 nvm->ops.acquire(hw);
2087
2088 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2089 if (ret_val) {
2090 e_dbg("Could not detect valid bank, assuming bank 0\n");
2091 bank = 0;
2092 }
2093
2094 act_offset = (bank) ? nvm->flash_bank_size : 0;
2095 act_offset += offset;
2096
2097 ret_val = 0;
2098 for (i = 0; i < words; i++) {
2099 if ((dev_spec->shadow_ram) &&
2100 (dev_spec->shadow_ram[offset+i].modified)) {
2101 data[i] = dev_spec->shadow_ram[offset+i].value;
2102 } else {
2103 ret_val = e1000_read_flash_word_ich8lan(hw,
2104 act_offset + i,
2105 &word);
2106 if (ret_val)
2107 break;
2108 data[i] = word;
2109 }
2110 }
2111
2112 nvm->ops.release(hw);
2113
2114 out:
2115 if (ret_val)
2116 e_dbg("NVM read error: %d\n", ret_val);
2117
2118 return ret_val;
2119 }
2120
2121 /**
2122 * e1000_flash_cycle_init_ich8lan - Initialize flash
2123 * @hw: pointer to the HW structure
2124 *
2125 * This function does initial flash setup so that a new read/write/erase cycle
2126 * can be started.
2127 **/
2128 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2129 {
2130 union ich8_hws_flash_status hsfsts;
2131 s32 ret_val = -E1000_ERR_NVM;
2132
2133 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2134
2135 /* Check if the flash descriptor is valid */
2136 if (hsfsts.hsf_status.fldesvalid == 0) {
2137 e_dbg("Flash descriptor invalid. "
2138 "SW Sequencing must be used.\n");
2139 return -E1000_ERR_NVM;
2140 }
2141
2142 /* Clear FCERR and DAEL in hw status by writing 1 */
2143 hsfsts.hsf_status.flcerr = 1;
2144 hsfsts.hsf_status.dael = 1;
2145
2146 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2147
2148 /*
2149 * Either we should have a hardware SPI cycle in progress
2150 * bit to check against, in order to start a new cycle or
2151 * FDONE bit should be changed in the hardware so that it
2152 * is 1 after hardware reset, which can then be used as an
2153 * indication whether a cycle is in progress or has been
2154 * completed.
2155 */
2156
2157 if (hsfsts.hsf_status.flcinprog == 0) {
2158 /*
2159 * There is no cycle running at present,
2160 * so we can start a cycle.
2161 * Begin by setting Flash Cycle Done.
2162 */
2163 hsfsts.hsf_status.flcdone = 1;
2164 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2165 ret_val = 0;
2166 } else {
2167 s32 i = 0;
2168
2169 /*
2170 * Otherwise poll for sometime so the current
2171 * cycle has a chance to end before giving up.
2172 */
2173 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2174 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2175 if (hsfsts.hsf_status.flcinprog == 0) {
2176 ret_val = 0;
2177 break;
2178 }
2179 udelay(1);
2180 }
2181 if (ret_val == 0) {
2182 /*
2183 * Successful in waiting for previous cycle to timeout,
2184 * now set the Flash Cycle Done.
2185 */
2186 hsfsts.hsf_status.flcdone = 1;
2187 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2188 } else {
2189 e_dbg("Flash controller busy, cannot get access\n");
2190 }
2191 }
2192
2193 return ret_val;
2194 }
2195
2196 /**
2197 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2198 * @hw: pointer to the HW structure
2199 * @timeout: maximum time to wait for completion
2200 *
2201 * This function starts a flash cycle and waits for its completion.
2202 **/
2203 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2204 {
2205 union ich8_hws_flash_ctrl hsflctl;
2206 union ich8_hws_flash_status hsfsts;
2207 s32 ret_val = -E1000_ERR_NVM;
2208 u32 i = 0;
2209
2210 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2211 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2212 hsflctl.hsf_ctrl.flcgo = 1;
2213 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2214
2215 /* wait till FDONE bit is set to 1 */
2216 do {
2217 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2218 if (hsfsts.hsf_status.flcdone == 1)
2219 break;
2220 udelay(1);
2221 } while (i++ < timeout);
2222
2223 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2224 return 0;
2225
2226 return ret_val;
2227 }
2228
2229 /**
2230 * e1000_read_flash_word_ich8lan - Read word from flash
2231 * @hw: pointer to the HW structure
2232 * @offset: offset to data location
2233 * @data: pointer to the location for storing the data
2234 *
2235 * Reads the flash word at offset into data. Offset is converted
2236 * to bytes before read.
2237 **/
2238 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2239 u16 *data)
2240 {
2241 /* Must convert offset into bytes. */
2242 offset <<= 1;
2243
2244 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2245 }
2246
2247 /**
2248 * e1000_read_flash_byte_ich8lan - Read byte from flash
2249 * @hw: pointer to the HW structure
2250 * @offset: The offset of the byte to read.
2251 * @data: Pointer to a byte to store the value read.
2252 *
2253 * Reads a single byte from the NVM using the flash access registers.
2254 **/
2255 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2256 u8 *data)
2257 {
2258 s32 ret_val;
2259 u16 word = 0;
2260
2261 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2262 if (ret_val)
2263 return ret_val;
2264
2265 *data = (u8)word;
2266
2267 return 0;
2268 }
2269
2270 /**
2271 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2272 * @hw: pointer to the HW structure
2273 * @offset: The offset (in bytes) of the byte or word to read.
2274 * @size: Size of data to read, 1=byte 2=word
2275 * @data: Pointer to the word to store the value read.
2276 *
2277 * Reads a byte or word from the NVM using the flash access registers.
2278 **/
2279 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2280 u8 size, u16 *data)
2281 {
2282 union ich8_hws_flash_status hsfsts;
2283 union ich8_hws_flash_ctrl hsflctl;
2284 u32 flash_linear_addr;
2285 u32 flash_data = 0;
2286 s32 ret_val = -E1000_ERR_NVM;
2287 u8 count = 0;
2288
2289 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2290 return -E1000_ERR_NVM;
2291
2292 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2293 hw->nvm.flash_base_addr;
2294
2295 do {
2296 udelay(1);
2297 /* Steps */
2298 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2299 if (ret_val != 0)
2300 break;
2301
2302 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2303 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2304 hsflctl.hsf_ctrl.fldbcount = size - 1;
2305 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2306 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2307
2308 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2309
2310 ret_val = e1000_flash_cycle_ich8lan(hw,
2311 ICH_FLASH_READ_COMMAND_TIMEOUT);
2312
2313 /*
2314 * Check if FCERR is set to 1, if set to 1, clear it
2315 * and try the whole sequence a few more times, else
2316 * read in (shift in) the Flash Data0, the order is
2317 * least significant byte first msb to lsb
2318 */
2319 if (ret_val == 0) {
2320 flash_data = er32flash(ICH_FLASH_FDATA0);
2321 if (size == 1)
2322 *data = (u8)(flash_data & 0x000000FF);
2323 else if (size == 2)
2324 *data = (u16)(flash_data & 0x0000FFFF);
2325 break;
2326 } else {
2327 /*
2328 * If we've gotten here, then things are probably
2329 * completely hosed, but if the error condition is
2330 * detected, it won't hurt to give it another try...
2331 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2332 */
2333 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2334 if (hsfsts.hsf_status.flcerr == 1) {
2335 /* Repeat for some time before giving up. */
2336 continue;
2337 } else if (hsfsts.hsf_status.flcdone == 0) {
2338 e_dbg("Timeout error - flash cycle "
2339 "did not complete.\n");
2340 break;
2341 }
2342 }
2343 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2344
2345 return ret_val;
2346 }
2347
2348 /**
2349 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2350 * @hw: pointer to the HW structure
2351 * @offset: The offset (in bytes) of the word(s) to write.
2352 * @words: Size of data to write in words
2353 * @data: Pointer to the word(s) to write at offset.
2354 *
2355 * Writes a byte or word to the NVM using the flash access registers.
2356 **/
2357 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2358 u16 *data)
2359 {
2360 struct e1000_nvm_info *nvm = &hw->nvm;
2361 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2362 u16 i;
2363
2364 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2365 (words == 0)) {
2366 e_dbg("nvm parameter(s) out of bounds\n");
2367 return -E1000_ERR_NVM;
2368 }
2369
2370 nvm->ops.acquire(hw);
2371
2372 for (i = 0; i < words; i++) {
2373 dev_spec->shadow_ram[offset+i].modified = true;
2374 dev_spec->shadow_ram[offset+i].value = data[i];
2375 }
2376
2377 nvm->ops.release(hw);
2378
2379 return 0;
2380 }
2381
2382 /**
2383 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2384 * @hw: pointer to the HW structure
2385 *
2386 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2387 * which writes the checksum to the shadow ram. The changes in the shadow
2388 * ram are then committed to the EEPROM by processing each bank at a time
2389 * checking for the modified bit and writing only the pending changes.
2390 * After a successful commit, the shadow ram is cleared and is ready for
2391 * future writes.
2392 **/
2393 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2394 {
2395 struct e1000_nvm_info *nvm = &hw->nvm;
2396 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2397 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2398 s32 ret_val;
2399 u16 data;
2400
2401 ret_val = e1000e_update_nvm_checksum_generic(hw);
2402 if (ret_val)
2403 goto out;
2404
2405 if (nvm->type != e1000_nvm_flash_sw)
2406 goto out;
2407
2408 nvm->ops.acquire(hw);
2409
2410 /*
2411 * We're writing to the opposite bank so if we're on bank 1,
2412 * write to bank 0 etc. We also need to erase the segment that
2413 * is going to be written
2414 */
2415 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2416 if (ret_val) {
2417 e_dbg("Could not detect valid bank, assuming bank 0\n");
2418 bank = 0;
2419 }
2420
2421 if (bank == 0) {
2422 new_bank_offset = nvm->flash_bank_size;
2423 old_bank_offset = 0;
2424 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2425 if (ret_val)
2426 goto release;
2427 } else {
2428 old_bank_offset = nvm->flash_bank_size;
2429 new_bank_offset = 0;
2430 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2431 if (ret_val)
2432 goto release;
2433 }
2434
2435 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2436 /*
2437 * Determine whether to write the value stored
2438 * in the other NVM bank or a modified value stored
2439 * in the shadow RAM
2440 */
2441 if (dev_spec->shadow_ram[i].modified) {
2442 data = dev_spec->shadow_ram[i].value;
2443 } else {
2444 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2445 old_bank_offset,
2446 &data);
2447 if (ret_val)
2448 break;
2449 }
2450
2451 /*
2452 * If the word is 0x13, then make sure the signature bits
2453 * (15:14) are 11b until the commit has completed.
2454 * This will allow us to write 10b which indicates the
2455 * signature is valid. We want to do this after the write
2456 * has completed so that we don't mark the segment valid
2457 * while the write is still in progress
2458 */
2459 if (i == E1000_ICH_NVM_SIG_WORD)
2460 data |= E1000_ICH_NVM_SIG_MASK;
2461
2462 /* Convert offset to bytes. */
2463 act_offset = (i + new_bank_offset) << 1;
2464
2465 udelay(100);
2466 /* Write the bytes to the new bank. */
2467 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2468 act_offset,
2469 (u8)data);
2470 if (ret_val)
2471 break;
2472
2473 udelay(100);
2474 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2475 act_offset + 1,
2476 (u8)(data >> 8));
2477 if (ret_val)
2478 break;
2479 }
2480
2481 /*
2482 * Don't bother writing the segment valid bits if sector
2483 * programming failed.
2484 */
2485 if (ret_val) {
2486 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2487 e_dbg("Flash commit failed.\n");
2488 goto release;
2489 }
2490
2491 /*
2492 * Finally validate the new segment by setting bit 15:14
2493 * to 10b in word 0x13 , this can be done without an
2494 * erase as well since these bits are 11 to start with
2495 * and we need to change bit 14 to 0b
2496 */
2497 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2498 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2499 if (ret_val)
2500 goto release;
2501
2502 data &= 0xBFFF;
2503 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2504 act_offset * 2 + 1,
2505 (u8)(data >> 8));
2506 if (ret_val)
2507 goto release;
2508
2509 /*
2510 * And invalidate the previously valid segment by setting
2511 * its signature word (0x13) high_byte to 0b. This can be
2512 * done without an erase because flash erase sets all bits
2513 * to 1's. We can write 1's to 0's without an erase
2514 */
2515 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2516 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2517 if (ret_val)
2518 goto release;
2519
2520 /* Great! Everything worked, we can now clear the cached entries. */
2521 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2522 dev_spec->shadow_ram[i].modified = false;
2523 dev_spec->shadow_ram[i].value = 0xFFFF;
2524 }
2525
2526 release:
2527 nvm->ops.release(hw);
2528
2529 /*
2530 * Reload the EEPROM, or else modifications will not appear
2531 * until after the next adapter reset.
2532 */
2533 if (!ret_val) {
2534 e1000e_reload_nvm(hw);
2535 msleep(10);
2536 }
2537
2538 out:
2539 if (ret_val)
2540 e_dbg("NVM update error: %d\n", ret_val);
2541
2542 return ret_val;
2543 }
2544
2545 /**
2546 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2547 * @hw: pointer to the HW structure
2548 *
2549 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2550 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2551 * calculated, in which case we need to calculate the checksum and set bit 6.
2552 **/
2553 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2554 {
2555 s32 ret_val;
2556 u16 data;
2557
2558 /*
2559 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2560 * needs to be fixed. This bit is an indication that the NVM
2561 * was prepared by OEM software and did not calculate the
2562 * checksum...a likely scenario.
2563 */
2564 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2565 if (ret_val)
2566 return ret_val;
2567
2568 if ((data & 0x40) == 0) {
2569 data |= 0x40;
2570 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2571 if (ret_val)
2572 return ret_val;
2573 ret_val = e1000e_update_nvm_checksum(hw);
2574 if (ret_val)
2575 return ret_val;
2576 }
2577
2578 return e1000e_validate_nvm_checksum_generic(hw);
2579 }
2580
2581 /**
2582 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2583 * @hw: pointer to the HW structure
2584 *
2585 * To prevent malicious write/erase of the NVM, set it to be read-only
2586 * so that the hardware ignores all write/erase cycles of the NVM via
2587 * the flash control registers. The shadow-ram copy of the NVM will
2588 * still be updated, however any updates to this copy will not stick
2589 * across driver reloads.
2590 **/
2591 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2592 {
2593 struct e1000_nvm_info *nvm = &hw->nvm;
2594 union ich8_flash_protected_range pr0;
2595 union ich8_hws_flash_status hsfsts;
2596 u32 gfpreg;
2597
2598 nvm->ops.acquire(hw);
2599
2600 gfpreg = er32flash(ICH_FLASH_GFPREG);
2601
2602 /* Write-protect GbE Sector of NVM */
2603 pr0.regval = er32flash(ICH_FLASH_PR0);
2604 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2605 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2606 pr0.range.wpe = true;
2607 ew32flash(ICH_FLASH_PR0, pr0.regval);
2608
2609 /*
2610 * Lock down a subset of GbE Flash Control Registers, e.g.
2611 * PR0 to prevent the write-protection from being lifted.
2612 * Once FLOCKDN is set, the registers protected by it cannot
2613 * be written until FLOCKDN is cleared by a hardware reset.
2614 */
2615 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2616 hsfsts.hsf_status.flockdn = true;
2617 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2618
2619 nvm->ops.release(hw);
2620 }
2621
2622 /**
2623 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2624 * @hw: pointer to the HW structure
2625 * @offset: The offset (in bytes) of the byte/word to read.
2626 * @size: Size of data to read, 1=byte 2=word
2627 * @data: The byte(s) to write to the NVM.
2628 *
2629 * Writes one/two bytes to the NVM using the flash access registers.
2630 **/
2631 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2632 u8 size, u16 data)
2633 {
2634 union ich8_hws_flash_status hsfsts;
2635 union ich8_hws_flash_ctrl hsflctl;
2636 u32 flash_linear_addr;
2637 u32 flash_data = 0;
2638 s32 ret_val;
2639 u8 count = 0;
2640
2641 if (size < 1 || size > 2 || data > size * 0xff ||
2642 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2643 return -E1000_ERR_NVM;
2644
2645 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2646 hw->nvm.flash_base_addr;
2647
2648 do {
2649 udelay(1);
2650 /* Steps */
2651 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2652 if (ret_val)
2653 break;
2654
2655 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2656 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2657 hsflctl.hsf_ctrl.fldbcount = size -1;
2658 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2659 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2660
2661 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2662
2663 if (size == 1)
2664 flash_data = (u32)data & 0x00FF;
2665 else
2666 flash_data = (u32)data;
2667
2668 ew32flash(ICH_FLASH_FDATA0, flash_data);
2669
2670 /*
2671 * check if FCERR is set to 1 , if set to 1, clear it
2672 * and try the whole sequence a few more times else done
2673 */
2674 ret_val = e1000_flash_cycle_ich8lan(hw,
2675 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2676 if (!ret_val)
2677 break;
2678
2679 /*
2680 * If we're here, then things are most likely
2681 * completely hosed, but if the error condition
2682 * is detected, it won't hurt to give it another
2683 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2684 */
2685 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2686 if (hsfsts.hsf_status.flcerr == 1)
2687 /* Repeat for some time before giving up. */
2688 continue;
2689 if (hsfsts.hsf_status.flcdone == 0) {
2690 e_dbg("Timeout error - flash cycle "
2691 "did not complete.");
2692 break;
2693 }
2694 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2695
2696 return ret_val;
2697 }
2698
2699 /**
2700 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2701 * @hw: pointer to the HW structure
2702 * @offset: The index of the byte to read.
2703 * @data: The byte to write to the NVM.
2704 *
2705 * Writes a single byte to the NVM using the flash access registers.
2706 **/
2707 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2708 u8 data)
2709 {
2710 u16 word = (u16)data;
2711
2712 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2713 }
2714
2715 /**
2716 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2717 * @hw: pointer to the HW structure
2718 * @offset: The offset of the byte to write.
2719 * @byte: The byte to write to the NVM.
2720 *
2721 * Writes a single byte to the NVM using the flash access registers.
2722 * Goes through a retry algorithm before giving up.
2723 **/
2724 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2725 u32 offset, u8 byte)
2726 {
2727 s32 ret_val;
2728 u16 program_retries;
2729
2730 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2731 if (!ret_val)
2732 return ret_val;
2733
2734 for (program_retries = 0; program_retries < 100; program_retries++) {
2735 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2736 udelay(100);
2737 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2738 if (!ret_val)
2739 break;
2740 }
2741 if (program_retries == 100)
2742 return -E1000_ERR_NVM;
2743
2744 return 0;
2745 }
2746
2747 /**
2748 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2749 * @hw: pointer to the HW structure
2750 * @bank: 0 for first bank, 1 for second bank, etc.
2751 *
2752 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2753 * bank N is 4096 * N + flash_reg_addr.
2754 **/
2755 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2756 {
2757 struct e1000_nvm_info *nvm = &hw->nvm;
2758 union ich8_hws_flash_status hsfsts;
2759 union ich8_hws_flash_ctrl hsflctl;
2760 u32 flash_linear_addr;
2761 /* bank size is in 16bit words - adjust to bytes */
2762 u32 flash_bank_size = nvm->flash_bank_size * 2;
2763 s32 ret_val;
2764 s32 count = 0;
2765 s32 j, iteration, sector_size;
2766
2767 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2768
2769 /*
2770 * Determine HW Sector size: Read BERASE bits of hw flash status
2771 * register
2772 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2773 * consecutive sectors. The start index for the nth Hw sector
2774 * can be calculated as = bank * 4096 + n * 256
2775 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2776 * The start index for the nth Hw sector can be calculated
2777 * as = bank * 4096
2778 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2779 * (ich9 only, otherwise error condition)
2780 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2781 */
2782 switch (hsfsts.hsf_status.berasesz) {
2783 case 0:
2784 /* Hw sector size 256 */
2785 sector_size = ICH_FLASH_SEG_SIZE_256;
2786 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2787 break;
2788 case 1:
2789 sector_size = ICH_FLASH_SEG_SIZE_4K;
2790 iteration = 1;
2791 break;
2792 case 2:
2793 sector_size = ICH_FLASH_SEG_SIZE_8K;
2794 iteration = 1;
2795 break;
2796 case 3:
2797 sector_size = ICH_FLASH_SEG_SIZE_64K;
2798 iteration = 1;
2799 break;
2800 default:
2801 return -E1000_ERR_NVM;
2802 }
2803
2804 /* Start with the base address, then add the sector offset. */
2805 flash_linear_addr = hw->nvm.flash_base_addr;
2806 flash_linear_addr += (bank) ? flash_bank_size : 0;
2807
2808 for (j = 0; j < iteration ; j++) {
2809 do {
2810 /* Steps */
2811 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2812 if (ret_val)
2813 return ret_val;
2814
2815 /*
2816 * Write a value 11 (block Erase) in Flash
2817 * Cycle field in hw flash control
2818 */
2819 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2820 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2821 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2822
2823 /*
2824 * Write the last 24 bits of an index within the
2825 * block into Flash Linear address field in Flash
2826 * Address.
2827 */
2828 flash_linear_addr += (j * sector_size);
2829 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2830
2831 ret_val = e1000_flash_cycle_ich8lan(hw,
2832 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2833 if (ret_val == 0)
2834 break;
2835
2836 /*
2837 * Check if FCERR is set to 1. If 1,
2838 * clear it and try the whole sequence
2839 * a few more times else Done
2840 */
2841 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2842 if (hsfsts.hsf_status.flcerr == 1)
2843 /* repeat for some time before giving up */
2844 continue;
2845 else if (hsfsts.hsf_status.flcdone == 0)
2846 return ret_val;
2847 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2848 }
2849
2850 return 0;
2851 }
2852
2853 /**
2854 * e1000_valid_led_default_ich8lan - Set the default LED settings
2855 * @hw: pointer to the HW structure
2856 * @data: Pointer to the LED settings
2857 *
2858 * Reads the LED default settings from the NVM to data. If the NVM LED
2859 * settings is all 0's or F's, set the LED default to a valid LED default
2860 * setting.
2861 **/
2862 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2863 {
2864 s32 ret_val;
2865
2866 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2867 if (ret_val) {
2868 e_dbg("NVM Read Error\n");
2869 return ret_val;
2870 }
2871
2872 if (*data == ID_LED_RESERVED_0000 ||
2873 *data == ID_LED_RESERVED_FFFF)
2874 *data = ID_LED_DEFAULT_ICH8LAN;
2875
2876 return 0;
2877 }
2878
2879 /**
2880 * e1000_id_led_init_pchlan - store LED configurations
2881 * @hw: pointer to the HW structure
2882 *
2883 * PCH does not control LEDs via the LEDCTL register, rather it uses
2884 * the PHY LED configuration register.
2885 *
2886 * PCH also does not have an "always on" or "always off" mode which
2887 * complicates the ID feature. Instead of using the "on" mode to indicate
2888 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2889 * use "link_up" mode. The LEDs will still ID on request if there is no
2890 * link based on logic in e1000_led_[on|off]_pchlan().
2891 **/
2892 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2893 {
2894 struct e1000_mac_info *mac = &hw->mac;
2895 s32 ret_val;
2896 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2897 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2898 u16 data, i, temp, shift;
2899
2900 /* Get default ID LED modes */
2901 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2902 if (ret_val)
2903 goto out;
2904
2905 mac->ledctl_default = er32(LEDCTL);
2906 mac->ledctl_mode1 = mac->ledctl_default;
2907 mac->ledctl_mode2 = mac->ledctl_default;
2908
2909 for (i = 0; i < 4; i++) {
2910 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2911 shift = (i * 5);
2912 switch (temp) {
2913 case ID_LED_ON1_DEF2:
2914 case ID_LED_ON1_ON2:
2915 case ID_LED_ON1_OFF2:
2916 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2917 mac->ledctl_mode1 |= (ledctl_on << shift);
2918 break;
2919 case ID_LED_OFF1_DEF2:
2920 case ID_LED_OFF1_ON2:
2921 case ID_LED_OFF1_OFF2:
2922 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2923 mac->ledctl_mode1 |= (ledctl_off << shift);
2924 break;
2925 default:
2926 /* Do nothing */
2927 break;
2928 }
2929 switch (temp) {
2930 case ID_LED_DEF1_ON2:
2931 case ID_LED_ON1_ON2:
2932 case ID_LED_OFF1_ON2:
2933 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2934 mac->ledctl_mode2 |= (ledctl_on << shift);
2935 break;
2936 case ID_LED_DEF1_OFF2:
2937 case ID_LED_ON1_OFF2:
2938 case ID_LED_OFF1_OFF2:
2939 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2940 mac->ledctl_mode2 |= (ledctl_off << shift);
2941 break;
2942 default:
2943 /* Do nothing */
2944 break;
2945 }
2946 }
2947
2948 out:
2949 return ret_val;
2950 }
2951
2952 /**
2953 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2954 * @hw: pointer to the HW structure
2955 *
2956 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2957 * register, so the the bus width is hard coded.
2958 **/
2959 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2960 {
2961 struct e1000_bus_info *bus = &hw->bus;
2962 s32 ret_val;
2963
2964 ret_val = e1000e_get_bus_info_pcie(hw);
2965
2966 /*
2967 * ICH devices are "PCI Express"-ish. They have
2968 * a configuration space, but do not contain
2969 * PCI Express Capability registers, so bus width
2970 * must be hardcoded.
2971 */
2972 if (bus->width == e1000_bus_width_unknown)
2973 bus->width = e1000_bus_width_pcie_x1;
2974
2975 return ret_val;
2976 }
2977
2978 /**
2979 * e1000_reset_hw_ich8lan - Reset the hardware
2980 * @hw: pointer to the HW structure
2981 *
2982 * Does a full reset of the hardware which includes a reset of the PHY and
2983 * MAC.
2984 **/
2985 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2986 {
2987 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2988 u16 reg;
2989 u32 ctrl, kab;
2990 s32 ret_val;
2991
2992 /*
2993 * Prevent the PCI-E bus from sticking if there is no TLP connection
2994 * on the last TLP read/write transaction when MAC is reset.
2995 */
2996 ret_val = e1000e_disable_pcie_master(hw);
2997 if (ret_val)
2998 e_dbg("PCI-E Master disable polling has failed.\n");
2999
3000 e_dbg("Masking off all interrupts\n");
3001 ew32(IMC, 0xffffffff);
3002
3003 /*
3004 * Disable the Transmit and Receive units. Then delay to allow
3005 * any pending transactions to complete before we hit the MAC
3006 * with the global reset.
3007 */
3008 ew32(RCTL, 0);
3009 ew32(TCTL, E1000_TCTL_PSP);
3010 e1e_flush();
3011
3012 msleep(10);
3013
3014 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3015 if (hw->mac.type == e1000_ich8lan) {
3016 /* Set Tx and Rx buffer allocation to 8k apiece. */
3017 ew32(PBA, E1000_PBA_8K);
3018 /* Set Packet Buffer Size to 16k. */
3019 ew32(PBS, E1000_PBS_16K);
3020 }
3021
3022 if (hw->mac.type == e1000_pchlan) {
3023 /* Save the NVM K1 bit setting*/
3024 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3025 if (ret_val)
3026 return ret_val;
3027
3028 if (reg & E1000_NVM_K1_ENABLE)
3029 dev_spec->nvm_k1_enabled = true;
3030 else
3031 dev_spec->nvm_k1_enabled = false;
3032 }
3033
3034 ctrl = er32(CTRL);
3035
3036 if (!e1000_check_reset_block(hw)) {
3037 /*
3038 * Full-chip reset requires MAC and PHY reset at the same
3039 * time to make sure the interface between MAC and the
3040 * external PHY is reset.
3041 */
3042 ctrl |= E1000_CTRL_PHY_RST;
3043
3044 /*
3045 * Gate automatic PHY configuration by hardware on
3046 * non-managed 82579
3047 */
3048 if ((hw->mac.type == e1000_pch2lan) &&
3049 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3050 e1000_gate_hw_phy_config_ich8lan(hw, true);
3051 }
3052 ret_val = e1000_acquire_swflag_ich8lan(hw);
3053 e_dbg("Issuing a global reset to ich8lan\n");
3054 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3055 msleep(20);
3056
3057 if (!ret_val)
3058 e1000_release_swflag_ich8lan(hw);
3059
3060 if (ctrl & E1000_CTRL_PHY_RST) {
3061 ret_val = hw->phy.ops.get_cfg_done(hw);
3062 if (ret_val)
3063 goto out;
3064
3065 ret_val = e1000_post_phy_reset_ich8lan(hw);
3066 if (ret_val)
3067 goto out;
3068 }
3069
3070 /*
3071 * For PCH, this write will make sure that any noise
3072 * will be detected as a CRC error and be dropped rather than show up
3073 * as a bad packet to the DMA engine.
3074 */
3075 if (hw->mac.type == e1000_pchlan)
3076 ew32(CRC_OFFSET, 0x65656565);
3077
3078 ew32(IMC, 0xffffffff);
3079 er32(ICR);
3080
3081 kab = er32(KABGTXD);
3082 kab |= E1000_KABGTXD_BGSQLBIAS;
3083 ew32(KABGTXD, kab);
3084
3085 out:
3086 return ret_val;
3087 }
3088
3089 /**
3090 * e1000_init_hw_ich8lan - Initialize the hardware
3091 * @hw: pointer to the HW structure
3092 *
3093 * Prepares the hardware for transmit and receive by doing the following:
3094 * - initialize hardware bits
3095 * - initialize LED identification
3096 * - setup receive address registers
3097 * - setup flow control
3098 * - setup transmit descriptors
3099 * - clear statistics
3100 **/
3101 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3102 {
3103 struct e1000_mac_info *mac = &hw->mac;
3104 u32 ctrl_ext, txdctl, snoop;
3105 s32 ret_val;
3106 u16 i;
3107
3108 e1000_initialize_hw_bits_ich8lan(hw);
3109
3110 /* Initialize identification LED */
3111 ret_val = mac->ops.id_led_init(hw);
3112 if (ret_val)
3113 e_dbg("Error initializing identification LED\n");
3114 /* This is not fatal and we should not stop init due to this */
3115
3116 /* Setup the receive address. */
3117 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3118
3119 /* Zero out the Multicast HASH table */
3120 e_dbg("Zeroing the MTA\n");
3121 for (i = 0; i < mac->mta_reg_count; i++)
3122 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3123
3124 /*
3125 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3126 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3127 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3128 */
3129 if (hw->phy.type == e1000_phy_82578) {
3130 e1e_rphy(hw, BM_WUC, &i);
3131 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3132 if (ret_val)
3133 return ret_val;
3134 }
3135
3136 /* Setup link and flow control */
3137 ret_val = e1000_setup_link_ich8lan(hw);
3138
3139 /* Set the transmit descriptor write-back policy for both queues */
3140 txdctl = er32(TXDCTL(0));
3141 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3142 E1000_TXDCTL_FULL_TX_DESC_WB;
3143 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3144 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3145 ew32(TXDCTL(0), txdctl);
3146 txdctl = er32(TXDCTL(1));
3147 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3148 E1000_TXDCTL_FULL_TX_DESC_WB;
3149 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3150 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3151 ew32(TXDCTL(1), txdctl);
3152
3153 /*
3154 * ICH8 has opposite polarity of no_snoop bits.
3155 * By default, we should use snoop behavior.
3156 */
3157 if (mac->type == e1000_ich8lan)
3158 snoop = PCIE_ICH8_SNOOP_ALL;
3159 else
3160 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3161 e1000e_set_pcie_no_snoop(hw, snoop);
3162
3163 ctrl_ext = er32(CTRL_EXT);
3164 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3165 ew32(CTRL_EXT, ctrl_ext);
3166
3167 /*
3168 * Clear all of the statistics registers (clear on read). It is
3169 * important that we do this after we have tried to establish link
3170 * because the symbol error count will increment wildly if there
3171 * is no link.
3172 */
3173 e1000_clear_hw_cntrs_ich8lan(hw);
3174
3175 return 0;
3176 }
3177 /**
3178 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3179 * @hw: pointer to the HW structure
3180 *
3181 * Sets/Clears required hardware bits necessary for correctly setting up the
3182 * hardware for transmit and receive.
3183 **/
3184 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3185 {
3186 u32 reg;
3187
3188 /* Extended Device Control */
3189 reg = er32(CTRL_EXT);
3190 reg |= (1 << 22);
3191 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3192 if (hw->mac.type >= e1000_pchlan)
3193 reg |= E1000_CTRL_EXT_PHYPDEN;
3194 ew32(CTRL_EXT, reg);
3195
3196 /* Transmit Descriptor Control 0 */
3197 reg = er32(TXDCTL(0));
3198 reg |= (1 << 22);
3199 ew32(TXDCTL(0), reg);
3200
3201 /* Transmit Descriptor Control 1 */
3202 reg = er32(TXDCTL(1));
3203 reg |= (1 << 22);
3204 ew32(TXDCTL(1), reg);
3205
3206 /* Transmit Arbitration Control 0 */
3207 reg = er32(TARC(0));
3208 if (hw->mac.type == e1000_ich8lan)
3209 reg |= (1 << 28) | (1 << 29);
3210 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3211 ew32(TARC(0), reg);
3212
3213 /* Transmit Arbitration Control 1 */
3214 reg = er32(TARC(1));
3215 if (er32(TCTL) & E1000_TCTL_MULR)
3216 reg &= ~(1 << 28);
3217 else
3218 reg |= (1 << 28);
3219 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3220 ew32(TARC(1), reg);
3221
3222 /* Device Status */
3223 if (hw->mac.type == e1000_ich8lan) {
3224 reg = er32(STATUS);
3225 reg &= ~(1 << 31);
3226 ew32(STATUS, reg);
3227 }
3228
3229 /*
3230 * work-around descriptor data corruption issue during nfs v2 udp
3231 * traffic, just disable the nfs filtering capability
3232 */
3233 reg = er32(RFCTL);
3234 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3235 ew32(RFCTL, reg);
3236 }
3237
3238 /**
3239 * e1000_setup_link_ich8lan - Setup flow control and link settings
3240 * @hw: pointer to the HW structure
3241 *
3242 * Determines which flow control settings to use, then configures flow
3243 * control. Calls the appropriate media-specific link configuration
3244 * function. Assuming the adapter has a valid link partner, a valid link
3245 * should be established. Assumes the hardware has previously been reset
3246 * and the transmitter and receiver are not enabled.
3247 **/
3248 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3249 {
3250 s32 ret_val;
3251
3252 if (e1000_check_reset_block(hw))
3253 return 0;
3254
3255 /*
3256 * ICH parts do not have a word in the NVM to determine
3257 * the default flow control setting, so we explicitly
3258 * set it to full.
3259 */
3260 if (hw->fc.requested_mode == e1000_fc_default) {
3261 /* Workaround h/w hang when Tx flow control enabled */
3262 if (hw->mac.type == e1000_pchlan)
3263 hw->fc.requested_mode = e1000_fc_rx_pause;
3264 else
3265 hw->fc.requested_mode = e1000_fc_full;
3266 }
3267
3268 /*
3269 * Save off the requested flow control mode for use later. Depending
3270 * on the link partner's capabilities, we may or may not use this mode.
3271 */
3272 hw->fc.current_mode = hw->fc.requested_mode;
3273
3274 e_dbg("After fix-ups FlowControl is now = %x\n",
3275 hw->fc.current_mode);
3276
3277 /* Continue to configure the copper link. */
3278 ret_val = e1000_setup_copper_link_ich8lan(hw);
3279 if (ret_val)
3280 return ret_val;
3281
3282 ew32(FCTTV, hw->fc.pause_time);
3283 if ((hw->phy.type == e1000_phy_82578) ||
3284 (hw->phy.type == e1000_phy_82579) ||
3285 (hw->phy.type == e1000_phy_82577)) {
3286 ew32(FCRTV_PCH, hw->fc.refresh_time);
3287
3288 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3289 hw->fc.pause_time);
3290 if (ret_val)
3291 return ret_val;
3292 }
3293
3294 return e1000e_set_fc_watermarks(hw);
3295 }
3296
3297 /**
3298 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3299 * @hw: pointer to the HW structure
3300 *
3301 * Configures the kumeran interface to the PHY to wait the appropriate time
3302 * when polling the PHY, then call the generic setup_copper_link to finish
3303 * configuring the copper link.
3304 **/
3305 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3306 {
3307 u32 ctrl;
3308 s32 ret_val;
3309 u16 reg_data;
3310
3311 ctrl = er32(CTRL);
3312 ctrl |= E1000_CTRL_SLU;
3313 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3314 ew32(CTRL, ctrl);
3315
3316 /*
3317 * Set the mac to wait the maximum time between each iteration
3318 * and increase the max iterations when polling the phy;
3319 * this fixes erroneous timeouts at 10Mbps.
3320 */
3321 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3322 if (ret_val)
3323 return ret_val;
3324 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3325 &reg_data);
3326 if (ret_val)
3327 return ret_val;
3328 reg_data |= 0x3F;
3329 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3330 reg_data);
3331 if (ret_val)
3332 return ret_val;
3333
3334 switch (hw->phy.type) {
3335 case e1000_phy_igp_3:
3336 ret_val = e1000e_copper_link_setup_igp(hw);
3337 if (ret_val)
3338 return ret_val;
3339 break;
3340 case e1000_phy_bm:
3341 case e1000_phy_82578:
3342 ret_val = e1000e_copper_link_setup_m88(hw);
3343 if (ret_val)
3344 return ret_val;
3345 break;
3346 case e1000_phy_82577:
3347 case e1000_phy_82579:
3348 ret_val = e1000_copper_link_setup_82577(hw);
3349 if (ret_val)
3350 return ret_val;
3351 break;
3352 case e1000_phy_ife:
3353 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3354 if (ret_val)
3355 return ret_val;
3356
3357 reg_data &= ~IFE_PMC_AUTO_MDIX;
3358
3359 switch (hw->phy.mdix) {
3360 case 1:
3361 reg_data &= ~IFE_PMC_FORCE_MDIX;
3362 break;
3363 case 2:
3364 reg_data |= IFE_PMC_FORCE_MDIX;
3365 break;
3366 case 0:
3367 default:
3368 reg_data |= IFE_PMC_AUTO_MDIX;
3369 break;
3370 }
3371 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3372 if (ret_val)
3373 return ret_val;
3374 break;
3375 default:
3376 break;
3377 }
3378 return e1000e_setup_copper_link(hw);
3379 }
3380
3381 /**
3382 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3383 * @hw: pointer to the HW structure
3384 * @speed: pointer to store current link speed
3385 * @duplex: pointer to store the current link duplex
3386 *
3387 * Calls the generic get_speed_and_duplex to retrieve the current link
3388 * information and then calls the Kumeran lock loss workaround for links at
3389 * gigabit speeds.
3390 **/
3391 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3392 u16 *duplex)
3393 {
3394 s32 ret_val;
3395
3396 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3397 if (ret_val)
3398 return ret_val;
3399
3400 if ((hw->mac.type == e1000_ich8lan) &&
3401 (hw->phy.type == e1000_phy_igp_3) &&
3402 (*speed == SPEED_1000)) {
3403 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3404 }
3405
3406 return ret_val;
3407 }
3408
3409 /**
3410 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3411 * @hw: pointer to the HW structure
3412 *
3413 * Work-around for 82566 Kumeran PCS lock loss:
3414 * On link status change (i.e. PCI reset, speed change) and link is up and
3415 * speed is gigabit-
3416 * 0) if workaround is optionally disabled do nothing
3417 * 1) wait 1ms for Kumeran link to come up
3418 * 2) check Kumeran Diagnostic register PCS lock loss bit
3419 * 3) if not set the link is locked (all is good), otherwise...
3420 * 4) reset the PHY
3421 * 5) repeat up to 10 times
3422 * Note: this is only called for IGP3 copper when speed is 1gb.
3423 **/
3424 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3425 {
3426 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3427 u32 phy_ctrl;
3428 s32 ret_val;
3429 u16 i, data;
3430 bool link;
3431
3432 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3433 return 0;
3434
3435 /*
3436 * Make sure link is up before proceeding. If not just return.
3437 * Attempting this while link is negotiating fouled up link
3438 * stability
3439 */
3440 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3441 if (!link)
3442 return 0;
3443
3444 for (i = 0; i < 10; i++) {
3445 /* read once to clear */
3446 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3447 if (ret_val)
3448 return ret_val;
3449 /* and again to get new status */
3450 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3451 if (ret_val)
3452 return ret_val;
3453
3454 /* check for PCS lock */
3455 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3456 return 0;
3457
3458 /* Issue PHY reset */
3459 e1000_phy_hw_reset(hw);
3460 mdelay(5);
3461 }
3462 /* Disable GigE link negotiation */
3463 phy_ctrl = er32(PHY_CTRL);
3464 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3465 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3466 ew32(PHY_CTRL, phy_ctrl);
3467
3468 /*
3469 * Call gig speed drop workaround on Gig disable before accessing
3470 * any PHY registers
3471 */
3472 e1000e_gig_downshift_workaround_ich8lan(hw);
3473
3474 /* unable to acquire PCS lock */
3475 return -E1000_ERR_PHY;
3476 }
3477
3478 /**
3479 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3480 * @hw: pointer to the HW structure
3481 * @state: boolean value used to set the current Kumeran workaround state
3482 *
3483 * If ICH8, set the current Kumeran workaround state (enabled - true
3484 * /disabled - false).
3485 **/
3486 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3487 bool state)
3488 {
3489 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3490
3491 if (hw->mac.type != e1000_ich8lan) {
3492 e_dbg("Workaround applies to ICH8 only.\n");
3493 return;
3494 }
3495
3496 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3497 }
3498
3499 /**
3500 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3501 * @hw: pointer to the HW structure
3502 *
3503 * Workaround for 82566 power-down on D3 entry:
3504 * 1) disable gigabit link
3505 * 2) write VR power-down enable
3506 * 3) read it back
3507 * Continue if successful, else issue LCD reset and repeat
3508 **/
3509 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3510 {
3511 u32 reg;
3512 u16 data;
3513 u8 retry = 0;
3514
3515 if (hw->phy.type != e1000_phy_igp_3)
3516 return;
3517
3518 /* Try the workaround twice (if needed) */
3519 do {
3520 /* Disable link */
3521 reg = er32(PHY_CTRL);
3522 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3523 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3524 ew32(PHY_CTRL, reg);
3525
3526 /*
3527 * Call gig speed drop workaround on Gig disable before
3528 * accessing any PHY registers
3529 */
3530 if (hw->mac.type == e1000_ich8lan)
3531 e1000e_gig_downshift_workaround_ich8lan(hw);
3532
3533 /* Write VR power-down enable */
3534 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3535 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3536 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3537
3538 /* Read it back and test */
3539 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3540 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3541 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3542 break;
3543
3544 /* Issue PHY reset and repeat at most one more time */
3545 reg = er32(CTRL);
3546 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3547 retry++;
3548 } while (retry);
3549 }
3550
3551 /**
3552 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3553 * @hw: pointer to the HW structure
3554 *
3555 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3556 * LPLU, Gig disable, MDIC PHY reset):
3557 * 1) Set Kumeran Near-end loopback
3558 * 2) Clear Kumeran Near-end loopback
3559 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3560 **/
3561 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3562 {
3563 s32 ret_val;
3564 u16 reg_data;
3565
3566 if ((hw->mac.type != e1000_ich8lan) ||
3567 (hw->phy.type != e1000_phy_igp_3))
3568 return;
3569
3570 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3571 &reg_data);
3572 if (ret_val)
3573 return;
3574 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3575 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3576 reg_data);
3577 if (ret_val)
3578 return;
3579 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3580 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3581 reg_data);
3582 }
3583
3584 /**
3585 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3586 * @hw: pointer to the HW structure
3587 *
3588 * During S0 to Sx transition, it is possible the link remains at gig
3589 * instead of negotiating to a lower speed. Before going to Sx, set
3590 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3591 * to a lower speed.
3592 *
3593 * Should only be called for applicable parts.
3594 **/
3595 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3596 {
3597 u32 phy_ctrl;
3598 s32 ret_val;
3599
3600 phy_ctrl = er32(PHY_CTRL);
3601 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3602 ew32(PHY_CTRL, phy_ctrl);
3603
3604 if (hw->mac.type >= e1000_pchlan) {
3605 e1000_oem_bits_config_ich8lan(hw, false);
3606 ret_val = hw->phy.ops.acquire(hw);
3607 if (ret_val)
3608 return;
3609 e1000_write_smbus_addr(hw);
3610 hw->phy.ops.release(hw);
3611 }
3612 }
3613
3614 /**
3615 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3616 * @hw: pointer to the HW structure
3617 *
3618 * Return the LED back to the default configuration.
3619 **/
3620 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3621 {
3622 if (hw->phy.type == e1000_phy_ife)
3623 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3624
3625 ew32(LEDCTL, hw->mac.ledctl_default);
3626 return 0;
3627 }
3628
3629 /**
3630 * e1000_led_on_ich8lan - Turn LEDs on
3631 * @hw: pointer to the HW structure
3632 *
3633 * Turn on the LEDs.
3634 **/
3635 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3636 {
3637 if (hw->phy.type == e1000_phy_ife)
3638 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3639 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3640
3641 ew32(LEDCTL, hw->mac.ledctl_mode2);
3642 return 0;
3643 }
3644
3645 /**
3646 * e1000_led_off_ich8lan - Turn LEDs off
3647 * @hw: pointer to the HW structure
3648 *
3649 * Turn off the LEDs.
3650 **/
3651 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3652 {
3653 if (hw->phy.type == e1000_phy_ife)
3654 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3655 (IFE_PSCL_PROBE_MODE |
3656 IFE_PSCL_PROBE_LEDS_OFF));
3657
3658 ew32(LEDCTL, hw->mac.ledctl_mode1);
3659 return 0;
3660 }
3661
3662 /**
3663 * e1000_setup_led_pchlan - Configures SW controllable LED
3664 * @hw: pointer to the HW structure
3665 *
3666 * This prepares the SW controllable LED for use.
3667 **/
3668 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3669 {
3670 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3671 }
3672
3673 /**
3674 * e1000_cleanup_led_pchlan - Restore the default LED operation
3675 * @hw: pointer to the HW structure
3676 *
3677 * Return the LED back to the default configuration.
3678 **/
3679 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3680 {
3681 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3682 }
3683
3684 /**
3685 * e1000_led_on_pchlan - Turn LEDs on
3686 * @hw: pointer to the HW structure
3687 *
3688 * Turn on the LEDs.
3689 **/
3690 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3691 {
3692 u16 data = (u16)hw->mac.ledctl_mode2;
3693 u32 i, led;
3694
3695 /*
3696 * If no link, then turn LED on by setting the invert bit
3697 * for each LED that's mode is "link_up" in ledctl_mode2.
3698 */
3699 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3700 for (i = 0; i < 3; i++) {
3701 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3702 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3703 E1000_LEDCTL_MODE_LINK_UP)
3704 continue;
3705 if (led & E1000_PHY_LED0_IVRT)
3706 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3707 else
3708 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3709 }
3710 }
3711
3712 return e1e_wphy(hw, HV_LED_CONFIG, data);
3713 }
3714
3715 /**
3716 * e1000_led_off_pchlan - Turn LEDs off
3717 * @hw: pointer to the HW structure
3718 *
3719 * Turn off the LEDs.
3720 **/
3721 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3722 {
3723 u16 data = (u16)hw->mac.ledctl_mode1;
3724 u32 i, led;
3725
3726 /*
3727 * If no link, then turn LED off by clearing the invert bit
3728 * for each LED that's mode is "link_up" in ledctl_mode1.
3729 */
3730 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3731 for (i = 0; i < 3; i++) {
3732 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3733 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3734 E1000_LEDCTL_MODE_LINK_UP)
3735 continue;
3736 if (led & E1000_PHY_LED0_IVRT)
3737 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3738 else
3739 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3740 }
3741 }
3742
3743 return e1e_wphy(hw, HV_LED_CONFIG, data);
3744 }
3745
3746 /**
3747 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3748 * @hw: pointer to the HW structure
3749 *
3750 * Read appropriate register for the config done bit for completion status
3751 * and configure the PHY through s/w for EEPROM-less parts.
3752 *
3753 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3754 * config done bit, so only an error is logged and continues. If we were
3755 * to return with error, EEPROM-less silicon would not be able to be reset
3756 * or change link.
3757 **/
3758 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3759 {
3760 s32 ret_val = 0;
3761 u32 bank = 0;
3762 u32 status;
3763
3764 e1000e_get_cfg_done(hw);
3765
3766 /* Wait for indication from h/w that it has completed basic config */
3767 if (hw->mac.type >= e1000_ich10lan) {
3768 e1000_lan_init_done_ich8lan(hw);
3769 } else {
3770 ret_val = e1000e_get_auto_rd_done(hw);
3771 if (ret_val) {
3772 /*
3773 * When auto config read does not complete, do not
3774 * return with an error. This can happen in situations
3775 * where there is no eeprom and prevents getting link.
3776 */
3777 e_dbg("Auto Read Done did not complete\n");
3778 ret_val = 0;
3779 }
3780 }
3781
3782 /* Clear PHY Reset Asserted bit */
3783 status = er32(STATUS);
3784 if (status & E1000_STATUS_PHYRA)
3785 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3786 else
3787 e_dbg("PHY Reset Asserted not set - needs delay\n");
3788
3789 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3790 if (hw->mac.type <= e1000_ich9lan) {
3791 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3792 (hw->phy.type == e1000_phy_igp_3)) {
3793 e1000e_phy_init_script_igp3(hw);
3794 }
3795 } else {
3796 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3797 /* Maybe we should do a basic PHY config */
3798 e_dbg("EEPROM not present\n");
3799 ret_val = -E1000_ERR_CONFIG;
3800 }
3801 }
3802
3803 return ret_val;
3804 }
3805
3806 /**
3807 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3808 * @hw: pointer to the HW structure
3809 *
3810 * In the case of a PHY power down to save power, or to turn off link during a
3811 * driver unload, or wake on lan is not enabled, remove the link.
3812 **/
3813 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3814 {
3815 /* If the management interface is not enabled, then power down */
3816 if (!(hw->mac.ops.check_mng_mode(hw) ||
3817 hw->phy.ops.check_reset_block(hw)))
3818 e1000_power_down_phy_copper(hw);
3819 }
3820
3821 /**
3822 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3823 * @hw: pointer to the HW structure
3824 *
3825 * Clears hardware counters specific to the silicon family and calls
3826 * clear_hw_cntrs_generic to clear all general purpose counters.
3827 **/
3828 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3829 {
3830 u16 phy_data;
3831
3832 e1000e_clear_hw_cntrs_base(hw);
3833
3834 er32(ALGNERRC);
3835 er32(RXERRC);
3836 er32(TNCRS);
3837 er32(CEXTERR);
3838 er32(TSCTC);
3839 er32(TSCTFC);
3840
3841 er32(MGTPRC);
3842 er32(MGTPDC);
3843 er32(MGTPTC);
3844
3845 er32(IAC);
3846 er32(ICRXOC);
3847
3848 /* Clear PHY statistics registers */
3849 if ((hw->phy.type == e1000_phy_82578) ||
3850 (hw->phy.type == e1000_phy_82579) ||
3851 (hw->phy.type == e1000_phy_82577)) {
3852 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3853 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3854 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3855 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3856 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3857 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3858 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3859 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3860 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3861 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3862 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3863 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3864 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3865 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3866 }
3867 }
3868
3869 static struct e1000_mac_operations ich8_mac_ops = {
3870 .id_led_init = e1000e_id_led_init,
3871 /* check_mng_mode dependent on mac type */
3872 .check_for_link = e1000_check_for_copper_link_ich8lan,
3873 /* cleanup_led dependent on mac type */
3874 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3875 .get_bus_info = e1000_get_bus_info_ich8lan,
3876 .set_lan_id = e1000_set_lan_id_single_port,
3877 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3878 /* led_on dependent on mac type */
3879 /* led_off dependent on mac type */
3880 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3881 .reset_hw = e1000_reset_hw_ich8lan,
3882 .init_hw = e1000_init_hw_ich8lan,
3883 .setup_link = e1000_setup_link_ich8lan,
3884 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3885 /* id_led_init dependent on mac type */
3886 };
3887
3888 static struct e1000_phy_operations ich8_phy_ops = {
3889 .acquire = e1000_acquire_swflag_ich8lan,
3890 .check_reset_block = e1000_check_reset_block_ich8lan,
3891 .commit = NULL,
3892 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3893 .get_cable_length = e1000e_get_cable_length_igp_2,
3894 .read_reg = e1000e_read_phy_reg_igp,
3895 .release = e1000_release_swflag_ich8lan,
3896 .reset = e1000_phy_hw_reset_ich8lan,
3897 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3898 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3899 .write_reg = e1000e_write_phy_reg_igp,
3900 };
3901
3902 static struct e1000_nvm_operations ich8_nvm_ops = {
3903 .acquire = e1000_acquire_nvm_ich8lan,
3904 .read = e1000_read_nvm_ich8lan,
3905 .release = e1000_release_nvm_ich8lan,
3906 .update = e1000_update_nvm_checksum_ich8lan,
3907 .valid_led_default = e1000_valid_led_default_ich8lan,
3908 .validate = e1000_validate_nvm_checksum_ich8lan,
3909 .write = e1000_write_nvm_ich8lan,
3910 };
3911
3912 struct e1000_info e1000_ich8_info = {
3913 .mac = e1000_ich8lan,
3914 .flags = FLAG_HAS_WOL
3915 | FLAG_IS_ICH
3916 | FLAG_RX_CSUM_ENABLED
3917 | FLAG_HAS_CTRLEXT_ON_LOAD
3918 | FLAG_HAS_AMT
3919 | FLAG_HAS_FLASH
3920 | FLAG_APME_IN_WUC,
3921 .pba = 8,
3922 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3923 .get_variants = e1000_get_variants_ich8lan,
3924 .mac_ops = &ich8_mac_ops,
3925 .phy_ops = &ich8_phy_ops,
3926 .nvm_ops = &ich8_nvm_ops,
3927 };
3928
3929 struct e1000_info e1000_ich9_info = {
3930 .mac = e1000_ich9lan,
3931 .flags = FLAG_HAS_JUMBO_FRAMES
3932 | FLAG_IS_ICH
3933 | FLAG_HAS_WOL
3934 | FLAG_RX_CSUM_ENABLED
3935 | FLAG_HAS_CTRLEXT_ON_LOAD
3936 | FLAG_HAS_AMT
3937 | FLAG_HAS_ERT
3938 | FLAG_HAS_FLASH
3939 | FLAG_APME_IN_WUC,
3940 .pba = 10,
3941 .max_hw_frame_size = DEFAULT_JUMBO,
3942 .get_variants = e1000_get_variants_ich8lan,
3943 .mac_ops = &ich8_mac_ops,
3944 .phy_ops = &ich8_phy_ops,
3945 .nvm_ops = &ich8_nvm_ops,
3946 };
3947
3948 struct e1000_info e1000_ich10_info = {
3949 .mac = e1000_ich10lan,
3950 .flags = FLAG_HAS_JUMBO_FRAMES
3951 | FLAG_IS_ICH
3952 | FLAG_HAS_WOL
3953 | FLAG_RX_CSUM_ENABLED
3954 | FLAG_HAS_CTRLEXT_ON_LOAD
3955 | FLAG_HAS_AMT
3956 | FLAG_HAS_ERT
3957 | FLAG_HAS_FLASH
3958 | FLAG_APME_IN_WUC,
3959 .pba = 10,
3960 .max_hw_frame_size = DEFAULT_JUMBO,
3961 .get_variants = e1000_get_variants_ich8lan,
3962 .mac_ops = &ich8_mac_ops,
3963 .phy_ops = &ich8_phy_ops,
3964 .nvm_ops = &ich8_nvm_ops,
3965 };
3966
3967 struct e1000_info e1000_pch_info = {
3968 .mac = e1000_pchlan,
3969 .flags = FLAG_IS_ICH
3970 | FLAG_HAS_WOL
3971 | FLAG_RX_CSUM_ENABLED
3972 | FLAG_HAS_CTRLEXT_ON_LOAD
3973 | FLAG_HAS_AMT
3974 | FLAG_HAS_FLASH
3975 | FLAG_HAS_JUMBO_FRAMES
3976 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3977 | FLAG_APME_IN_WUC,
3978 .flags2 = FLAG2_HAS_PHY_STATS,
3979 .pba = 26,
3980 .max_hw_frame_size = 4096,
3981 .get_variants = e1000_get_variants_ich8lan,
3982 .mac_ops = &ich8_mac_ops,
3983 .phy_ops = &ich8_phy_ops,
3984 .nvm_ops = &ich8_nvm_ops,
3985 };
3986
3987 struct e1000_info e1000_pch2_info = {
3988 .mac = e1000_pch2lan,
3989 .flags = FLAG_IS_ICH
3990 | FLAG_HAS_WOL
3991 | FLAG_RX_CSUM_ENABLED
3992 | FLAG_HAS_CTRLEXT_ON_LOAD
3993 | FLAG_HAS_AMT
3994 | FLAG_HAS_FLASH
3995 | FLAG_HAS_JUMBO_FRAMES
3996 | FLAG_APME_IN_WUC,
3997 .flags2 = FLAG2_HAS_PHY_STATS
3998 | FLAG2_HAS_EEE,
3999 .pba = 26,
4000 .max_hw_frame_size = DEFAULT_JUMBO,
4001 .get_variants = e1000_get_variants_ich8lan,
4002 .mac_ops = &ich8_mac_ops,
4003 .phy_ops = &ich8_phy_ops,
4004 .nvm_ops = &ich8_nvm_ops,
4005 };
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