?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / net / qlcnic / qlcnic.h
blobb0dead00b2d1d6b7809bd2b01906b5bff5a786b5
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32
33 #include "qlcnic_hdr.h"
34
35 #define _QLCNIC_LINUX_MAJOR 5
36 #define _QLCNIC_LINUX_MINOR 0
37 #define _QLCNIC_LINUX_SUBVERSION 15
38 #define QLCNIC_LINUX_VERSIONID "5.0.15"
39 #define QLCNIC_DRV_IDC_VER 0x01
40 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
41 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
42
43 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
44 #define _major(v) (((v) >> 24) & 0xff)
45 #define _minor(v) (((v) >> 16) & 0xff)
46 #define _build(v) ((v) & 0xffff)
47
48 /* version in image has weird encoding:
49 * 7:0 - major
50 * 15:8 - minor
51 * 31:16 - build (little endian)
52 */
53 #define QLCNIC_DECODE_VERSION(v) \
54 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
55
56 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
57 #define QLCNIC_NUM_FLASH_SECTORS (64)
58 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
59 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
60 * QLCNIC_FLASH_SECTOR_SIZE)
61
62 #define RCV_DESC_RINGSIZE(rds_ring) \
63 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
64 #define RCV_BUFF_RINGSIZE(rds_ring) \
65 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
66 #define STATUS_DESC_RINGSIZE(sds_ring) \
67 (sizeof(struct status_desc) * (sds_ring)->num_desc)
68 #define TX_BUFF_RINGSIZE(tx_ring) \
69 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
70 #define TX_DESC_RINGSIZE(tx_ring) \
71 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
72
73 #define QLCNIC_P3P_A0 0x50
74
75 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
76
77 #define FIRST_PAGE_GROUP_START 0
78 #define FIRST_PAGE_GROUP_END 0x100000
79
80 #define P3P_MAX_MTU (9600)
81 #define P3P_MIN_MTU (68)
82 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
83
84 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
85 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
86 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
87 #define QLCNIC_LRO_BUFFER_EXTRA 2048
88
89 /* Opcodes to be used with the commands */
90 #define TX_ETHER_PKT 0x01
91 #define TX_TCP_PKT 0x02
92 #define TX_UDP_PKT 0x03
93 #define TX_IP_PKT 0x04
94 #define TX_TCP_LSO 0x05
95 #define TX_TCP_LSO6 0x06
96 #define TX_IPSEC 0x07
97 #define TX_IPSEC_CMD 0x0a
98 #define TX_TCPV6_PKT 0x0b
99 #define TX_UDPV6_PKT 0x0c
100
101 /* Tx defines */
102 #define QLCNIC_MAX_FRAGS_PER_TX 14
103 #define MAX_TSO_HEADER_DESC 2
104 #define MGMT_CMD_DESC_RESV 4
105 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
106 + MGMT_CMD_DESC_RESV)
107 #define QLCNIC_MAX_TX_TIMEOUTS 2
108
109 /*
110 * Following are the states of the Phantom. Phantom will set them and
111 * Host will read to check if the fields are correct.
112 */
113 #define PHAN_INITIALIZE_FAILED 0xffff
114 #define PHAN_INITIALIZE_COMPLETE 0xff01
115
116 /* Host writes the following to notify that it has done the init-handshake */
117 #define PHAN_INITIALIZE_ACK 0xf00f
118 #define PHAN_PEG_RCV_INITIALIZED 0xff01
119
120 #define NUM_RCV_DESC_RINGS 3
121 #define NUM_STS_DESC_RINGS 4
122
123 #define RCV_RING_NORMAL 0
124 #define RCV_RING_JUMBO 1
125
126 #define MIN_CMD_DESCRIPTORS 64
127 #define MIN_RCV_DESCRIPTORS 64
128 #define MIN_JUMBO_DESCRIPTORS 32
129
130 #define MAX_CMD_DESCRIPTORS 1024
131 #define MAX_RCV_DESCRIPTORS_1G 4096
132 #define MAX_RCV_DESCRIPTORS_10G 8192
133 #define MAX_RCV_DESCRIPTORS_VF 2048
134 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
135 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
136
137 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
138 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
139 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
140 #define MAX_RDS_RINGS 2
141
142 #define get_next_index(index, length) \
143 (((index) + 1) & ((length) - 1))
144
145 /*
146 * Following data structures describe the descriptors that will be used.
147 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
148 * we are doing LSO (above the 1500 size packet) only.
149 */
150
151 #define FLAGS_VLAN_TAGGED 0x10
152 #define FLAGS_VLAN_OOB 0x40
153
154 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
155 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
156 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
158 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160
161 #define qlcnic_set_tx_port(_desc, _port) \
162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163
164 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
165 ((_desc)->flags_opcode |= \
166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167
168 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
169 ((_desc)->nfrags__length = \
170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171
172 struct cmd_desc_type0 {
173 u8 tcp_hdr_offset; /* For LSO only */
174 u8 ip_hdr_offset; /* For LSO only */
175 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
176 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
177
178 __le64 addr_buffer2;
179
180 __le16 reference_handle;
181 __le16 mss;
182 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
183 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
184 __le16 conn_id; /* IPSec offoad only */
185
186 __le64 addr_buffer3;
187 __le64 addr_buffer1;
188
189 __le16 buffer_length[4];
190
191 __le64 addr_buffer4;
192
193 u8 eth_addr[ETH_ALEN];
194 __le16 vlan_TCI;
195
196 } __attribute__ ((aligned(64)));
197
198 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
199 struct rcv_desc {
200 __le16 reference_handle;
201 __le16 reserved;
202 __le32 buffer_length; /* allocated buffer length (usually 2K) */
203 __le64 addr_buffer;
204 };
205
206 /* opcode field in status_desc */
207 #define QLCNIC_SYN_OFFLOAD 0x03
208 #define QLCNIC_RXPKT_DESC 0x04
209 #define QLCNIC_OLD_RXPKT_DESC 0x3f
210 #define QLCNIC_RESPONSE_DESC 0x05
211 #define QLCNIC_LRO_DESC 0x12
212
213 /* for status field in status_desc */
214 #define STATUS_CKSUM_LOOP 0
215 #define STATUS_CKSUM_OK 2
216
217 /* owner bits of status_desc */
218 #define STATUS_OWNER_HOST (0x1ULL << 56)
219 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220
221 /* Status descriptor:
222 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
223 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
224 53-55 desc_cnt, 56-57 owner, 58-63 opcode
225 */
226 #define qlcnic_get_sts_port(sts_data) \
227 ((sts_data) & 0x0F)
228 #define qlcnic_get_sts_status(sts_data) \
229 (((sts_data) >> 4) & 0x0F)
230 #define qlcnic_get_sts_type(sts_data) \
231 (((sts_data) >> 8) & 0x0F)
232 #define qlcnic_get_sts_totallength(sts_data) \
233 (((sts_data) >> 12) & 0xFFFF)
234 #define qlcnic_get_sts_refhandle(sts_data) \
235 (((sts_data) >> 28) & 0xFFFF)
236 #define qlcnic_get_sts_prot(sts_data) \
237 (((sts_data) >> 44) & 0x0F)
238 #define qlcnic_get_sts_pkt_offset(sts_data) \
239 (((sts_data) >> 48) & 0x1F)
240 #define qlcnic_get_sts_desc_cnt(sts_data) \
241 (((sts_data) >> 53) & 0x7)
242 #define qlcnic_get_sts_opcode(sts_data) \
243 (((sts_data) >> 58) & 0x03F)
244
245 #define qlcnic_get_lro_sts_refhandle(sts_data) \
246 ((sts_data) & 0x0FFFF)
247 #define qlcnic_get_lro_sts_length(sts_data) \
248 (((sts_data) >> 16) & 0x0FFFF)
249 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
250 (((sts_data) >> 32) & 0x0FF)
251 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
252 (((sts_data) >> 40) & 0x0FF)
253 #define qlcnic_get_lro_sts_timestamp(sts_data) \
254 (((sts_data) >> 48) & 0x1)
255 #define qlcnic_get_lro_sts_type(sts_data) \
256 (((sts_data) >> 49) & 0x7)
257 #define qlcnic_get_lro_sts_push_flag(sts_data) \
258 (((sts_data) >> 52) & 0x1)
259 #define qlcnic_get_lro_sts_seq_number(sts_data) \
260 ((sts_data) & 0x0FFFFFFFF)
261
262
263 struct status_desc {
264 __le64 status_desc_data[2];
265 } __attribute__ ((aligned(16)));
266
267 /* UNIFIED ROMIMAGE */
268 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
269 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
270 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
271 #define QLCNIC_UNI_DIR_SECT_FW 0x7
272
273 /*Offsets */
274 #define QLCNIC_UNI_CHIP_REV_OFF 10
275 #define QLCNIC_UNI_FLAGS_OFF 11
276 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
277 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
278 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
279
280 struct uni_table_desc{
281 u32 findex;
282 u32 num_entries;
283 u32 entry_size;
284 u32 reserved[5];
285 };
286
287 struct uni_data_desc{
288 u32 findex;
289 u32 size;
290 u32 reserved[5];
291 };
292
293 /* Flash Defines and Structures */
294 #define QLCNIC_FLT_LOCATION 0x3F1000
295 #define QLCNIC_FW_IMAGE_REGION 0x74
296 struct qlcnic_flt_header {
297 u16 version;
298 u16 len;
299 u16 checksum;
300 u16 reserved;
301 };
302
303 struct qlcnic_flt_entry {
304 u8 region;
305 u8 reserved0;
306 u8 attrib;
307 u8 reserved1;
308 u32 size;
309 u32 start_addr;
310 u32 end_add;
311 };
312
313 /* Magic number to let user know flash is programmed */
314 #define QLCNIC_BDINFO_MAGIC 0x12345678
315
316 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
317 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
318 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
319 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
320 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
321 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
322 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
323 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
324 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
326 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
327 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
328 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
329 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
330
331 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
332
333 /* Flash memory map */
334 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
335 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
336 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
337 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
338
339 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
340 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
341 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
342 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
343
344 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
345 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
346
347 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
348 #define QLCNIC_UNIFIED_ROMIMAGE 0
349 #define QLCNIC_FLASH_ROMIMAGE 1
350 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
351
352 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
353 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
354
355 extern char qlcnic_driver_name[];
356
357 /* Number of status descriptors to handle per interrupt */
358 #define MAX_STATUS_HANDLE (64)
359
360 /*
361 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
362 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
363 */
364 struct qlcnic_skb_frag {
365 u64 dma;
366 u64 length;
367 };
368
369 struct qlcnic_recv_crb {
370 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
371 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
372 u32 sw_int_mask[NUM_STS_DESC_RINGS];
373 };
374
375 /* Following defines are for the state of the buffers */
376 #define QLCNIC_BUFFER_FREE 0
377 #define QLCNIC_BUFFER_BUSY 1
378
379 /*
380 * There will be one qlcnic_buffer per skb packet. These will be
381 * used to save the dma info for pci_unmap_page()
382 */
383 struct qlcnic_cmd_buffer {
384 struct sk_buff *skb;
385 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
386 u32 frag_count;
387 };
388
389 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
390 struct qlcnic_rx_buffer {
391 struct list_head list;
392 struct sk_buff *skb;
393 u64 dma;
394 u16 ref_handle;
395 };
396
397 /* Board types */
398 #define QLCNIC_GBE 0x01
399 #define QLCNIC_XGBE 0x02
400
401 /*
402 * One hardware_context{} per adapter
403 * contains interrupt info as well shared hardware info.
404 */
405 struct qlcnic_hardware_context {
406 void __iomem *pci_base0;
407 void __iomem *ocm_win_crb;
408
409 unsigned long pci_len0;
410
411 rwlock_t crb_lock;
412 struct mutex mem_lock;
413
414 u8 revision_id;
415 u8 pci_func;
416 u8 linkup;
417 u16 port_type;
418 u16 board_type;
419 };
420
421 struct qlcnic_adapter_stats {
422 u64 xmitcalled;
423 u64 xmitfinished;
424 u64 rxdropped;
425 u64 txdropped;
426 u64 csummed;
427 u64 rx_pkts;
428 u64 lro_pkts;
429 u64 rxbytes;
430 u64 txbytes;
431 u64 lrobytes;
432 u64 lso_frames;
433 u64 xmit_on;
434 u64 xmit_off;
435 u64 skb_alloc_failure;
436 u64 null_rxbuf;
437 u64 rx_dma_map_error;
438 u64 tx_dma_map_error;
439 };
440
441 /*
442 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
443 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
444 */
445 struct qlcnic_host_rds_ring {
446 u32 producer;
447 u32 num_desc;
448 u32 dma_size;
449 u32 skb_size;
450 u32 flags;
451 void __iomem *crb_rcv_producer;
452 struct rcv_desc *desc_head;
453 struct qlcnic_rx_buffer *rx_buf_arr;
454 struct list_head free_list;
455 spinlock_t lock;
456 dma_addr_t phys_addr;
457 };
458
459 struct qlcnic_host_sds_ring {
460 u32 consumer;
461 u32 num_desc;
462 void __iomem *crb_sts_consumer;
463 void __iomem *crb_intr_mask;
464
465 struct status_desc *desc_head;
466 struct qlcnic_adapter *adapter;
467 struct napi_struct napi;
468 struct list_head free_list[NUM_RCV_DESC_RINGS];
469
470 int irq;
471
472 dma_addr_t phys_addr;
473 char name[IFNAMSIZ+4];
474 };
475
476 struct qlcnic_host_tx_ring {
477 u32 producer;
478 __le32 *hw_consumer;
479 u32 sw_consumer;
480 void __iomem *crb_cmd_producer;
481 u32 num_desc;
482
483 struct netdev_queue *txq;
484
485 struct qlcnic_cmd_buffer *cmd_buf_arr;
486 struct cmd_desc_type0 *desc_head;
487 dma_addr_t phys_addr;
488 dma_addr_t hw_cons_phys_addr;
489 };
490
491 /*
492 * Receive context. There is one such structure per instance of the
493 * receive processing. Any state information that is relevant to
494 * the receive, and is must be in this structure. The global data may be
495 * present elsewhere.
496 */
497 struct qlcnic_recv_context {
498 u32 state;
499 u16 context_id;
500 u16 virt_port;
501
502 struct qlcnic_host_rds_ring *rds_rings;
503 struct qlcnic_host_sds_ring *sds_rings;
504 };
505
506 /* HW context creation */
507
508 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
509 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
510 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
511
512 #define QLCNIC_CDRP_CMD_BIT 0x80000000
513
514 /*
515 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
516 * in the crb QLCNIC_CDRP_CRB_OFFSET.
517 */
518 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
519 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
520
521 #define QLCNIC_CDRP_RSP_OK 0x00000001
522 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
523 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
524
525 /*
526 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
527 * the crb QLCNIC_CDRP_CRB_OFFSET.
528 */
529 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
530 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
531
532 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
533 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
534 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
535 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
536 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
537 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
538 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
539 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
540 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
541 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
542 #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e
543 #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f
544 #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010
545 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
546 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
547 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
548 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
549 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
550 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
551 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
552 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
553 #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a
554 #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b
555 #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
556 #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
557 #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
558 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
559
560 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
561 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
562 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
563 #define QLCNIC_CDRP_CMD_RESET_NPAR 0x00000023
564 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
565 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
566 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
567 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
568 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
569 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
570 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
571
572 #define QLCNIC_RCODE_SUCCESS 0
573 #define QLCNIC_RCODE_TIMEOUT 17
574 #define QLCNIC_DESTROY_CTX_RESET 0
575
576 /*
577 * Capabilities Announced
578 */
579 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
580 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
581 #define QLCNIC_CAP0_LSO (1 << 6)
582 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
583 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
584 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
585
586 /*
587 * Context state
588 */
589 #define QLCNIC_HOST_CTX_STATE_FREED 0
590 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
591
592 /*
593 * Rx context
594 */
595
596 struct qlcnic_hostrq_sds_ring {
597 __le64 host_phys_addr; /* Ring base addr */
598 __le32 ring_size; /* Ring entries */
599 __le16 msi_index;
600 __le16 rsvd; /* Padding */
601 };
602
603 struct qlcnic_hostrq_rds_ring {
604 __le64 host_phys_addr; /* Ring base addr */
605 __le64 buff_size; /* Packet buffer size */
606 __le32 ring_size; /* Ring entries */
607 __le32 ring_kind; /* Class of ring */
608 };
609
610 struct qlcnic_hostrq_rx_ctx {
611 __le64 host_rsp_dma_addr; /* Response dma'd here */
612 __le32 capabilities[4]; /* Flag bit vector */
613 __le32 host_int_crb_mode; /* Interrupt crb usage */
614 __le32 host_rds_crb_mode; /* RDS crb usage */
615 /* These ring offsets are relative to data[0] below */
616 __le32 rds_ring_offset; /* Offset to RDS config */
617 __le32 sds_ring_offset; /* Offset to SDS config */
618 __le16 num_rds_rings; /* Count of RDS rings */
619 __le16 num_sds_rings; /* Count of SDS rings */
620 __le16 valid_field_offset;
621 u8 txrx_sds_binding;
622 u8 msix_handler;
623 u8 reserved[128]; /* reserve space for future expansion*/
624 /* MUST BE 64-bit aligned.
625 The following is packed:
626 - N hostrq_rds_rings
627 - N hostrq_sds_rings */
628 char data[0];
629 };
630
631 struct qlcnic_cardrsp_rds_ring{
632 __le32 host_producer_crb; /* Crb to use */
633 __le32 rsvd1; /* Padding */
634 };
635
636 struct qlcnic_cardrsp_sds_ring {
637 __le32 host_consumer_crb; /* Crb to use */
638 __le32 interrupt_crb; /* Crb to use */
639 };
640
641 struct qlcnic_cardrsp_rx_ctx {
642 /* These ring offsets are relative to data[0] below */
643 __le32 rds_ring_offset; /* Offset to RDS config */
644 __le32 sds_ring_offset; /* Offset to SDS config */
645 __le32 host_ctx_state; /* Starting State */
646 __le32 num_fn_per_port; /* How many PCI fn share the port */
647 __le16 num_rds_rings; /* Count of RDS rings */
648 __le16 num_sds_rings; /* Count of SDS rings */
649 __le16 context_id; /* Handle for context */
650 u8 phys_port; /* Physical id of port */
651 u8 virt_port; /* Virtual/Logical id of port */
652 u8 reserved[128]; /* save space for future expansion */
653 /* MUST BE 64-bit aligned.
654 The following is packed:
655 - N cardrsp_rds_rings
656 - N cardrs_sds_rings */
657 char data[0];
658 };
659
660 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
661 (sizeof(HOSTRQ_RX) + \
662 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
663 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
664
665 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
666 (sizeof(CARDRSP_RX) + \
667 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
668 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
669
670 /*
671 * Tx context
672 */
673
674 struct qlcnic_hostrq_cds_ring {
675 __le64 host_phys_addr; /* Ring base addr */
676 __le32 ring_size; /* Ring entries */
677 __le32 rsvd; /* Padding */
678 };
679
680 struct qlcnic_hostrq_tx_ctx {
681 __le64 host_rsp_dma_addr; /* Response dma'd here */
682 __le64 cmd_cons_dma_addr; /* */
683 __le64 dummy_dma_addr; /* */
684 __le32 capabilities[4]; /* Flag bit vector */
685 __le32 host_int_crb_mode; /* Interrupt crb usage */
686 __le32 rsvd1; /* Padding */
687 __le16 rsvd2; /* Padding */
688 __le16 interrupt_ctl;
689 __le16 msi_index;
690 __le16 rsvd3; /* Padding */
691 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
692 u8 reserved[128]; /* future expansion */
693 };
694
695 struct qlcnic_cardrsp_cds_ring {
696 __le32 host_producer_crb; /* Crb to use */
697 __le32 interrupt_crb; /* Crb to use */
698 };
699
700 struct qlcnic_cardrsp_tx_ctx {
701 __le32 host_ctx_state; /* Starting state */
702 __le16 context_id; /* Handle for context */
703 u8 phys_port; /* Physical id of port */
704 u8 virt_port; /* Virtual/Logical id of port */
705 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
706 u8 reserved[128]; /* future expansion */
707 };
708
709 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
710 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
711
712 /* CRB */
713
714 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
715 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
716 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
717 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
718
719 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
720 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
721 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
722 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
723 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
724
725
726 /* MAC */
727
728 #define MC_COUNT_P3P 38
729
730 #define QLCNIC_MAC_NOOP 0
731 #define QLCNIC_MAC_ADD 1
732 #define QLCNIC_MAC_DEL 2
733 #define QLCNIC_MAC_VLAN_ADD 3
734 #define QLCNIC_MAC_VLAN_DEL 4
735
736 struct qlcnic_mac_list_s {
737 struct list_head list;
738 uint8_t mac_addr[ETH_ALEN+2];
739 };
740
741 /*
742 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
743 * adjusted based on configured MTU.
744 */
745 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
746 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
747 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
748 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
749
750 #define QLCNIC_INTR_DEFAULT 0x04
751
752 union qlcnic_nic_intr_coalesce_data {
753 struct {
754 u16 rx_packets;
755 u16 rx_time_us;
756 u16 tx_packets;
757 u16 tx_time_us;
758 } data;
759 u64 word;
760 };
761
762 struct qlcnic_nic_intr_coalesce {
763 u16 stats_time_us;
764 u16 rate_sample_time;
765 u16 flags;
766 u16 rsvd_1;
767 u32 low_threshold;
768 u32 high_threshold;
769 union qlcnic_nic_intr_coalesce_data normal;
770 union qlcnic_nic_intr_coalesce_data low;
771 union qlcnic_nic_intr_coalesce_data high;
772 union qlcnic_nic_intr_coalesce_data irq;
773 };
774
775 #define QLCNIC_HOST_REQUEST 0x13
776 #define QLCNIC_REQUEST 0x14
777
778 #define QLCNIC_MAC_EVENT 0x1
779
780 #define QLCNIC_IP_UP 2
781 #define QLCNIC_IP_DOWN 3
782
783 /*
784 * Driver --> Firmware
785 */
786 #define QLCNIC_H2C_OPCODE_START 0
787 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1
788 #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2
789 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
790 #define QLCNIC_H2C_OPCODE_CONFIG_LED 4
791 #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
792 #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6
793 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7
794 #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8
795 #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9
796 #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
797 #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11
798 #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
799 #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
800 #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
801 #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
802 #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16
803 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
804 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18
805 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20
806 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21
807 #define QLCNIC_C2C_OPCODE 22
808 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23
809 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24
810 #define QLCNIC_H2C_OPCODE_LAST 25
811 /*
812 * Firmware --> Driver
813 */
814
815 #define QLCNIC_C2H_OPCODE_START 128
816 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
817 #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
818 #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
819 #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
820 #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
821 #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
822 #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
823 #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136
824 #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
825 #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
826 #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
827 #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
828 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
829 #define QLCNIC_C2H_OPCODE_LAST 142
830
831 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
832 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
833 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
834
835 #define QLCNIC_LRO_REQUEST_CLEANUP 4
836
837 /* Capabilites received */
838 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
839 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
840 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
841 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
842
843 /* module types */
844 #define LINKEVENT_MODULE_NOT_PRESENT 1
845 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
846 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
847 #define LINKEVENT_MODULE_OPTICAL_LRM 4
848 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
849 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
850 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
851 #define LINKEVENT_MODULE_TWINAX 8
852
853 #define LINKSPEED_10GBPS 10000
854 #define LINKSPEED_1GBPS 1000
855 #define LINKSPEED_100MBPS 100
856 #define LINKSPEED_10MBPS 10
857
858 #define LINKSPEED_ENCODED_10MBPS 0
859 #define LINKSPEED_ENCODED_100MBPS 1
860 #define LINKSPEED_ENCODED_1GBPS 2
861
862 #define LINKEVENT_AUTONEG_DISABLED 0
863 #define LINKEVENT_AUTONEG_ENABLED 1
864
865 #define LINKEVENT_HALF_DUPLEX 0
866 #define LINKEVENT_FULL_DUPLEX 1
867
868 #define LINKEVENT_LINKSPEED_MBPS 0
869 #define LINKEVENT_LINKSPEED_ENCODED 1
870
871 /* firmware response header:
872 * 63:58 - message type
873 * 57:56 - owner
874 * 55:53 - desc count
875 * 52:48 - reserved
876 * 47:40 - completion id
877 * 39:32 - opcode
878 * 31:16 - error code
879 * 15:00 - reserved
880 */
881 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
882 ((msg_hdr >> 32) & 0xFF)
883
884 struct qlcnic_fw_msg {
885 union {
886 struct {
887 u64 hdr;
888 u64 body[7];
889 };
890 u64 words[8];
891 };
892 };
893
894 struct qlcnic_nic_req {
895 __le64 qhdr;
896 __le64 req_hdr;
897 __le64 words[6];
898 };
899
900 struct qlcnic_mac_req {
901 u8 op;
902 u8 tag;
903 u8 mac_addr[6];
904 };
905
906 struct qlcnic_vlan_req {
907 __le16 vlan_id;
908 __le16 rsvd[3];
909 };
910
911 struct qlcnic_ipaddr {
912 __be32 ipv4;
913 __be32 ipv6[4];
914 };
915
916 #define QLCNIC_MSI_ENABLED 0x02
917 #define QLCNIC_MSIX_ENABLED 0x04
918 #define QLCNIC_LRO_ENABLED 0x08
919 #define QLCNIC_LRO_DISABLED 0x00
920 #define QLCNIC_BRIDGE_ENABLED 0X10
921 #define QLCNIC_DIAG_ENABLED 0x20
922 #define QLCNIC_ESWITCH_ENABLED 0x40
923 #define QLCNIC_ADAPTER_INITIALIZED 0x80
924 #define QLCNIC_TAGGING_ENABLED 0x100
925 #define QLCNIC_MACSPOOF 0x200
926 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
927 #define QLCNIC_PROMISC_DISABLED 0x800
928 #define QLCNIC_NEED_FLR 0x1000
929 #define QLCNIC_IS_MSI_FAMILY(adapter) \
930 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
931
932 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
933 #define QLCNIC_MSIX_TBL_SPACE 8192
934 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
935 #define QLCNIC_MSIX_TBL_PGSIZE 4096
936
937 #define QLCNIC_NETDEV_WEIGHT 128
938 #define QLCNIC_ADAPTER_UP_MAGIC 777
939
940 #define __QLCNIC_FW_ATTACHED 0
941 #define __QLCNIC_DEV_UP 1
942 #define __QLCNIC_RESETTING 2
943 #define __QLCNIC_START_FW 4
944 #define __QLCNIC_AER 5
945
946 #define QLCNIC_INTERRUPT_TEST 1
947 #define QLCNIC_LOOPBACK_TEST 2
948 #define QLCNIC_LED_TEST 3
949
950 #define QLCNIC_FILTER_AGE 80
951 #define QLCNIC_READD_AGE 20
952 #define QLCNIC_LB_MAX_FILTERS 64
953
954 struct qlcnic_filter {
955 struct hlist_node fnode;
956 u8 faddr[ETH_ALEN];
957 __le16 vlan_id;
958 unsigned long ftime;
959 };
960
961 struct qlcnic_filter_hash {
962 struct hlist_head *fhead;
963 u8 fnum;
964 u8 fmax;
965 };
966
967 struct qlcnic_adapter {
968 struct qlcnic_hardware_context ahw;
969
970 struct net_device *netdev;
971 struct pci_dev *pdev;
972 struct list_head mac_list;
973
974 spinlock_t tx_clean_lock;
975 spinlock_t mac_learn_lock;
976
977 u16 num_txd;
978 u16 num_rxd;
979 u16 num_jumbo_rxd;
980 u16 max_rxd;
981 u16 max_jumbo_rxd;
982
983 u8 max_rds_rings;
984 u8 max_sds_rings;
985 u8 msix_supported;
986 u8 rx_csum;
987 u8 portnum;
988 u8 physical_port;
989 u8 reset_context;
990
991 u8 mc_enabled;
992 u8 max_mc_count;
993 u8 rss_supported;
994 u8 fw_wait_cnt;
995 u8 fw_fail_cnt;
996 u8 tx_timeo_cnt;
997 u8 need_fw_reset;
998
999 u8 has_link_events;
1000 u8 fw_type;
1001 u16 tx_context_id;
1002 u16 is_up;
1003
1004 u16 link_speed;
1005 u16 link_duplex;
1006 u16 link_autoneg;
1007 u16 module_type;
1008
1009 u16 op_mode;
1010 u16 switch_mode;
1011 u16 max_tx_ques;
1012 u16 max_rx_ques;
1013 u16 max_mtu;
1014 u16 pvid;
1015
1016 u32 fw_hal_version;
1017 u32 capabilities;
1018 u32 flags;
1019 u32 irq;
1020 u32 temp;
1021
1022 u32 int_vec_bit;
1023 u32 heartbeat;
1024
1025 u8 max_mac_filters;
1026 u8 dev_state;
1027 u8 diag_test;
1028 u8 diag_cnt;
1029 u8 reset_ack_timeo;
1030 u8 dev_init_timeo;
1031 u16 msg_enable;
1032
1033 u8 mac_addr[ETH_ALEN];
1034
1035 u64 dev_rst_time;
1036
1037 struct vlan_group *vlgrp;
1038 struct qlcnic_npar_info *npars;
1039 struct qlcnic_eswitch *eswitch;
1040 struct qlcnic_nic_template *nic_ops;
1041
1042 struct qlcnic_adapter_stats stats;
1043
1044 struct qlcnic_recv_context recv_ctx;
1045 struct qlcnic_host_tx_ring *tx_ring;
1046
1047 void __iomem *tgt_mask_reg;
1048 void __iomem *tgt_status_reg;
1049 void __iomem *crb_int_state_reg;
1050 void __iomem *isr_int_vec;
1051
1052 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1053
1054 struct delayed_work fw_work;
1055
1056 struct qlcnic_nic_intr_coalesce coal;
1057
1058 struct qlcnic_filter_hash fhash;
1059
1060 unsigned long state;
1061 __le32 file_prd_off; /*File fw product offset*/
1062 u32 fw_version;
1063 const struct firmware *fw;
1064 };
1065
1066 struct qlcnic_info {
1067 __le16 pci_func;
1068 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1069 __le16 phys_port;
1070 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1071
1072 __le32 capabilities;
1073 u8 max_mac_filters;
1074 u8 reserved1;
1075 __le16 max_mtu;
1076
1077 __le16 max_tx_ques;
1078 __le16 max_rx_ques;
1079 __le16 min_tx_bw;
1080 __le16 max_tx_bw;
1081 u8 reserved2[104];
1082 };
1083
1084 struct qlcnic_pci_info {
1085 __le16 id; /* pci function id */
1086 __le16 active; /* 1 = Enabled */
1087 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1088 __le16 default_port; /* default port number */
1089
1090 __le16 tx_min_bw; /* Multiple of 100mbpc */
1091 __le16 tx_max_bw;
1092 __le16 reserved1[2];
1093
1094 u8 mac[ETH_ALEN];
1095 u8 reserved2[106];
1096 };
1097
1098 struct qlcnic_npar_info {
1099 u16 pvid;
1100 u16 min_bw;
1101 u16 max_bw;
1102 u8 phy_port;
1103 u8 type;
1104 u8 active;
1105 u8 enable_pm;
1106 u8 dest_npar;
1107 u8 discard_tagged;
1108 u8 mac_override;
1109 u8 mac_anti_spoof;
1110 u8 promisc_mode;
1111 u8 offload_flags;
1112 };
1113
1114 struct qlcnic_eswitch {
1115 u8 port;
1116 u8 active_vports;
1117 u8 active_vlans;
1118 u8 active_ucast_filters;
1119 u8 max_ucast_filters;
1120 u8 max_active_vlans;
1121
1122 u32 flags;
1123 #define QLCNIC_SWITCH_ENABLE BIT_1
1124 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1125 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1126 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1127 };
1128
1129
1130 /* Return codes for Error handling */
1131 #define QL_STATUS_INVALID_PARAM -1
1132
1133 #define MAX_BW 100 /* % of link speed */
1134 #define MAX_VLAN_ID 4095
1135 #define MIN_VLAN_ID 2
1136 #define DEFAULT_MAC_LEARN 1
1137
1138 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1139 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1140
1141 struct qlcnic_pci_func_cfg {
1142 u16 func_type;
1143 u16 min_bw;
1144 u16 max_bw;
1145 u16 port_num;
1146 u8 pci_func;
1147 u8 func_state;
1148 u8 def_mac_addr[6];
1149 };
1150
1151 struct qlcnic_npar_func_cfg {
1152 u32 fw_capab;
1153 u16 port_num;
1154 u16 min_bw;
1155 u16 max_bw;
1156 u16 max_tx_queues;
1157 u16 max_rx_queues;
1158 u8 pci_func;
1159 u8 op_mode;
1160 };
1161
1162 struct qlcnic_pm_func_cfg {
1163 u8 pci_func;
1164 u8 action;
1165 u8 dest_npar;
1166 u8 reserved[5];
1167 };
1168
1169 struct qlcnic_esw_func_cfg {
1170 u16 vlan_id;
1171 u8 op_mode;
1172 u8 op_type;
1173 u8 pci_func;
1174 u8 host_vlan_tag;
1175 u8 promisc_mode;
1176 u8 discard_tagged;
1177 u8 mac_override;
1178 u8 mac_anti_spoof;
1179 u8 offload_flags;
1180 u8 reserved[5];
1181 };
1182
1183 #define QLCNIC_STATS_VERSION 1
1184 #define QLCNIC_STATS_PORT 1
1185 #define QLCNIC_STATS_ESWITCH 2
1186 #define QLCNIC_QUERY_RX_COUNTER 0
1187 #define QLCNIC_QUERY_TX_COUNTER 1
1188 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1189
1190 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1191 do { \
1192 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1193 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1194 (VAL1) = (VAL2); \
1195 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1196 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1197 (VAL1) += (VAL2); \
1198 } while (0)
1199
1200 struct __qlcnic_esw_statistics {
1201 __le16 context_id;
1202 __le16 version;
1203 __le16 size;
1204 __le16 unused;
1205 __le64 unicast_frames;
1206 __le64 multicast_frames;
1207 __le64 broadcast_frames;
1208 __le64 dropped_frames;
1209 __le64 errors;
1210 __le64 local_frames;
1211 __le64 numbytes;
1212 __le64 rsvd[3];
1213 };
1214
1215 struct qlcnic_esw_statistics {
1216 struct __qlcnic_esw_statistics rx;
1217 struct __qlcnic_esw_statistics tx;
1218 };
1219
1220 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1221 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1222
1223 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1224 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1225 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1226 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1227 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1228 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1229
1230 #define ADDR_IN_RANGE(addr, low, high) \
1231 (((addr) < (high)) && ((addr) >= (low)))
1232
1233 #define QLCRD32(adapter, off) \
1234 (qlcnic_hw_read_wx_2M(adapter, off))
1235 #define QLCWR32(adapter, off, val) \
1236 (qlcnic_hw_write_wx_2M(adapter, off, val))
1237
1238 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1239 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1240
1241 #define qlcnic_rom_lock(a) \
1242 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1243 #define qlcnic_rom_unlock(a) \
1244 qlcnic_pcie_sem_unlock((a), 2)
1245 #define qlcnic_phy_lock(a) \
1246 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1247 #define qlcnic_phy_unlock(a) \
1248 qlcnic_pcie_sem_unlock((a), 3)
1249 #define qlcnic_api_lock(a) \
1250 qlcnic_pcie_sem_lock((a), 5, 0)
1251 #define qlcnic_api_unlock(a) \
1252 qlcnic_pcie_sem_unlock((a), 5)
1253 #define qlcnic_sw_lock(a) \
1254 qlcnic_pcie_sem_lock((a), 6, 0)
1255 #define qlcnic_sw_unlock(a) \
1256 qlcnic_pcie_sem_unlock((a), 6)
1257 #define crb_win_lock(a) \
1258 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1259 #define crb_win_unlock(a) \
1260 qlcnic_pcie_sem_unlock((a), 7)
1261
1262 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1263 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1264 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1265 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1266 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1267
1268 /* Functions from qlcnic_init.c */
1269 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1270 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1271 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1272 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1273 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1274 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1275 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1276
1277 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1278 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1279 u8 *bytes, size_t size);
1280 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1281 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1282
1283 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1284
1285 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1286 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1287
1288 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1289 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1290
1291 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1292 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1293 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1294
1295 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1296 void qlcnic_watchdog_task(struct work_struct *work);
1297 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
1298 struct qlcnic_host_rds_ring *rds_ring);
1299 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1300 void qlcnic_set_multi(struct net_device *netdev);
1301 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1302 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1303 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1304 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1305 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1306 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1307 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1308
1309 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1310 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1311 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1312 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1313 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1314 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1315 struct qlcnic_host_tx_ring *tx_ring);
1316 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1317
1318 /* Functions from qlcnic_main.c */
1319 int qlcnic_reset_context(struct qlcnic_adapter *);
1320 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1321 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1322 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1323 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1324 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1325
1326 /* Management functions */
1327 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1328 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1329 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1330 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1331
1332 /* eSwitch management functions */
1333 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1334 struct qlcnic_esw_func_cfg *);
1335 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1336 struct qlcnic_esw_func_cfg *);
1337 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1338 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1339 struct __qlcnic_esw_statistics *);
1340 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1341 struct __qlcnic_esw_statistics *);
1342 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1343 extern int qlcnic_config_tso;
1344
1345 /*
1346 * QLOGIC Board information
1347 */
1348
1349 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1350 struct qlcnic_brdinfo {
1351 unsigned short vendor;
1352 unsigned short device;
1353 unsigned short sub_vendor;
1354 unsigned short sub_device;
1355 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1356 };
1357
1358 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1359 {0x1077, 0x8020, 0x1077, 0x203,
1360 "8200 Series Single Port 10GbE Converged Network Adapter "
1361 "(TCP/IP Networking)"},
1362 {0x1077, 0x8020, 0x1077, 0x207,
1363 "8200 Series Dual Port 10GbE Converged Network Adapter "
1364 "(TCP/IP Networking)"},
1365 {0x1077, 0x8020, 0x1077, 0x20b,
1366 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1367 {0x1077, 0x8020, 0x1077, 0x20c,
1368 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1369 {0x1077, 0x8020, 0x1077, 0x20f,
1370 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1371 {0x1077, 0x8020, 0x103c, 0x3733,
1372 "NC523SFP 10Gb 2-port Server Adapter"},
1373 {0x1077, 0x8020, 0x103c, 0x3346,
1374 "CN1000Q Dual Port Converged Network Adapter"},
1375 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1376 };
1377
1378 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1379
1380 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1381 {
1382 smp_mb();
1383 if (tx_ring->producer < tx_ring->sw_consumer)
1384 return tx_ring->sw_consumer - tx_ring->producer;
1385 else
1386 return tx_ring->sw_consumer + tx_ring->num_desc -
1387 tx_ring->producer;
1388 }
1389
1390 extern const struct ethtool_ops qlcnic_ethtool_ops;
1391
1392 struct qlcnic_nic_template {
1393 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1394 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1395 int (*start_firmware) (struct qlcnic_adapter *);
1396 };
1397
1398 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1399 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1400 printk(KERN_INFO "%s: %s: " _fmt, \
1401 dev_name(&adapter->pdev->dev), \
1402 __func__, ##_args); \
1403 } while (0)
1404
1405 #endif /* __QLCNIC_H_ */
Mirror of the linux-mips.org kernel tree