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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / net / r8169.c
blob397c36810a159ad7dfc143a819303e059008fe56
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
41
42 #ifdef RTL8169_DEBUG
43 #define assert(expr) \
44 if (!(expr)) { \
45 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
46 #expr,__FILE__,__func__,__LINE__); \
47 }
48 #define dprintk(fmt, args...) \
49 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #else
51 #define assert(expr) do {} while (0)
52 #define dprintk(fmt, args...) do {} while (0)
53 #endif /* RTL8169_DEBUG */
54
55 #define R8169_MSG_DEFAULT \
56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57
58 #define TX_BUFFS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 static const int multicast_filter_limit = 32;
64
65 /* MAC address length */
66 #define MAC_ADDR_LEN 6
67
68 #define MAX_READ_REQUEST_SHIFT 12
69 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
70 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
71 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
72 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
73 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
74
75 #define R8169_REGS_SIZE 256
76 #define R8169_NAPI_WEIGHT 64
77 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
78 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
79 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
80 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
81 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
82
83 #define RTL8169_TX_TIMEOUT (6*HZ)
84 #define RTL8169_PHY_TIMEOUT (10*HZ)
85
86 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
87 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
88 #define RTL_EEPROM_SIG_ADDR 0x0000
89
90 /* write/read MMIO register */
91 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
92 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
93 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
94 #define RTL_R8(reg) readb (ioaddr + (reg))
95 #define RTL_R16(reg) readw (ioaddr + (reg))
96 #define RTL_R32(reg) readl (ioaddr + (reg))
97
98 enum mac_version {
99 RTL_GIGA_MAC_NONE = 0x00,
100 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
101 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
102 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
103 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
104 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
105 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
106 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
107 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
108 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
109 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
110 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
111 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
112 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
113 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
114 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
115 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
116 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
117 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
118 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
119 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
120 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
121 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
122 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
123 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
124 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
125 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
126 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
127 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
128 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
129 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
130 };
131
132 #define _R(NAME,MAC,MASK) \
133 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
134
135 static const struct {
136 const char *name;
137 u8 mac_version;
138 u32 RxConfigMask; /* Clears the bits supported by this chip */
139 } rtl_chip_info[] = {
140 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
141 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
142 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
143 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
144 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
145 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
146 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
147 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
148 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
149 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
153 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
154 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
155 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
156 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
158 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
159 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
160 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
161 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
162 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
163 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
164 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
165 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
166 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
167 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
168 _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
169 _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E
170 };
171 #undef _R
172
173 static const struct rtl_firmware_info {
174 int mac_version;
175 const char *fw_name;
176 } rtl_firmware_infos[] = {
177 { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
178 { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
179 { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
180 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 }
181 };
182
183 enum cfg_version {
184 RTL_CFG_0 = 0x00,
185 RTL_CFG_1,
186 RTL_CFG_2
187 };
188
189 static void rtl_hw_start_8169(struct net_device *);
190 static void rtl_hw_start_8168(struct net_device *);
191 static void rtl_hw_start_8101(struct net_device *);
192
193 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
194 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
195 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
196 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
197 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
198 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
199 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
200 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
201 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
202 { PCI_VENDOR_ID_LINKSYS, 0x1032,
203 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
204 { 0x0001, 0x8168,
205 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
206 {0,},
207 };
208
209 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
210
211 static int rx_buf_sz = 16383;
212 static int use_dac;
213 static struct {
214 u32 msg_enable;
215 } debug = { -1 };
216
217 enum rtl_registers {
218 MAC0 = 0, /* Ethernet hardware address. */
219 MAC4 = 4,
220 MAR0 = 8, /* Multicast filter. */
221 CounterAddrLow = 0x10,
222 CounterAddrHigh = 0x14,
223 TxDescStartAddrLow = 0x20,
224 TxDescStartAddrHigh = 0x24,
225 TxHDescStartAddrLow = 0x28,
226 TxHDescStartAddrHigh = 0x2c,
227 FLASH = 0x30,
228 ERSR = 0x36,
229 ChipCmd = 0x37,
230 TxPoll = 0x38,
231 IntrMask = 0x3c,
232 IntrStatus = 0x3e,
233 TxConfig = 0x40,
234 RxConfig = 0x44,
235 RxMissed = 0x4c,
236 Cfg9346 = 0x50,
237 Config0 = 0x51,
238 Config1 = 0x52,
239 Config2 = 0x53,
240 Config3 = 0x54,
241 Config4 = 0x55,
242 Config5 = 0x56,
243 MultiIntr = 0x5c,
244 PHYAR = 0x60,
245 PHYstatus = 0x6c,
246 RxMaxSize = 0xda,
247 CPlusCmd = 0xe0,
248 IntrMitigate = 0xe2,
249 RxDescAddrLow = 0xe4,
250 RxDescAddrHigh = 0xe8,
251 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
252
253 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
254
255 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
256
257 #define TxPacketMax (8064 >> 7)
258
259 FuncEvent = 0xf0,
260 FuncEventMask = 0xf4,
261 FuncPresetState = 0xf8,
262 FuncForceEvent = 0xfc,
263 };
264
265 enum rtl8110_registers {
266 TBICSR = 0x64,
267 TBI_ANAR = 0x68,
268 TBI_LPAR = 0x6a,
269 };
270
271 enum rtl8168_8101_registers {
272 CSIDR = 0x64,
273 CSIAR = 0x68,
274 #define CSIAR_FLAG 0x80000000
275 #define CSIAR_WRITE_CMD 0x80000000
276 #define CSIAR_BYTE_ENABLE 0x0f
277 #define CSIAR_BYTE_ENABLE_SHIFT 12
278 #define CSIAR_ADDR_MASK 0x0fff
279 PMCH = 0x6f,
280 EPHYAR = 0x80,
281 #define EPHYAR_FLAG 0x80000000
282 #define EPHYAR_WRITE_CMD 0x80000000
283 #define EPHYAR_REG_MASK 0x1f
284 #define EPHYAR_REG_SHIFT 16
285 #define EPHYAR_DATA_MASK 0xffff
286 DLLPR = 0xd0,
287 #define PM_SWITCH (1 << 6)
288 DBG_REG = 0xd1,
289 #define FIX_NAK_1 (1 << 4)
290 #define FIX_NAK_2 (1 << 3)
291 TWSI = 0xd2,
292 MCU = 0xd3,
293 #define EN_NDP (1 << 3)
294 #define EN_OOB_RESET (1 << 2)
295 EFUSEAR = 0xdc,
296 #define EFUSEAR_FLAG 0x80000000
297 #define EFUSEAR_WRITE_CMD 0x80000000
298 #define EFUSEAR_READ_CMD 0x00000000
299 #define EFUSEAR_REG_MASK 0x03ff
300 #define EFUSEAR_REG_SHIFT 8
301 #define EFUSEAR_DATA_MASK 0xff
302 };
303
304 enum rtl8168_registers {
305 ERIDR = 0x70,
306 ERIAR = 0x74,
307 #define ERIAR_FLAG 0x80000000
308 #define ERIAR_WRITE_CMD 0x80000000
309 #define ERIAR_READ_CMD 0x00000000
310 #define ERIAR_ADDR_BYTE_ALIGN 4
311 #define ERIAR_EXGMAC 0
312 #define ERIAR_MSIX 1
313 #define ERIAR_ASF 2
314 #define ERIAR_TYPE_SHIFT 16
315 #define ERIAR_BYTEEN 0x0f
316 #define ERIAR_BYTEEN_SHIFT 12
317 EPHY_RXER_NUM = 0x7c,
318 OCPDR = 0xb0, /* OCP GPHY access */
319 #define OCPDR_WRITE_CMD 0x80000000
320 #define OCPDR_READ_CMD 0x00000000
321 #define OCPDR_REG_MASK 0x7f
322 #define OCPDR_GPHY_REG_SHIFT 16
323 #define OCPDR_DATA_MASK 0xffff
324 OCPAR = 0xb4,
325 #define OCPAR_FLAG 0x80000000
326 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
327 #define OCPAR_GPHY_READ_CMD 0x0000f060
328 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
329 };
330
331 enum rtl_register_content {
332 /* InterruptStatusBits */
333 SYSErr = 0x8000,
334 PCSTimeout = 0x4000,
335 SWInt = 0x0100,
336 TxDescUnavail = 0x0080,
337 RxFIFOOver = 0x0040,
338 LinkChg = 0x0020,
339 RxOverflow = 0x0010,
340 TxErr = 0x0008,
341 TxOK = 0x0004,
342 RxErr = 0x0002,
343 RxOK = 0x0001,
344
345 /* RxStatusDesc */
346 RxFOVF = (1 << 23),
347 RxRWT = (1 << 22),
348 RxRES = (1 << 21),
349 RxRUNT = (1 << 20),
350 RxCRC = (1 << 19),
351
352 /* ChipCmdBits */
353 CmdReset = 0x10,
354 CmdRxEnb = 0x08,
355 CmdTxEnb = 0x04,
356 RxBufEmpty = 0x01,
357
358 /* TXPoll register p.5 */
359 HPQ = 0x80, /* Poll cmd on the high prio queue */
360 NPQ = 0x40, /* Poll cmd on the low prio queue */
361 FSWInt = 0x01, /* Forced software interrupt */
362
363 /* Cfg9346Bits */
364 Cfg9346_Lock = 0x00,
365 Cfg9346_Unlock = 0xc0,
366
367 /* rx_mode_bits */
368 AcceptErr = 0x20,
369 AcceptRunt = 0x10,
370 AcceptBroadcast = 0x08,
371 AcceptMulticast = 0x04,
372 AcceptMyPhys = 0x02,
373 AcceptAllPhys = 0x01,
374
375 /* RxConfigBits */
376 RxCfgFIFOShift = 13,
377 RxCfgDMAShift = 8,
378
379 /* TxConfigBits */
380 TxInterFrameGapShift = 24,
381 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
382
383 /* Config1 register p.24 */
384 LEDS1 = (1 << 7),
385 LEDS0 = (1 << 6),
386 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
387 Speed_down = (1 << 4),
388 MEMMAP = (1 << 3),
389 IOMAP = (1 << 2),
390 VPD = (1 << 1),
391 PMEnable = (1 << 0), /* Power Management Enable */
392
393 /* Config2 register p. 25 */
394 PCI_Clock_66MHz = 0x01,
395 PCI_Clock_33MHz = 0x00,
396
397 /* Config3 register p.25 */
398 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
399 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
400 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
401
402 /* Config5 register p.27 */
403 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
404 MWF = (1 << 5), /* Accept Multicast wakeup frame */
405 UWF = (1 << 4), /* Accept Unicast wakeup frame */
406 LanWake = (1 << 1), /* LanWake enable/disable */
407 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
408
409 /* TBICSR p.28 */
410 TBIReset = 0x80000000,
411 TBILoopback = 0x40000000,
412 TBINwEnable = 0x20000000,
413 TBINwRestart = 0x10000000,
414 TBILinkOk = 0x02000000,
415 TBINwComplete = 0x01000000,
416
417 /* CPlusCmd p.31 */
418 EnableBist = (1 << 15), // 8168 8101
419 Mac_dbgo_oe = (1 << 14), // 8168 8101
420 Normal_mode = (1 << 13), // unused
421 Force_half_dup = (1 << 12), // 8168 8101
422 Force_rxflow_en = (1 << 11), // 8168 8101
423 Force_txflow_en = (1 << 10), // 8168 8101
424 Cxpl_dbg_sel = (1 << 9), // 8168 8101
425 ASF = (1 << 8), // 8168 8101
426 PktCntrDisable = (1 << 7), // 8168 8101
427 Mac_dbgo_sel = 0x001c, // 8168
428 RxVlan = (1 << 6),
429 RxChkSum = (1 << 5),
430 PCIDAC = (1 << 4),
431 PCIMulRW = (1 << 3),
432 INTT_0 = 0x0000, // 8168
433 INTT_1 = 0x0001, // 8168
434 INTT_2 = 0x0002, // 8168
435 INTT_3 = 0x0003, // 8168
436
437 /* rtl8169_PHYstatus */
438 TBI_Enable = 0x80,
439 TxFlowCtrl = 0x40,
440 RxFlowCtrl = 0x20,
441 _1000bpsF = 0x10,
442 _100bps = 0x08,
443 _10bps = 0x04,
444 LinkStatus = 0x02,
445 FullDup = 0x01,
446
447 /* _TBICSRBit */
448 TBILinkOK = 0x02000000,
449
450 /* DumpCounterCommand */
451 CounterDump = 0x8,
452 };
453
454 enum desc_status_bit {
455 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
456 RingEnd = (1 << 30), /* End of descriptor ring */
457 FirstFrag = (1 << 29), /* First segment of a packet */
458 LastFrag = (1 << 28), /* Final segment of a packet */
459
460 /* Tx private */
461 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
462 MSSShift = 16, /* MSS value position */
463 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
464 IPCS = (1 << 18), /* Calculate IP checksum */
465 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
466 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
467 TxVlanTag = (1 << 17), /* Add VLAN tag */
468
469 /* Rx private */
470 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
471 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
472
473 #define RxProtoUDP (PID1)
474 #define RxProtoTCP (PID0)
475 #define RxProtoIP (PID1 | PID0)
476 #define RxProtoMask RxProtoIP
477
478 IPFail = (1 << 16), /* IP checksum failed */
479 UDPFail = (1 << 15), /* UDP/IP checksum failed */
480 TCPFail = (1 << 14), /* TCP/IP checksum failed */
481 RxVlanTag = (1 << 16), /* VLAN tag available */
482 };
483
484 #define RsvdMask 0x3fffc000
485
486 struct TxDesc {
487 __le32 opts1;
488 __le32 opts2;
489 __le64 addr;
490 };
491
492 struct RxDesc {
493 __le32 opts1;
494 __le32 opts2;
495 __le64 addr;
496 };
497
498 struct ring_info {
499 struct sk_buff *skb;
500 u32 len;
501 u8 __pad[sizeof(void *) - sizeof(u32)];
502 };
503
504 enum features {
505 RTL_FEATURE_WOL = (1 << 0),
506 RTL_FEATURE_MSI = (1 << 1),
507 RTL_FEATURE_GMII = (1 << 2),
508 };
509
510 struct rtl8169_counters {
511 __le64 tx_packets;
512 __le64 rx_packets;
513 __le64 tx_errors;
514 __le32 rx_errors;
515 __le16 rx_missed;
516 __le16 align_errors;
517 __le32 tx_one_collision;
518 __le32 tx_multi_collision;
519 __le64 rx_unicast;
520 __le64 rx_broadcast;
521 __le32 rx_multicast;
522 __le16 tx_aborted;
523 __le16 tx_underun;
524 };
525
526 struct rtl8169_private {
527 void __iomem *mmio_addr; /* memory map physical address */
528 struct pci_dev *pci_dev; /* Index of PCI device */
529 struct net_device *dev;
530 struct napi_struct napi;
531 spinlock_t lock; /* spin lock flag */
532 u32 msg_enable;
533 int chipset;
534 int mac_version;
535 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
536 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
537 u32 dirty_rx;
538 u32 dirty_tx;
539 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
540 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
541 dma_addr_t TxPhyAddr;
542 dma_addr_t RxPhyAddr;
543 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
544 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
545 struct timer_list timer;
546 u16 cp_cmd;
547 u16 intr_event;
548 u16 napi_event;
549 u16 intr_mask;
550 int phy_1000_ctrl_reg;
551
552 struct mdio_ops {
553 void (*write)(void __iomem *, int, int);
554 int (*read)(void __iomem *, int);
555 } mdio_ops;
556
557 struct pll_power_ops {
558 void (*down)(struct rtl8169_private *);
559 void (*up)(struct rtl8169_private *);
560 } pll_power_ops;
561
562 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
563 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
564 void (*phy_reset_enable)(struct rtl8169_private *tp);
565 void (*hw_start)(struct net_device *);
566 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
567 unsigned int (*link_ok)(void __iomem *);
568 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
569 int pcie_cap;
570 struct delayed_work task;
571 unsigned features;
572
573 struct mii_if_info mii;
574 struct rtl8169_counters counters;
575 u32 saved_wolopts;
576
577 const struct firmware *fw;
578 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
579 };
580
581 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
582 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
583 module_param(use_dac, int, 0);
584 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
585 module_param_named(debug, debug.msg_enable, int, 0);
586 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
587 MODULE_LICENSE("GPL");
588 MODULE_VERSION(RTL8169_VERSION);
589 MODULE_FIRMWARE(FIRMWARE_8168D_1);
590 MODULE_FIRMWARE(FIRMWARE_8168D_2);
591 MODULE_FIRMWARE(FIRMWARE_8105E_1);
592
593 static int rtl8169_open(struct net_device *dev);
594 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
595 struct net_device *dev);
596 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
597 static int rtl8169_init_ring(struct net_device *dev);
598 static void rtl_hw_start(struct net_device *dev);
599 static int rtl8169_close(struct net_device *dev);
600 static void rtl_set_rx_mode(struct net_device *dev);
601 static void rtl8169_tx_timeout(struct net_device *dev);
602 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
603 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
604 void __iomem *, u32 budget);
605 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
606 static void rtl8169_down(struct net_device *dev);
607 static void rtl8169_rx_clear(struct rtl8169_private *tp);
608 static int rtl8169_poll(struct napi_struct *napi, int budget);
609
610 static const unsigned int rtl8169_rx_config =
611 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
612
613 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
614 {
615 void __iomem *ioaddr = tp->mmio_addr;
616 int i;
617
618 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
619 for (i = 0; i < 20; i++) {
620 udelay(100);
621 if (RTL_R32(OCPAR) & OCPAR_FLAG)
622 break;
623 }
624 return RTL_R32(OCPDR);
625 }
626
627 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
628 {
629 void __iomem *ioaddr = tp->mmio_addr;
630 int i;
631
632 RTL_W32(OCPDR, data);
633 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
634 for (i = 0; i < 20; i++) {
635 udelay(100);
636 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
637 break;
638 }
639 }
640
641 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
642 {
643 void __iomem *ioaddr = tp->mmio_addr;
644 int i;
645
646 RTL_W8(ERIDR, cmd);
647 RTL_W32(ERIAR, 0x800010e8);
648 msleep(2);
649 for (i = 0; i < 5; i++) {
650 udelay(100);
651 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
652 break;
653 }
654
655 ocp_write(tp, 0x1, 0x30, 0x00000001);
656 }
657
658 #define OOB_CMD_RESET 0x00
659 #define OOB_CMD_DRIVER_START 0x05
660 #define OOB_CMD_DRIVER_STOP 0x06
661
662 static void rtl8168_driver_start(struct rtl8169_private *tp)
663 {
664 int i;
665
666 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
667
668 for (i = 0; i < 10; i++) {
669 msleep(10);
670 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
671 break;
672 }
673 }
674
675 static void rtl8168_driver_stop(struct rtl8169_private *tp)
676 {
677 int i;
678
679 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
680
681 for (i = 0; i < 10; i++) {
682 msleep(10);
683 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
684 break;
685 }
686 }
687
688
689 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
690 {
691 int i;
692
693 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
694
695 for (i = 20; i > 0; i--) {
696 /*
697 * Check if the RTL8169 has completed writing to the specified
698 * MII register.
699 */
700 if (!(RTL_R32(PHYAR) & 0x80000000))
701 break;
702 udelay(25);
703 }
704 /*
705 * According to hardware specs a 20us delay is required after write
706 * complete indication, but before sending next command.
707 */
708 udelay(20);
709 }
710
711 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
712 {
713 int i, value = -1;
714
715 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
716
717 for (i = 20; i > 0; i--) {
718 /*
719 * Check if the RTL8169 has completed retrieving data from
720 * the specified MII register.
721 */
722 if (RTL_R32(PHYAR) & 0x80000000) {
723 value = RTL_R32(PHYAR) & 0xffff;
724 break;
725 }
726 udelay(25);
727 }
728 /*
729 * According to hardware specs a 20us delay is required after read
730 * complete indication, but before sending next command.
731 */
732 udelay(20);
733
734 return value;
735 }
736
737 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
738 {
739 int i;
740
741 RTL_W32(OCPDR, data |
742 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
743 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
744 RTL_W32(EPHY_RXER_NUM, 0);
745
746 for (i = 0; i < 100; i++) {
747 mdelay(1);
748 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
749 break;
750 }
751 }
752
753 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
754 {
755 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
756 (value & OCPDR_DATA_MASK));
757 }
758
759 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
760 {
761 int i;
762
763 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
764
765 mdelay(1);
766 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
767 RTL_W32(EPHY_RXER_NUM, 0);
768
769 for (i = 0; i < 100; i++) {
770 mdelay(1);
771 if (RTL_R32(OCPAR) & OCPAR_FLAG)
772 break;
773 }
774
775 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
776 }
777
778 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
779
780 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
781 {
782 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
783 }
784
785 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
786 {
787 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
788 }
789
790 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
791 {
792 r8168dp_2_mdio_start(ioaddr);
793
794 r8169_mdio_write(ioaddr, reg_addr, value);
795
796 r8168dp_2_mdio_stop(ioaddr);
797 }
798
799 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
800 {
801 int value;
802
803 r8168dp_2_mdio_start(ioaddr);
804
805 value = r8169_mdio_read(ioaddr, reg_addr);
806
807 r8168dp_2_mdio_stop(ioaddr);
808
809 return value;
810 }
811
812 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
813 {
814 tp->mdio_ops.write(tp->mmio_addr, location, val);
815 }
816
817 static int rtl_readphy(struct rtl8169_private *tp, int location)
818 {
819 return tp->mdio_ops.read(tp->mmio_addr, location);
820 }
821
822 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
823 {
824 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
825 }
826
827 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
828 {
829 int val;
830
831 val = rtl_readphy(tp, reg_addr);
832 rtl_writephy(tp, reg_addr, (val | p) & ~m);
833 }
834
835 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
836 int val)
837 {
838 struct rtl8169_private *tp = netdev_priv(dev);
839
840 rtl_writephy(tp, location, val);
841 }
842
843 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
844 {
845 struct rtl8169_private *tp = netdev_priv(dev);
846
847 return rtl_readphy(tp, location);
848 }
849
850 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
851 {
852 unsigned int i;
853
854 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
855 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
856
857 for (i = 0; i < 100; i++) {
858 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
859 break;
860 udelay(10);
861 }
862 }
863
864 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
865 {
866 u16 value = 0xffff;
867 unsigned int i;
868
869 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
870
871 for (i = 0; i < 100; i++) {
872 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
873 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
874 break;
875 }
876 udelay(10);
877 }
878
879 return value;
880 }
881
882 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
883 {
884 unsigned int i;
885
886 RTL_W32(CSIDR, value);
887 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
888 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
889
890 for (i = 0; i < 100; i++) {
891 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
892 break;
893 udelay(10);
894 }
895 }
896
897 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
898 {
899 u32 value = ~0x00;
900 unsigned int i;
901
902 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
903 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
904
905 for (i = 0; i < 100; i++) {
906 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
907 value = RTL_R32(CSIDR);
908 break;
909 }
910 udelay(10);
911 }
912
913 return value;
914 }
915
916 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
917 {
918 u8 value = 0xff;
919 unsigned int i;
920
921 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
922
923 for (i = 0; i < 300; i++) {
924 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
925 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
926 break;
927 }
928 udelay(100);
929 }
930
931 return value;
932 }
933
934 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
935 {
936 RTL_W16(IntrMask, 0x0000);
937
938 RTL_W16(IntrStatus, 0xffff);
939 }
940
941 static void rtl8169_asic_down(void __iomem *ioaddr)
942 {
943 RTL_W8(ChipCmd, 0x00);
944 rtl8169_irq_mask_and_ack(ioaddr);
945 RTL_R16(CPlusCmd);
946 }
947
948 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
949 {
950 void __iomem *ioaddr = tp->mmio_addr;
951
952 return RTL_R32(TBICSR) & TBIReset;
953 }
954
955 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
956 {
957 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
958 }
959
960 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
961 {
962 return RTL_R32(TBICSR) & TBILinkOk;
963 }
964
965 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
966 {
967 return RTL_R8(PHYstatus) & LinkStatus;
968 }
969
970 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
971 {
972 void __iomem *ioaddr = tp->mmio_addr;
973
974 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
975 }
976
977 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
978 {
979 unsigned int val;
980
981 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
982 rtl_writephy(tp, MII_BMCR, val & 0xffff);
983 }
984
985 static void __rtl8169_check_link_status(struct net_device *dev,
986 struct rtl8169_private *tp,
987 void __iomem *ioaddr,
988 bool pm)
989 {
990 unsigned long flags;
991
992 spin_lock_irqsave(&tp->lock, flags);
993 if (tp->link_ok(ioaddr)) {
994 /* This is to cancel a scheduled suspend if there's one. */
995 if (pm)
996 pm_request_resume(&tp->pci_dev->dev);
997 netif_carrier_on(dev);
998 if (net_ratelimit())
999 netif_info(tp, ifup, dev, "link up\n");
1000 } else {
1001 netif_carrier_off(dev);
1002 netif_info(tp, ifdown, dev, "link down\n");
1003 if (pm)
1004 pm_schedule_suspend(&tp->pci_dev->dev, 100);
1005 }
1006 spin_unlock_irqrestore(&tp->lock, flags);
1007 }
1008
1009 static void rtl8169_check_link_status(struct net_device *dev,
1010 struct rtl8169_private *tp,
1011 void __iomem *ioaddr)
1012 {
1013 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1014 }
1015
1016 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1017
1018 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1019 {
1020 void __iomem *ioaddr = tp->mmio_addr;
1021 u8 options;
1022 u32 wolopts = 0;
1023
1024 options = RTL_R8(Config1);
1025 if (!(options & PMEnable))
1026 return 0;
1027
1028 options = RTL_R8(Config3);
1029 if (options & LinkUp)
1030 wolopts |= WAKE_PHY;
1031 if (options & MagicPacket)
1032 wolopts |= WAKE_MAGIC;
1033
1034 options = RTL_R8(Config5);
1035 if (options & UWF)
1036 wolopts |= WAKE_UCAST;
1037 if (options & BWF)
1038 wolopts |= WAKE_BCAST;
1039 if (options & MWF)
1040 wolopts |= WAKE_MCAST;
1041
1042 return wolopts;
1043 }
1044
1045 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1046 {
1047 struct rtl8169_private *tp = netdev_priv(dev);
1048
1049 spin_lock_irq(&tp->lock);
1050
1051 wol->supported = WAKE_ANY;
1052 wol->wolopts = __rtl8169_get_wol(tp);
1053
1054 spin_unlock_irq(&tp->lock);
1055 }
1056
1057 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1058 {
1059 void __iomem *ioaddr = tp->mmio_addr;
1060 unsigned int i;
1061 static const struct {
1062 u32 opt;
1063 u16 reg;
1064 u8 mask;
1065 } cfg[] = {
1066 { WAKE_ANY, Config1, PMEnable },
1067 { WAKE_PHY, Config3, LinkUp },
1068 { WAKE_MAGIC, Config3, MagicPacket },
1069 { WAKE_UCAST, Config5, UWF },
1070 { WAKE_BCAST, Config5, BWF },
1071 { WAKE_MCAST, Config5, MWF },
1072 { WAKE_ANY, Config5, LanWake }
1073 };
1074
1075 RTL_W8(Cfg9346, Cfg9346_Unlock);
1076
1077 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1078 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1079 if (wolopts & cfg[i].opt)
1080 options |= cfg[i].mask;
1081 RTL_W8(cfg[i].reg, options);
1082 }
1083
1084 RTL_W8(Cfg9346, Cfg9346_Lock);
1085 }
1086
1087 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1088 {
1089 struct rtl8169_private *tp = netdev_priv(dev);
1090
1091 spin_lock_irq(&tp->lock);
1092
1093 if (wol->wolopts)
1094 tp->features |= RTL_FEATURE_WOL;
1095 else
1096 tp->features &= ~RTL_FEATURE_WOL;
1097 __rtl8169_set_wol(tp, wol->wolopts);
1098 spin_unlock_irq(&tp->lock);
1099
1100 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1101
1102 return 0;
1103 }
1104
1105 static void rtl8169_get_drvinfo(struct net_device *dev,
1106 struct ethtool_drvinfo *info)
1107 {
1108 struct rtl8169_private *tp = netdev_priv(dev);
1109
1110 strcpy(info->driver, MODULENAME);
1111 strcpy(info->version, RTL8169_VERSION);
1112 strcpy(info->bus_info, pci_name(tp->pci_dev));
1113 }
1114
1115 static int rtl8169_get_regs_len(struct net_device *dev)
1116 {
1117 return R8169_REGS_SIZE;
1118 }
1119
1120 static int rtl8169_set_speed_tbi(struct net_device *dev,
1121 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1122 {
1123 struct rtl8169_private *tp = netdev_priv(dev);
1124 void __iomem *ioaddr = tp->mmio_addr;
1125 int ret = 0;
1126 u32 reg;
1127
1128 reg = RTL_R32(TBICSR);
1129 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1130 (duplex == DUPLEX_FULL)) {
1131 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1132 } else if (autoneg == AUTONEG_ENABLE)
1133 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1134 else {
1135 netif_warn(tp, link, dev,
1136 "incorrect speed setting refused in TBI mode\n");
1137 ret = -EOPNOTSUPP;
1138 }
1139
1140 return ret;
1141 }
1142
1143 static int rtl8169_set_speed_xmii(struct net_device *dev,
1144 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1145 {
1146 struct rtl8169_private *tp = netdev_priv(dev);
1147 int giga_ctrl, bmcr;
1148 int rc = -EINVAL;
1149
1150 rtl_writephy(tp, 0x1f, 0x0000);
1151
1152 if (autoneg == AUTONEG_ENABLE) {
1153 int auto_nego;
1154
1155 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1156 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1157 ADVERTISE_100HALF | ADVERTISE_100FULL);
1158
1159 if (adv & ADVERTISED_10baseT_Half)
1160 auto_nego |= ADVERTISE_10HALF;
1161 if (adv & ADVERTISED_10baseT_Full)
1162 auto_nego |= ADVERTISE_10FULL;
1163 if (adv & ADVERTISED_100baseT_Half)
1164 auto_nego |= ADVERTISE_100HALF;
1165 if (adv & ADVERTISED_100baseT_Full)
1166 auto_nego |= ADVERTISE_100FULL;
1167
1168 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1169
1170 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1171 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1172
1173 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1174 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1175 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1176 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1177 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1178 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1179 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1180 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1181 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1182 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1183 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1184 if (adv & ADVERTISED_1000baseT_Half)
1185 giga_ctrl |= ADVERTISE_1000HALF;
1186 if (adv & ADVERTISED_1000baseT_Full)
1187 giga_ctrl |= ADVERTISE_1000FULL;
1188 } else if (adv & (ADVERTISED_1000baseT_Half |
1189 ADVERTISED_1000baseT_Full)) {
1190 netif_info(tp, link, dev,
1191 "PHY does not support 1000Mbps\n");
1192 goto out;
1193 }
1194
1195 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1196
1197 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1198 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1199 } else {
1200 giga_ctrl = 0;
1201
1202 if (speed == SPEED_10)
1203 bmcr = 0;
1204 else if (speed == SPEED_100)
1205 bmcr = BMCR_SPEED100;
1206 else
1207 goto out;
1208
1209 if (duplex == DUPLEX_FULL)
1210 bmcr |= BMCR_FULLDPLX;
1211 }
1212
1213 tp->phy_1000_ctrl_reg = giga_ctrl;
1214
1215 rtl_writephy(tp, MII_BMCR, bmcr);
1216
1217 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1218 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1219 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1220 rtl_writephy(tp, 0x17, 0x2138);
1221 rtl_writephy(tp, 0x0e, 0x0260);
1222 } else {
1223 rtl_writephy(tp, 0x17, 0x2108);
1224 rtl_writephy(tp, 0x0e, 0x0000);
1225 }
1226 }
1227
1228 rc = 0;
1229 out:
1230 return rc;
1231 }
1232
1233 static int rtl8169_set_speed(struct net_device *dev,
1234 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1235 {
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237 int ret;
1238
1239 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1240
1241 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1242 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1243
1244 return ret;
1245 }
1246
1247 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1248 {
1249 struct rtl8169_private *tp = netdev_priv(dev);
1250 unsigned long flags;
1251 int ret;
1252
1253 spin_lock_irqsave(&tp->lock, flags);
1254 ret = rtl8169_set_speed(dev,
1255 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1256 spin_unlock_irqrestore(&tp->lock, flags);
1257
1258 return ret;
1259 }
1260
1261 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1262 {
1263 struct rtl8169_private *tp = netdev_priv(dev);
1264
1265 return tp->cp_cmd & RxChkSum;
1266 }
1267
1268 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1269 {
1270 struct rtl8169_private *tp = netdev_priv(dev);
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 unsigned long flags;
1273
1274 spin_lock_irqsave(&tp->lock, flags);
1275
1276 if (data)
1277 tp->cp_cmd |= RxChkSum;
1278 else
1279 tp->cp_cmd &= ~RxChkSum;
1280
1281 RTL_W16(CPlusCmd, tp->cp_cmd);
1282 RTL_R16(CPlusCmd);
1283
1284 spin_unlock_irqrestore(&tp->lock, flags);
1285
1286 return 0;
1287 }
1288
1289 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1290 struct sk_buff *skb)
1291 {
1292 return (vlan_tx_tag_present(skb)) ?
1293 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1294 }
1295
1296 #define NETIF_F_HW_VLAN_TX_RX (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX)
1297
1298 static void rtl8169_vlan_mode(struct net_device *dev)
1299 {
1300 struct rtl8169_private *tp = netdev_priv(dev);
1301 void __iomem *ioaddr = tp->mmio_addr;
1302 unsigned long flags;
1303
1304 spin_lock_irqsave(&tp->lock, flags);
1305 if (dev->features & NETIF_F_HW_VLAN_RX)
1306 tp->cp_cmd |= RxVlan;
1307 else
1308 tp->cp_cmd &= ~RxVlan;
1309 RTL_W16(CPlusCmd, tp->cp_cmd);
1310 /* PCI commit */
1311 RTL_R16(CPlusCmd);
1312 spin_unlock_irqrestore(&tp->lock, flags);
1313
1314 dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX;
1315 }
1316
1317 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1318 {
1319 u32 opts2 = le32_to_cpu(desc->opts2);
1320
1321 if (opts2 & RxVlanTag)
1322 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1323
1324 desc->opts2 = 0;
1325 }
1326
1327 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1328 {
1329 struct rtl8169_private *tp = netdev_priv(dev);
1330 void __iomem *ioaddr = tp->mmio_addr;
1331 u32 status;
1332
1333 cmd->supported =
1334 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1335 cmd->port = PORT_FIBRE;
1336 cmd->transceiver = XCVR_INTERNAL;
1337
1338 status = RTL_R32(TBICSR);
1339 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1340 cmd->autoneg = !!(status & TBINwEnable);
1341
1342 cmd->speed = SPEED_1000;
1343 cmd->duplex = DUPLEX_FULL; /* Always set */
1344
1345 return 0;
1346 }
1347
1348 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1349 {
1350 struct rtl8169_private *tp = netdev_priv(dev);
1351
1352 return mii_ethtool_gset(&tp->mii, cmd);
1353 }
1354
1355 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1356 {
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 unsigned long flags;
1359 int rc;
1360
1361 spin_lock_irqsave(&tp->lock, flags);
1362
1363 rc = tp->get_settings(dev, cmd);
1364
1365 spin_unlock_irqrestore(&tp->lock, flags);
1366 return rc;
1367 }
1368
1369 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1370 void *p)
1371 {
1372 struct rtl8169_private *tp = netdev_priv(dev);
1373 unsigned long flags;
1374
1375 if (regs->len > R8169_REGS_SIZE)
1376 regs->len = R8169_REGS_SIZE;
1377
1378 spin_lock_irqsave(&tp->lock, flags);
1379 memcpy_fromio(p, tp->mmio_addr, regs->len);
1380 spin_unlock_irqrestore(&tp->lock, flags);
1381 }
1382
1383 static u32 rtl8169_get_msglevel(struct net_device *dev)
1384 {
1385 struct rtl8169_private *tp = netdev_priv(dev);
1386
1387 return tp->msg_enable;
1388 }
1389
1390 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1391 {
1392 struct rtl8169_private *tp = netdev_priv(dev);
1393
1394 tp->msg_enable = value;
1395 }
1396
1397 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1398 "tx_packets",
1399 "rx_packets",
1400 "tx_errors",
1401 "rx_errors",
1402 "rx_missed",
1403 "align_errors",
1404 "tx_single_collisions",
1405 "tx_multi_collisions",
1406 "unicast",
1407 "broadcast",
1408 "multicast",
1409 "tx_aborted",
1410 "tx_underrun",
1411 };
1412
1413 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1414 {
1415 switch (sset) {
1416 case ETH_SS_STATS:
1417 return ARRAY_SIZE(rtl8169_gstrings);
1418 default:
1419 return -EOPNOTSUPP;
1420 }
1421 }
1422
1423 static void rtl8169_update_counters(struct net_device *dev)
1424 {
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 void __iomem *ioaddr = tp->mmio_addr;
1427 struct rtl8169_counters *counters;
1428 dma_addr_t paddr;
1429 u32 cmd;
1430 int wait = 1000;
1431 struct device *d = &tp->pci_dev->dev;
1432
1433 /*
1434 * Some chips are unable to dump tally counters when the receiver
1435 * is disabled.
1436 */
1437 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1438 return;
1439
1440 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1441 if (!counters)
1442 return;
1443
1444 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1445 cmd = (u64)paddr & DMA_BIT_MASK(32);
1446 RTL_W32(CounterAddrLow, cmd);
1447 RTL_W32(CounterAddrLow, cmd | CounterDump);
1448
1449 while (wait--) {
1450 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1451 /* copy updated counters */
1452 memcpy(&tp->counters, counters, sizeof(*counters));
1453 break;
1454 }
1455 udelay(10);
1456 }
1457
1458 RTL_W32(CounterAddrLow, 0);
1459 RTL_W32(CounterAddrHigh, 0);
1460
1461 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1462 }
1463
1464 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1465 struct ethtool_stats *stats, u64 *data)
1466 {
1467 struct rtl8169_private *tp = netdev_priv(dev);
1468
1469 ASSERT_RTNL();
1470
1471 rtl8169_update_counters(dev);
1472
1473 data[0] = le64_to_cpu(tp->counters.tx_packets);
1474 data[1] = le64_to_cpu(tp->counters.rx_packets);
1475 data[2] = le64_to_cpu(tp->counters.tx_errors);
1476 data[3] = le32_to_cpu(tp->counters.rx_errors);
1477 data[4] = le16_to_cpu(tp->counters.rx_missed);
1478 data[5] = le16_to_cpu(tp->counters.align_errors);
1479 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1480 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1481 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1482 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1483 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1484 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1485 data[12] = le16_to_cpu(tp->counters.tx_underun);
1486 }
1487
1488 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1489 {
1490 switch(stringset) {
1491 case ETH_SS_STATS:
1492 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1493 break;
1494 }
1495 }
1496
1497 static int rtl8169_set_flags(struct net_device *dev, u32 data)
1498 {
1499 struct rtl8169_private *tp = netdev_priv(dev);
1500 unsigned long old_feat = dev->features;
1501 int rc;
1502
1503 if ((tp->mac_version == RTL_GIGA_MAC_VER_05) &&
1504 !(data & ETH_FLAG_RXVLAN)) {
1505 netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n");
1506 return -EINVAL;
1507 }
1508
1509 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN);
1510 if (rc)
1511 return rc;
1512
1513 if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX)
1514 rtl8169_vlan_mode(dev);
1515
1516 return 0;
1517 }
1518
1519 static const struct ethtool_ops rtl8169_ethtool_ops = {
1520 .get_drvinfo = rtl8169_get_drvinfo,
1521 .get_regs_len = rtl8169_get_regs_len,
1522 .get_link = ethtool_op_get_link,
1523 .get_settings = rtl8169_get_settings,
1524 .set_settings = rtl8169_set_settings,
1525 .get_msglevel = rtl8169_get_msglevel,
1526 .set_msglevel = rtl8169_set_msglevel,
1527 .get_rx_csum = rtl8169_get_rx_csum,
1528 .set_rx_csum = rtl8169_set_rx_csum,
1529 .set_tx_csum = ethtool_op_set_tx_csum,
1530 .set_sg = ethtool_op_set_sg,
1531 .set_tso = ethtool_op_set_tso,
1532 .get_regs = rtl8169_get_regs,
1533 .get_wol = rtl8169_get_wol,
1534 .set_wol = rtl8169_set_wol,
1535 .get_strings = rtl8169_get_strings,
1536 .get_sset_count = rtl8169_get_sset_count,
1537 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1538 .set_flags = rtl8169_set_flags,
1539 .get_flags = ethtool_op_get_flags,
1540 };
1541
1542 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1543 void __iomem *ioaddr)
1544 {
1545 /*
1546 * The driver currently handles the 8168Bf and the 8168Be identically
1547 * but they can be identified more specifically through the test below
1548 * if needed:
1549 *
1550 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1551 *
1552 * Same thing for the 8101Eb and the 8101Ec:
1553 *
1554 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1555 */
1556 static const struct {
1557 u32 mask;
1558 u32 val;
1559 int mac_version;
1560 } mac_info[] = {
1561 /* 8168D family. */
1562 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1563 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1564 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1565
1566 /* 8168DP family. */
1567 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1568 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1569
1570 /* 8168C family. */
1571 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1572 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1573 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1574 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1575 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1576 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1577 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1578 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1579 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1580
1581 /* 8168B family. */
1582 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1583 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1584 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1585 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1586
1587 /* 8101 family. */
1588 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1589 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1590 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1591 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1592 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1593 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1594 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1595 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1596 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1597 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1598 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1599 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1600 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1601 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1602 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1603 /* FIXME: where did these entries come from ? -- FR */
1604 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1605 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1606
1607 /* 8110 family. */
1608 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1609 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1610 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1611 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1612 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1613 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1614
1615 /* Catch-all */
1616 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1617 }, *p = mac_info;
1618 u32 reg;
1619
1620 reg = RTL_R32(TxConfig);
1621 while ((reg & p->mask) != p->val)
1622 p++;
1623 tp->mac_version = p->mac_version;
1624 }
1625
1626 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1627 {
1628 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1629 }
1630
1631 struct phy_reg {
1632 u16 reg;
1633 u16 val;
1634 };
1635
1636 static void rtl_writephy_batch(struct rtl8169_private *tp,
1637 const struct phy_reg *regs, int len)
1638 {
1639 while (len-- > 0) {
1640 rtl_writephy(tp, regs->reg, regs->val);
1641 regs++;
1642 }
1643 }
1644
1645 #define PHY_READ 0x00000000
1646 #define PHY_DATA_OR 0x10000000
1647 #define PHY_DATA_AND 0x20000000
1648 #define PHY_BJMPN 0x30000000
1649 #define PHY_READ_EFUSE 0x40000000
1650 #define PHY_READ_MAC_BYTE 0x50000000
1651 #define PHY_WRITE_MAC_BYTE 0x60000000
1652 #define PHY_CLEAR_READCOUNT 0x70000000
1653 #define PHY_WRITE 0x80000000
1654 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1655 #define PHY_COMP_EQ_SKIPN 0xa0000000
1656 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1657 #define PHY_WRITE_PREVIOUS 0xc0000000
1658 #define PHY_SKIPN 0xd0000000
1659 #define PHY_DELAY_MS 0xe0000000
1660 #define PHY_WRITE_ERI_WORD 0xf0000000
1661
1662 static void
1663 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1664 {
1665 __le32 *phytable = (__le32 *)fw->data;
1666 struct net_device *dev = tp->dev;
1667 size_t index, fw_size = fw->size / sizeof(*phytable);
1668 u32 predata, count;
1669
1670 if (fw->size % sizeof(*phytable)) {
1671 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1672 return;
1673 }
1674
1675 for (index = 0; index < fw_size; index++) {
1676 u32 action = le32_to_cpu(phytable[index]);
1677 u32 regno = (action & 0x0fff0000) >> 16;
1678
1679 switch(action & 0xf0000000) {
1680 case PHY_READ:
1681 case PHY_DATA_OR:
1682 case PHY_DATA_AND:
1683 case PHY_READ_EFUSE:
1684 case PHY_CLEAR_READCOUNT:
1685 case PHY_WRITE:
1686 case PHY_WRITE_PREVIOUS:
1687 case PHY_DELAY_MS:
1688 break;
1689
1690 case PHY_BJMPN:
1691 if (regno > index) {
1692 netif_err(tp, probe, tp->dev,
1693 "Out of range of firmware\n");
1694 return;
1695 }
1696 break;
1697 case PHY_READCOUNT_EQ_SKIP:
1698 if (index + 2 >= fw_size) {
1699 netif_err(tp, probe, tp->dev,
1700 "Out of range of firmware\n");
1701 return;
1702 }
1703 break;
1704 case PHY_COMP_EQ_SKIPN:
1705 case PHY_COMP_NEQ_SKIPN:
1706 case PHY_SKIPN:
1707 if (index + 1 + regno >= fw_size) {
1708 netif_err(tp, probe, tp->dev,
1709 "Out of range of firmware\n");
1710 return;
1711 }
1712 break;
1713
1714 case PHY_READ_MAC_BYTE:
1715 case PHY_WRITE_MAC_BYTE:
1716 case PHY_WRITE_ERI_WORD:
1717 default:
1718 netif_err(tp, probe, tp->dev,
1719 "Invalid action 0x%08x\n", action);
1720 return;
1721 }
1722 }
1723
1724 predata = 0;
1725 count = 0;
1726
1727 for (index = 0; index < fw_size; ) {
1728 u32 action = le32_to_cpu(phytable[index]);
1729 u32 data = action & 0x0000ffff;
1730 u32 regno = (action & 0x0fff0000) >> 16;
1731
1732 if (!action)
1733 break;
1734
1735 switch(action & 0xf0000000) {
1736 case PHY_READ:
1737 predata = rtl_readphy(tp, regno);
1738 count++;
1739 index++;
1740 break;
1741 case PHY_DATA_OR:
1742 predata |= data;
1743 index++;
1744 break;
1745 case PHY_DATA_AND:
1746 predata &= data;
1747 index++;
1748 break;
1749 case PHY_BJMPN:
1750 index -= regno;
1751 break;
1752 case PHY_READ_EFUSE:
1753 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1754 index++;
1755 break;
1756 case PHY_CLEAR_READCOUNT:
1757 count = 0;
1758 index++;
1759 break;
1760 case PHY_WRITE:
1761 rtl_writephy(tp, regno, data);
1762 index++;
1763 break;
1764 case PHY_READCOUNT_EQ_SKIP:
1765 if (count == data)
1766 index += 2;
1767 else
1768 index += 1;
1769 break;
1770 case PHY_COMP_EQ_SKIPN:
1771 if (predata == data)
1772 index += regno;
1773 index++;
1774 break;
1775 case PHY_COMP_NEQ_SKIPN:
1776 if (predata != data)
1777 index += regno;
1778 index++;
1779 break;
1780 case PHY_WRITE_PREVIOUS:
1781 rtl_writephy(tp, regno, predata);
1782 index++;
1783 break;
1784 case PHY_SKIPN:
1785 index += regno + 1;
1786 break;
1787 case PHY_DELAY_MS:
1788 mdelay(data);
1789 index++;
1790 break;
1791
1792 case PHY_READ_MAC_BYTE:
1793 case PHY_WRITE_MAC_BYTE:
1794 case PHY_WRITE_ERI_WORD:
1795 default:
1796 BUG();
1797 }
1798 }
1799 }
1800
1801 static void rtl_release_firmware(struct rtl8169_private *tp)
1802 {
1803 if (!IS_ERR_OR_NULL(tp->fw))
1804 release_firmware(tp->fw);
1805 tp->fw = RTL_FIRMWARE_UNKNOWN;
1806 }
1807
1808 static void rtl_apply_firmware(struct rtl8169_private *tp)
1809 {
1810 const struct firmware *fw = tp->fw;
1811
1812 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1813 if (!IS_ERR_OR_NULL(fw))
1814 rtl_phy_write_fw(tp, fw);
1815 }
1816
1817 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1818 {
1819 if (rtl_readphy(tp, reg) != val)
1820 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1821 else
1822 rtl_apply_firmware(tp);
1823 }
1824
1825 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1826 {
1827 static const struct phy_reg phy_reg_init[] = {
1828 { 0x1f, 0x0001 },
1829 { 0x06, 0x006e },
1830 { 0x08, 0x0708 },
1831 { 0x15, 0x4000 },
1832 { 0x18, 0x65c7 },
1833
1834 { 0x1f, 0x0001 },
1835 { 0x03, 0x00a1 },
1836 { 0x02, 0x0008 },
1837 { 0x01, 0x0120 },
1838 { 0x00, 0x1000 },
1839 { 0x04, 0x0800 },
1840 { 0x04, 0x0000 },
1841
1842 { 0x03, 0xff41 },
1843 { 0x02, 0xdf60 },
1844 { 0x01, 0x0140 },
1845 { 0x00, 0x0077 },
1846 { 0x04, 0x7800 },
1847 { 0x04, 0x7000 },
1848
1849 { 0x03, 0x802f },
1850 { 0x02, 0x4f02 },
1851 { 0x01, 0x0409 },
1852 { 0x00, 0xf0f9 },
1853 { 0x04, 0x9800 },
1854 { 0x04, 0x9000 },
1855
1856 { 0x03, 0xdf01 },
1857 { 0x02, 0xdf20 },
1858 { 0x01, 0xff95 },
1859 { 0x00, 0xba00 },
1860 { 0x04, 0xa800 },
1861 { 0x04, 0xa000 },
1862
1863 { 0x03, 0xff41 },
1864 { 0x02, 0xdf20 },
1865 { 0x01, 0x0140 },
1866 { 0x00, 0x00bb },
1867 { 0x04, 0xb800 },
1868 { 0x04, 0xb000 },
1869
1870 { 0x03, 0xdf41 },
1871 { 0x02, 0xdc60 },
1872 { 0x01, 0x6340 },
1873 { 0x00, 0x007d },
1874 { 0x04, 0xd800 },
1875 { 0x04, 0xd000 },
1876
1877 { 0x03, 0xdf01 },
1878 { 0x02, 0xdf20 },
1879 { 0x01, 0x100a },
1880 { 0x00, 0xa0ff },
1881 { 0x04, 0xf800 },
1882 { 0x04, 0xf000 },
1883
1884 { 0x1f, 0x0000 },
1885 { 0x0b, 0x0000 },
1886 { 0x00, 0x9200 }
1887 };
1888
1889 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1890 }
1891
1892 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1893 {
1894 static const struct phy_reg phy_reg_init[] = {
1895 { 0x1f, 0x0002 },
1896 { 0x01, 0x90d0 },
1897 { 0x1f, 0x0000 }
1898 };
1899
1900 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1901 }
1902
1903 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1904 {
1905 struct pci_dev *pdev = tp->pci_dev;
1906 u16 vendor_id, device_id;
1907
1908 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1909 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1910
1911 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1912 return;
1913
1914 rtl_writephy(tp, 0x1f, 0x0001);
1915 rtl_writephy(tp, 0x10, 0xf01b);
1916 rtl_writephy(tp, 0x1f, 0x0000);
1917 }
1918
1919 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1920 {
1921 static const struct phy_reg phy_reg_init[] = {
1922 { 0x1f, 0x0001 },
1923 { 0x04, 0x0000 },
1924 { 0x03, 0x00a1 },
1925 { 0x02, 0x0008 },
1926 { 0x01, 0x0120 },
1927 { 0x00, 0x1000 },
1928 { 0x04, 0x0800 },
1929 { 0x04, 0x9000 },
1930 { 0x03, 0x802f },
1931 { 0x02, 0x4f02 },
1932 { 0x01, 0x0409 },
1933 { 0x00, 0xf099 },
1934 { 0x04, 0x9800 },
1935 { 0x04, 0xa000 },
1936 { 0x03, 0xdf01 },
1937 { 0x02, 0xdf20 },
1938 { 0x01, 0xff95 },
1939 { 0x00, 0xba00 },
1940 { 0x04, 0xa800 },
1941 { 0x04, 0xf000 },
1942 { 0x03, 0xdf01 },
1943 { 0x02, 0xdf20 },
1944 { 0x01, 0x101a },
1945 { 0x00, 0xa0ff },
1946 { 0x04, 0xf800 },
1947 { 0x04, 0x0000 },
1948 { 0x1f, 0x0000 },
1949
1950 { 0x1f, 0x0001 },
1951 { 0x10, 0xf41b },
1952 { 0x14, 0xfb54 },
1953 { 0x18, 0xf5c7 },
1954 { 0x1f, 0x0000 },
1955
1956 { 0x1f, 0x0001 },
1957 { 0x17, 0x0cc0 },
1958 { 0x1f, 0x0000 }
1959 };
1960
1961 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1962
1963 rtl8169scd_hw_phy_config_quirk(tp);
1964 }
1965
1966 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1967 {
1968 static const struct phy_reg phy_reg_init[] = {
1969 { 0x1f, 0x0001 },
1970 { 0x04, 0x0000 },
1971 { 0x03, 0x00a1 },
1972 { 0x02, 0x0008 },
1973 { 0x01, 0x0120 },
1974 { 0x00, 0x1000 },
1975 { 0x04, 0x0800 },
1976 { 0x04, 0x9000 },
1977 { 0x03, 0x802f },
1978 { 0x02, 0x4f02 },
1979 { 0x01, 0x0409 },
1980 { 0x00, 0xf099 },
1981 { 0x04, 0x9800 },
1982 { 0x04, 0xa000 },
1983 { 0x03, 0xdf01 },
1984 { 0x02, 0xdf20 },
1985 { 0x01, 0xff95 },
1986 { 0x00, 0xba00 },
1987 { 0x04, 0xa800 },
1988 { 0x04, 0xf000 },
1989 { 0x03, 0xdf01 },
1990 { 0x02, 0xdf20 },
1991 { 0x01, 0x101a },
1992 { 0x00, 0xa0ff },
1993 { 0x04, 0xf800 },
1994 { 0x04, 0x0000 },
1995 { 0x1f, 0x0000 },
1996
1997 { 0x1f, 0x0001 },
1998 { 0x0b, 0x8480 },
1999 { 0x1f, 0x0000 },
2000
2001 { 0x1f, 0x0001 },
2002 { 0x18, 0x67c7 },
2003 { 0x04, 0x2000 },
2004 { 0x03, 0x002f },
2005 { 0x02, 0x4360 },
2006 { 0x01, 0x0109 },
2007 { 0x00, 0x3022 },
2008 { 0x04, 0x2800 },
2009 { 0x1f, 0x0000 },
2010
2011 { 0x1f, 0x0001 },
2012 { 0x17, 0x0cc0 },
2013 { 0x1f, 0x0000 }
2014 };
2015
2016 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2017 }
2018
2019 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2020 {
2021 static const struct phy_reg phy_reg_init[] = {
2022 { 0x10, 0xf41b },
2023 { 0x1f, 0x0000 }
2024 };
2025
2026 rtl_writephy(tp, 0x1f, 0x0001);
2027 rtl_patchphy(tp, 0x16, 1 << 0);
2028
2029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2030 }
2031
2032 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2033 {
2034 static const struct phy_reg phy_reg_init[] = {
2035 { 0x1f, 0x0001 },
2036 { 0x10, 0xf41b },
2037 { 0x1f, 0x0000 }
2038 };
2039
2040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2041 }
2042
2043 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2044 {
2045 static const struct phy_reg phy_reg_init[] = {
2046 { 0x1f, 0x0000 },
2047 { 0x1d, 0x0f00 },
2048 { 0x1f, 0x0002 },
2049 { 0x0c, 0x1ec8 },
2050 { 0x1f, 0x0000 }
2051 };
2052
2053 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2054 }
2055
2056 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2057 {
2058 static const struct phy_reg phy_reg_init[] = {
2059 { 0x1f, 0x0001 },
2060 { 0x1d, 0x3d98 },
2061 { 0x1f, 0x0000 }
2062 };
2063
2064 rtl_writephy(tp, 0x1f, 0x0000);
2065 rtl_patchphy(tp, 0x14, 1 << 5);
2066 rtl_patchphy(tp, 0x0d, 1 << 5);
2067
2068 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2069 }
2070
2071 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2072 {
2073 static const struct phy_reg phy_reg_init[] = {
2074 { 0x1f, 0x0001 },
2075 { 0x12, 0x2300 },
2076 { 0x1f, 0x0002 },
2077 { 0x00, 0x88d4 },
2078 { 0x01, 0x82b1 },
2079 { 0x03, 0x7002 },
2080 { 0x08, 0x9e30 },
2081 { 0x09, 0x01f0 },
2082 { 0x0a, 0x5500 },
2083 { 0x0c, 0x00c8 },
2084 { 0x1f, 0x0003 },
2085 { 0x12, 0xc096 },
2086 { 0x16, 0x000a },
2087 { 0x1f, 0x0000 },
2088 { 0x1f, 0x0000 },
2089 { 0x09, 0x2000 },
2090 { 0x09, 0x0000 }
2091 };
2092
2093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2094
2095 rtl_patchphy(tp, 0x14, 1 << 5);
2096 rtl_patchphy(tp, 0x0d, 1 << 5);
2097 rtl_writephy(tp, 0x1f, 0x0000);
2098 }
2099
2100 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2101 {
2102 static const struct phy_reg phy_reg_init[] = {
2103 { 0x1f, 0x0001 },
2104 { 0x12, 0x2300 },
2105 { 0x03, 0x802f },
2106 { 0x02, 0x4f02 },
2107 { 0x01, 0x0409 },
2108 { 0x00, 0xf099 },
2109 { 0x04, 0x9800 },
2110 { 0x04, 0x9000 },
2111 { 0x1d, 0x3d98 },
2112 { 0x1f, 0x0002 },
2113 { 0x0c, 0x7eb8 },
2114 { 0x06, 0x0761 },
2115 { 0x1f, 0x0003 },
2116 { 0x16, 0x0f0a },
2117 { 0x1f, 0x0000 }
2118 };
2119
2120 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2121
2122 rtl_patchphy(tp, 0x16, 1 << 0);
2123 rtl_patchphy(tp, 0x14, 1 << 5);
2124 rtl_patchphy(tp, 0x0d, 1 << 5);
2125 rtl_writephy(tp, 0x1f, 0x0000);
2126 }
2127
2128 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2129 {
2130 static const struct phy_reg phy_reg_init[] = {
2131 { 0x1f, 0x0001 },
2132 { 0x12, 0x2300 },
2133 { 0x1d, 0x3d98 },
2134 { 0x1f, 0x0002 },
2135 { 0x0c, 0x7eb8 },
2136 { 0x06, 0x5461 },
2137 { 0x1f, 0x0003 },
2138 { 0x16, 0x0f0a },
2139 { 0x1f, 0x0000 }
2140 };
2141
2142 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2143
2144 rtl_patchphy(tp, 0x16, 1 << 0);
2145 rtl_patchphy(tp, 0x14, 1 << 5);
2146 rtl_patchphy(tp, 0x0d, 1 << 5);
2147 rtl_writephy(tp, 0x1f, 0x0000);
2148 }
2149
2150 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2151 {
2152 rtl8168c_3_hw_phy_config(tp);
2153 }
2154
2155 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2156 {
2157 static const struct phy_reg phy_reg_init_0[] = {
2158 /* Channel Estimation */
2159 { 0x1f, 0x0001 },
2160 { 0x06, 0x4064 },
2161 { 0x07, 0x2863 },
2162 { 0x08, 0x059c },
2163 { 0x09, 0x26b4 },
2164 { 0x0a, 0x6a19 },
2165 { 0x0b, 0xdcc8 },
2166 { 0x10, 0xf06d },
2167 { 0x14, 0x7f68 },
2168 { 0x18, 0x7fd9 },
2169 { 0x1c, 0xf0ff },
2170 { 0x1d, 0x3d9c },
2171 { 0x1f, 0x0003 },
2172 { 0x12, 0xf49f },
2173 { 0x13, 0x070b },
2174 { 0x1a, 0x05ad },
2175 { 0x14, 0x94c0 },
2176
2177 /*
2178 * Tx Error Issue
2179 * enhance line driver power
2180 */
2181 { 0x1f, 0x0002 },
2182 { 0x06, 0x5561 },
2183 { 0x1f, 0x0005 },
2184 { 0x05, 0x8332 },
2185 { 0x06, 0x5561 },
2186
2187 /*
2188 * Can not link to 1Gbps with bad cable
2189 * Decrease SNR threshold form 21.07dB to 19.04dB
2190 */
2191 { 0x1f, 0x0001 },
2192 { 0x17, 0x0cc0 },
2193
2194 { 0x1f, 0x0000 },
2195 { 0x0d, 0xf880 }
2196 };
2197 void __iomem *ioaddr = tp->mmio_addr;
2198
2199 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2200
2201 /*
2202 * Rx Error Issue
2203 * Fine Tune Switching regulator parameter
2204 */
2205 rtl_writephy(tp, 0x1f, 0x0002);
2206 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2207 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2208
2209 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2210 static const struct phy_reg phy_reg_init[] = {
2211 { 0x1f, 0x0002 },
2212 { 0x05, 0x669a },
2213 { 0x1f, 0x0005 },
2214 { 0x05, 0x8330 },
2215 { 0x06, 0x669a },
2216 { 0x1f, 0x0002 }
2217 };
2218 int val;
2219
2220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2221
2222 val = rtl_readphy(tp, 0x0d);
2223
2224 if ((val & 0x00ff) != 0x006c) {
2225 static const u32 set[] = {
2226 0x0065, 0x0066, 0x0067, 0x0068,
2227 0x0069, 0x006a, 0x006b, 0x006c
2228 };
2229 int i;
2230
2231 rtl_writephy(tp, 0x1f, 0x0002);
2232
2233 val &= 0xff00;
2234 for (i = 0; i < ARRAY_SIZE(set); i++)
2235 rtl_writephy(tp, 0x0d, val | set[i]);
2236 }
2237 } else {
2238 static const struct phy_reg phy_reg_init[] = {
2239 { 0x1f, 0x0002 },
2240 { 0x05, 0x6662 },
2241 { 0x1f, 0x0005 },
2242 { 0x05, 0x8330 },
2243 { 0x06, 0x6662 }
2244 };
2245
2246 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2247 }
2248
2249 /* RSET couple improve */
2250 rtl_writephy(tp, 0x1f, 0x0002);
2251 rtl_patchphy(tp, 0x0d, 0x0300);
2252 rtl_patchphy(tp, 0x0f, 0x0010);
2253
2254 /* Fine tune PLL performance */
2255 rtl_writephy(tp, 0x1f, 0x0002);
2256 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2257 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2258
2259 rtl_writephy(tp, 0x1f, 0x0005);
2260 rtl_writephy(tp, 0x05, 0x001b);
2261
2262 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2263
2264 rtl_writephy(tp, 0x1f, 0x0000);
2265 }
2266
2267 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2268 {
2269 static const struct phy_reg phy_reg_init_0[] = {
2270 /* Channel Estimation */
2271 { 0x1f, 0x0001 },
2272 { 0x06, 0x4064 },
2273 { 0x07, 0x2863 },
2274 { 0x08, 0x059c },
2275 { 0x09, 0x26b4 },
2276 { 0x0a, 0x6a19 },
2277 { 0x0b, 0xdcc8 },
2278 { 0x10, 0xf06d },
2279 { 0x14, 0x7f68 },
2280 { 0x18, 0x7fd9 },
2281 { 0x1c, 0xf0ff },
2282 { 0x1d, 0x3d9c },
2283 { 0x1f, 0x0003 },
2284 { 0x12, 0xf49f },
2285 { 0x13, 0x070b },
2286 { 0x1a, 0x05ad },
2287 { 0x14, 0x94c0 },
2288
2289 /*
2290 * Tx Error Issue
2291 * enhance line driver power
2292 */
2293 { 0x1f, 0x0002 },
2294 { 0x06, 0x5561 },
2295 { 0x1f, 0x0005 },
2296 { 0x05, 0x8332 },
2297 { 0x06, 0x5561 },
2298
2299 /*
2300 * Can not link to 1Gbps with bad cable
2301 * Decrease SNR threshold form 21.07dB to 19.04dB
2302 */
2303 { 0x1f, 0x0001 },
2304 { 0x17, 0x0cc0 },
2305
2306 { 0x1f, 0x0000 },
2307 { 0x0d, 0xf880 }
2308 };
2309 void __iomem *ioaddr = tp->mmio_addr;
2310
2311 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2312
2313 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2314 static const struct phy_reg phy_reg_init[] = {
2315 { 0x1f, 0x0002 },
2316 { 0x05, 0x669a },
2317 { 0x1f, 0x0005 },
2318 { 0x05, 0x8330 },
2319 { 0x06, 0x669a },
2320
2321 { 0x1f, 0x0002 }
2322 };
2323 int val;
2324
2325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326
2327 val = rtl_readphy(tp, 0x0d);
2328 if ((val & 0x00ff) != 0x006c) {
2329 static const u32 set[] = {
2330 0x0065, 0x0066, 0x0067, 0x0068,
2331 0x0069, 0x006a, 0x006b, 0x006c
2332 };
2333 int i;
2334
2335 rtl_writephy(tp, 0x1f, 0x0002);
2336
2337 val &= 0xff00;
2338 for (i = 0; i < ARRAY_SIZE(set); i++)
2339 rtl_writephy(tp, 0x0d, val | set[i]);
2340 }
2341 } else {
2342 static const struct phy_reg phy_reg_init[] = {
2343 { 0x1f, 0x0002 },
2344 { 0x05, 0x2642 },
2345 { 0x1f, 0x0005 },
2346 { 0x05, 0x8330 },
2347 { 0x06, 0x2642 }
2348 };
2349
2350 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2351 }
2352
2353 /* Fine tune PLL performance */
2354 rtl_writephy(tp, 0x1f, 0x0002);
2355 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2356 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2357
2358 /* Switching regulator Slew rate */
2359 rtl_writephy(tp, 0x1f, 0x0002);
2360 rtl_patchphy(tp, 0x0f, 0x0017);
2361
2362 rtl_writephy(tp, 0x1f, 0x0005);
2363 rtl_writephy(tp, 0x05, 0x001b);
2364
2365 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2366
2367 rtl_writephy(tp, 0x1f, 0x0000);
2368 }
2369
2370 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2371 {
2372 static const struct phy_reg phy_reg_init[] = {
2373 { 0x1f, 0x0002 },
2374 { 0x10, 0x0008 },
2375 { 0x0d, 0x006c },
2376
2377 { 0x1f, 0x0000 },
2378 { 0x0d, 0xf880 },
2379
2380 { 0x1f, 0x0001 },
2381 { 0x17, 0x0cc0 },
2382
2383 { 0x1f, 0x0001 },
2384 { 0x0b, 0xa4d8 },
2385 { 0x09, 0x281c },
2386 { 0x07, 0x2883 },
2387 { 0x0a, 0x6b35 },
2388 { 0x1d, 0x3da4 },
2389 { 0x1c, 0xeffd },
2390 { 0x14, 0x7f52 },
2391 { 0x18, 0x7fc6 },
2392 { 0x08, 0x0601 },
2393 { 0x06, 0x4063 },
2394 { 0x10, 0xf074 },
2395 { 0x1f, 0x0003 },
2396 { 0x13, 0x0789 },
2397 { 0x12, 0xf4bd },
2398 { 0x1a, 0x04fd },
2399 { 0x14, 0x84b0 },
2400 { 0x1f, 0x0000 },
2401 { 0x00, 0x9200 },
2402
2403 { 0x1f, 0x0005 },
2404 { 0x01, 0x0340 },
2405 { 0x1f, 0x0001 },
2406 { 0x04, 0x4000 },
2407 { 0x03, 0x1d21 },
2408 { 0x02, 0x0c32 },
2409 { 0x01, 0x0200 },
2410 { 0x00, 0x5554 },
2411 { 0x04, 0x4800 },
2412 { 0x04, 0x4000 },
2413 { 0x04, 0xf000 },
2414 { 0x03, 0xdf01 },
2415 { 0x02, 0xdf20 },
2416 { 0x01, 0x101a },
2417 { 0x00, 0xa0ff },
2418 { 0x04, 0xf800 },
2419 { 0x04, 0xf000 },
2420 { 0x1f, 0x0000 },
2421
2422 { 0x1f, 0x0007 },
2423 { 0x1e, 0x0023 },
2424 { 0x16, 0x0000 },
2425 { 0x1f, 0x0000 }
2426 };
2427
2428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2429 }
2430
2431 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2432 {
2433 static const struct phy_reg phy_reg_init[] = {
2434 { 0x1f, 0x0001 },
2435 { 0x17, 0x0cc0 },
2436
2437 { 0x1f, 0x0007 },
2438 { 0x1e, 0x002d },
2439 { 0x18, 0x0040 },
2440 { 0x1f, 0x0000 }
2441 };
2442
2443 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2444 rtl_patchphy(tp, 0x0d, 1 << 5);
2445 }
2446
2447 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2448 {
2449 static const struct phy_reg phy_reg_init[] = {
2450 { 0x1f, 0x0003 },
2451 { 0x08, 0x441d },
2452 { 0x01, 0x9100 },
2453 { 0x1f, 0x0000 }
2454 };
2455
2456 rtl_writephy(tp, 0x1f, 0x0000);
2457 rtl_patchphy(tp, 0x11, 1 << 12);
2458 rtl_patchphy(tp, 0x19, 1 << 13);
2459 rtl_patchphy(tp, 0x10, 1 << 15);
2460
2461 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2462 }
2463
2464 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2465 {
2466 static const struct phy_reg phy_reg_init[] = {
2467 { 0x1f, 0x0005 },
2468 { 0x1a, 0x0000 },
2469 { 0x1f, 0x0000 },
2470
2471 { 0x1f, 0x0004 },
2472 { 0x1c, 0x0000 },
2473 { 0x1f, 0x0000 },
2474
2475 { 0x1f, 0x0001 },
2476 { 0x15, 0x7701 },
2477 { 0x1f, 0x0000 }
2478 };
2479
2480 /* Disable ALDPS before ram code */
2481 rtl_writephy(tp, 0x1f, 0x0000);
2482 rtl_writephy(tp, 0x18, 0x0310);
2483 msleep(100);
2484
2485 rtl_apply_firmware(tp);
2486
2487 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2488 }
2489
2490 static void rtl_hw_phy_config(struct net_device *dev)
2491 {
2492 struct rtl8169_private *tp = netdev_priv(dev);
2493
2494 rtl8169_print_mac_version(tp);
2495
2496 switch (tp->mac_version) {
2497 case RTL_GIGA_MAC_VER_01:
2498 break;
2499 case RTL_GIGA_MAC_VER_02:
2500 case RTL_GIGA_MAC_VER_03:
2501 rtl8169s_hw_phy_config(tp);
2502 break;
2503 case RTL_GIGA_MAC_VER_04:
2504 rtl8169sb_hw_phy_config(tp);
2505 break;
2506 case RTL_GIGA_MAC_VER_05:
2507 rtl8169scd_hw_phy_config(tp);
2508 break;
2509 case RTL_GIGA_MAC_VER_06:
2510 rtl8169sce_hw_phy_config(tp);
2511 break;
2512 case RTL_GIGA_MAC_VER_07:
2513 case RTL_GIGA_MAC_VER_08:
2514 case RTL_GIGA_MAC_VER_09:
2515 rtl8102e_hw_phy_config(tp);
2516 break;
2517 case RTL_GIGA_MAC_VER_11:
2518 rtl8168bb_hw_phy_config(tp);
2519 break;
2520 case RTL_GIGA_MAC_VER_12:
2521 rtl8168bef_hw_phy_config(tp);
2522 break;
2523 case RTL_GIGA_MAC_VER_17:
2524 rtl8168bef_hw_phy_config(tp);
2525 break;
2526 case RTL_GIGA_MAC_VER_18:
2527 rtl8168cp_1_hw_phy_config(tp);
2528 break;
2529 case RTL_GIGA_MAC_VER_19:
2530 rtl8168c_1_hw_phy_config(tp);
2531 break;
2532 case RTL_GIGA_MAC_VER_20:
2533 rtl8168c_2_hw_phy_config(tp);
2534 break;
2535 case RTL_GIGA_MAC_VER_21:
2536 rtl8168c_3_hw_phy_config(tp);
2537 break;
2538 case RTL_GIGA_MAC_VER_22:
2539 rtl8168c_4_hw_phy_config(tp);
2540 break;
2541 case RTL_GIGA_MAC_VER_23:
2542 case RTL_GIGA_MAC_VER_24:
2543 rtl8168cp_2_hw_phy_config(tp);
2544 break;
2545 case RTL_GIGA_MAC_VER_25:
2546 rtl8168d_1_hw_phy_config(tp);
2547 break;
2548 case RTL_GIGA_MAC_VER_26:
2549 rtl8168d_2_hw_phy_config(tp);
2550 break;
2551 case RTL_GIGA_MAC_VER_27:
2552 rtl8168d_3_hw_phy_config(tp);
2553 break;
2554 case RTL_GIGA_MAC_VER_28:
2555 rtl8168d_4_hw_phy_config(tp);
2556 break;
2557 case RTL_GIGA_MAC_VER_29:
2558 case RTL_GIGA_MAC_VER_30:
2559 rtl8105e_hw_phy_config(tp);
2560 break;
2561
2562 default:
2563 break;
2564 }
2565 }
2566
2567 static void rtl8169_phy_timer(unsigned long __opaque)
2568 {
2569 struct net_device *dev = (struct net_device *)__opaque;
2570 struct rtl8169_private *tp = netdev_priv(dev);
2571 struct timer_list *timer = &tp->timer;
2572 void __iomem *ioaddr = tp->mmio_addr;
2573 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2574
2575 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2576
2577 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2578 return;
2579
2580 spin_lock_irq(&tp->lock);
2581
2582 if (tp->phy_reset_pending(tp)) {
2583 /*
2584 * A busy loop could burn quite a few cycles on nowadays CPU.
2585 * Let's delay the execution of the timer for a few ticks.
2586 */
2587 timeout = HZ/10;
2588 goto out_mod_timer;
2589 }
2590
2591 if (tp->link_ok(ioaddr))
2592 goto out_unlock;
2593
2594 netif_warn(tp, link, dev, "PHY reset until link up\n");
2595
2596 tp->phy_reset_enable(tp);
2597
2598 out_mod_timer:
2599 mod_timer(timer, jiffies + timeout);
2600 out_unlock:
2601 spin_unlock_irq(&tp->lock);
2602 }
2603
2604 static inline void rtl8169_delete_timer(struct net_device *dev)
2605 {
2606 struct rtl8169_private *tp = netdev_priv(dev);
2607 struct timer_list *timer = &tp->timer;
2608
2609 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2610 return;
2611
2612 del_timer_sync(timer);
2613 }
2614
2615 static inline void rtl8169_request_timer(struct net_device *dev)
2616 {
2617 struct rtl8169_private *tp = netdev_priv(dev);
2618 struct timer_list *timer = &tp->timer;
2619
2620 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2621 return;
2622
2623 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2624 }
2625
2626 #ifdef CONFIG_NET_POLL_CONTROLLER
2627 /*
2628 * Polling 'interrupt' - used by things like netconsole to send skbs
2629 * without having to re-enable interrupts. It's not called while
2630 * the interrupt routine is executing.
2631 */
2632 static void rtl8169_netpoll(struct net_device *dev)
2633 {
2634 struct rtl8169_private *tp = netdev_priv(dev);
2635 struct pci_dev *pdev = tp->pci_dev;
2636
2637 disable_irq(pdev->irq);
2638 rtl8169_interrupt(pdev->irq, dev);
2639 enable_irq(pdev->irq);
2640 }
2641 #endif
2642
2643 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2644 void __iomem *ioaddr)
2645 {
2646 iounmap(ioaddr);
2647 pci_release_regions(pdev);
2648 pci_clear_mwi(pdev);
2649 pci_disable_device(pdev);
2650 free_netdev(dev);
2651 }
2652
2653 static void rtl8169_phy_reset(struct net_device *dev,
2654 struct rtl8169_private *tp)
2655 {
2656 unsigned int i;
2657
2658 tp->phy_reset_enable(tp);
2659 for (i = 0; i < 100; i++) {
2660 if (!tp->phy_reset_pending(tp))
2661 return;
2662 msleep(1);
2663 }
2664 netif_err(tp, link, dev, "PHY reset failed\n");
2665 }
2666
2667 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2668 {
2669 void __iomem *ioaddr = tp->mmio_addr;
2670
2671 rtl_hw_phy_config(dev);
2672
2673 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2674 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2675 RTL_W8(0x82, 0x01);
2676 }
2677
2678 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2679
2680 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2681 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2682
2683 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2684 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2685 RTL_W8(0x82, 0x01);
2686 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2687 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2688 }
2689
2690 rtl8169_phy_reset(dev, tp);
2691
2692 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2693 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2694 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2695 (tp->mii.supports_gmii ?
2696 ADVERTISED_1000baseT_Half |
2697 ADVERTISED_1000baseT_Full : 0));
2698
2699 if (RTL_R8(PHYstatus) & TBI_Enable)
2700 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2701 }
2702
2703 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2704 {
2705 void __iomem *ioaddr = tp->mmio_addr;
2706 u32 high;
2707 u32 low;
2708
2709 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2710 high = addr[4] | (addr[5] << 8);
2711
2712 spin_lock_irq(&tp->lock);
2713
2714 RTL_W8(Cfg9346, Cfg9346_Unlock);
2715
2716 RTL_W32(MAC4, high);
2717 RTL_R32(MAC4);
2718
2719 RTL_W32(MAC0, low);
2720 RTL_R32(MAC0);
2721
2722 RTL_W8(Cfg9346, Cfg9346_Lock);
2723
2724 spin_unlock_irq(&tp->lock);
2725 }
2726
2727 static int rtl_set_mac_address(struct net_device *dev, void *p)
2728 {
2729 struct rtl8169_private *tp = netdev_priv(dev);
2730 struct sockaddr *addr = p;
2731
2732 if (!is_valid_ether_addr(addr->sa_data))
2733 return -EADDRNOTAVAIL;
2734
2735 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2736
2737 rtl_rar_set(tp, dev->dev_addr);
2738
2739 return 0;
2740 }
2741
2742 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2743 {
2744 struct rtl8169_private *tp = netdev_priv(dev);
2745 struct mii_ioctl_data *data = if_mii(ifr);
2746
2747 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2748 }
2749
2750 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2751 {
2752 switch (cmd) {
2753 case SIOCGMIIPHY:
2754 data->phy_id = 32; /* Internal PHY */
2755 return 0;
2756
2757 case SIOCGMIIREG:
2758 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2759 return 0;
2760
2761 case SIOCSMIIREG:
2762 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2763 return 0;
2764 }
2765 return -EOPNOTSUPP;
2766 }
2767
2768 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2769 {
2770 return -EOPNOTSUPP;
2771 }
2772
2773 static const struct rtl_cfg_info {
2774 void (*hw_start)(struct net_device *);
2775 unsigned int region;
2776 unsigned int align;
2777 u16 intr_event;
2778 u16 napi_event;
2779 unsigned features;
2780 u8 default_ver;
2781 } rtl_cfg_infos [] = {
2782 [RTL_CFG_0] = {
2783 .hw_start = rtl_hw_start_8169,
2784 .region = 1,
2785 .align = 0,
2786 .intr_event = SYSErr | LinkChg | RxOverflow |
2787 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2788 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2789 .features = RTL_FEATURE_GMII,
2790 .default_ver = RTL_GIGA_MAC_VER_01,
2791 },
2792 [RTL_CFG_1] = {
2793 .hw_start = rtl_hw_start_8168,
2794 .region = 2,
2795 .align = 8,
2796 .intr_event = SYSErr | LinkChg | RxOverflow |
2797 TxErr | TxOK | RxOK | RxErr,
2798 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2799 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2800 .default_ver = RTL_GIGA_MAC_VER_11,
2801 },
2802 [RTL_CFG_2] = {
2803 .hw_start = rtl_hw_start_8101,
2804 .region = 2,
2805 .align = 8,
2806 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2807 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2808 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2809 .features = RTL_FEATURE_MSI,
2810 .default_ver = RTL_GIGA_MAC_VER_13,
2811 }
2812 };
2813
2814 /* Cfg9346_Unlock assumed. */
2815 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2816 const struct rtl_cfg_info *cfg)
2817 {
2818 unsigned msi = 0;
2819 u8 cfg2;
2820
2821 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2822 if (cfg->features & RTL_FEATURE_MSI) {
2823 if (pci_enable_msi(pdev)) {
2824 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2825 } else {
2826 cfg2 |= MSIEnable;
2827 msi = RTL_FEATURE_MSI;
2828 }
2829 }
2830 RTL_W8(Config2, cfg2);
2831 return msi;
2832 }
2833
2834 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2835 {
2836 if (tp->features & RTL_FEATURE_MSI) {
2837 pci_disable_msi(pdev);
2838 tp->features &= ~RTL_FEATURE_MSI;
2839 }
2840 }
2841
2842 static const struct net_device_ops rtl8169_netdev_ops = {
2843 .ndo_open = rtl8169_open,
2844 .ndo_stop = rtl8169_close,
2845 .ndo_get_stats = rtl8169_get_stats,
2846 .ndo_start_xmit = rtl8169_start_xmit,
2847 .ndo_tx_timeout = rtl8169_tx_timeout,
2848 .ndo_validate_addr = eth_validate_addr,
2849 .ndo_change_mtu = rtl8169_change_mtu,
2850 .ndo_set_mac_address = rtl_set_mac_address,
2851 .ndo_do_ioctl = rtl8169_ioctl,
2852 .ndo_set_multicast_list = rtl_set_rx_mode,
2853 #ifdef CONFIG_NET_POLL_CONTROLLER
2854 .ndo_poll_controller = rtl8169_netpoll,
2855 #endif
2856
2857 };
2858
2859 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2860 {
2861 struct mdio_ops *ops = &tp->mdio_ops;
2862
2863 switch (tp->mac_version) {
2864 case RTL_GIGA_MAC_VER_27:
2865 ops->write = r8168dp_1_mdio_write;
2866 ops->read = r8168dp_1_mdio_read;
2867 break;
2868 case RTL_GIGA_MAC_VER_28:
2869 ops->write = r8168dp_2_mdio_write;
2870 ops->read = r8168dp_2_mdio_read;
2871 break;
2872 default:
2873 ops->write = r8169_mdio_write;
2874 ops->read = r8169_mdio_read;
2875 break;
2876 }
2877 }
2878
2879 static void r810x_phy_power_down(struct rtl8169_private *tp)
2880 {
2881 rtl_writephy(tp, 0x1f, 0x0000);
2882 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2883 }
2884
2885 static void r810x_phy_power_up(struct rtl8169_private *tp)
2886 {
2887 rtl_writephy(tp, 0x1f, 0x0000);
2888 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2889 }
2890
2891 static void r810x_pll_power_down(struct rtl8169_private *tp)
2892 {
2893 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2894 rtl_writephy(tp, 0x1f, 0x0000);
2895 rtl_writephy(tp, MII_BMCR, 0x0000);
2896 return;
2897 }
2898
2899 r810x_phy_power_down(tp);
2900 }
2901
2902 static void r810x_pll_power_up(struct rtl8169_private *tp)
2903 {
2904 r810x_phy_power_up(tp);
2905 }
2906
2907 static void r8168_phy_power_up(struct rtl8169_private *tp)
2908 {
2909 rtl_writephy(tp, 0x1f, 0x0000);
2910 rtl_writephy(tp, 0x0e, 0x0000);
2911 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2912 }
2913
2914 static void r8168_phy_power_down(struct rtl8169_private *tp)
2915 {
2916 rtl_writephy(tp, 0x1f, 0x0000);
2917 rtl_writephy(tp, 0x0e, 0x0200);
2918 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2919 }
2920
2921 static void r8168_pll_power_down(struct rtl8169_private *tp)
2922 {
2923 void __iomem *ioaddr = tp->mmio_addr;
2924
2925 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2926 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2927 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2928 return;
2929 }
2930
2931 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2932 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2933 (RTL_R16(CPlusCmd) & ASF)) {
2934 return;
2935 }
2936
2937 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2938 rtl_writephy(tp, 0x1f, 0x0000);
2939 rtl_writephy(tp, MII_BMCR, 0x0000);
2940
2941 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2942 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2943 return;
2944 }
2945
2946 r8168_phy_power_down(tp);
2947
2948 switch (tp->mac_version) {
2949 case RTL_GIGA_MAC_VER_25:
2950 case RTL_GIGA_MAC_VER_26:
2951 case RTL_GIGA_MAC_VER_27:
2952 case RTL_GIGA_MAC_VER_28:
2953 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2954 break;
2955 }
2956 }
2957
2958 static void r8168_pll_power_up(struct rtl8169_private *tp)
2959 {
2960 void __iomem *ioaddr = tp->mmio_addr;
2961
2962 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2963 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2964 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2965 return;
2966 }
2967
2968 switch (tp->mac_version) {
2969 case RTL_GIGA_MAC_VER_25:
2970 case RTL_GIGA_MAC_VER_26:
2971 case RTL_GIGA_MAC_VER_27:
2972 case RTL_GIGA_MAC_VER_28:
2973 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2974 break;
2975 }
2976
2977 r8168_phy_power_up(tp);
2978 }
2979
2980 static void rtl_pll_power_op(struct rtl8169_private *tp,
2981 void (*op)(struct rtl8169_private *))
2982 {
2983 if (op)
2984 op(tp);
2985 }
2986
2987 static void rtl_pll_power_down(struct rtl8169_private *tp)
2988 {
2989 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2990 }
2991
2992 static void rtl_pll_power_up(struct rtl8169_private *tp)
2993 {
2994 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2995 }
2996
2997 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2998 {
2999 struct pll_power_ops *ops = &tp->pll_power_ops;
3000
3001 switch (tp->mac_version) {
3002 case RTL_GIGA_MAC_VER_07:
3003 case RTL_GIGA_MAC_VER_08:
3004 case RTL_GIGA_MAC_VER_09:
3005 case RTL_GIGA_MAC_VER_10:
3006 case RTL_GIGA_MAC_VER_16:
3007 case RTL_GIGA_MAC_VER_29:
3008 case RTL_GIGA_MAC_VER_30:
3009 ops->down = r810x_pll_power_down;
3010 ops->up = r810x_pll_power_up;
3011 break;
3012
3013 case RTL_GIGA_MAC_VER_11:
3014 case RTL_GIGA_MAC_VER_12:
3015 case RTL_GIGA_MAC_VER_17:
3016 case RTL_GIGA_MAC_VER_18:
3017 case RTL_GIGA_MAC_VER_19:
3018 case RTL_GIGA_MAC_VER_20:
3019 case RTL_GIGA_MAC_VER_21:
3020 case RTL_GIGA_MAC_VER_22:
3021 case RTL_GIGA_MAC_VER_23:
3022 case RTL_GIGA_MAC_VER_24:
3023 case RTL_GIGA_MAC_VER_25:
3024 case RTL_GIGA_MAC_VER_26:
3025 case RTL_GIGA_MAC_VER_27:
3026 case RTL_GIGA_MAC_VER_28:
3027 ops->down = r8168_pll_power_down;
3028 ops->up = r8168_pll_power_up;
3029 break;
3030
3031 default:
3032 ops->down = NULL;
3033 ops->up = NULL;
3034 break;
3035 }
3036 }
3037
3038 static int __devinit
3039 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3040 {
3041 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3042 const unsigned int region = cfg->region;
3043 struct rtl8169_private *tp;
3044 struct mii_if_info *mii;
3045 struct net_device *dev;
3046 void __iomem *ioaddr;
3047 unsigned int i;
3048 int rc;
3049
3050 if (netif_msg_drv(&debug)) {
3051 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3052 MODULENAME, RTL8169_VERSION);
3053 }
3054
3055 dev = alloc_etherdev(sizeof (*tp));
3056 if (!dev) {
3057 if (netif_msg_drv(&debug))
3058 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3059 rc = -ENOMEM;
3060 goto out;
3061 }
3062
3063 SET_NETDEV_DEV(dev, &pdev->dev);
3064 dev->netdev_ops = &rtl8169_netdev_ops;
3065 tp = netdev_priv(dev);
3066 tp->dev = dev;
3067 tp->pci_dev = pdev;
3068 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3069
3070 mii = &tp->mii;
3071 mii->dev = dev;
3072 mii->mdio_read = rtl_mdio_read;
3073 mii->mdio_write = rtl_mdio_write;
3074 mii->phy_id_mask = 0x1f;
3075 mii->reg_num_mask = 0x1f;
3076 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3077
3078 /* disable ASPM completely as that cause random device stop working
3079 * problems as well as full system hangs for some PCIe devices users */
3080 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3081 PCIE_LINK_STATE_CLKPM);
3082
3083 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3084 rc = pci_enable_device(pdev);
3085 if (rc < 0) {
3086 netif_err(tp, probe, dev, "enable failure\n");
3087 goto err_out_free_dev_1;
3088 }
3089
3090 if (pci_set_mwi(pdev) < 0)
3091 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3092
3093 /* make sure PCI base addr 1 is MMIO */
3094 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3095 netif_err(tp, probe, dev,
3096 "region #%d not an MMIO resource, aborting\n",
3097 region);
3098 rc = -ENODEV;
3099 goto err_out_mwi_2;
3100 }
3101
3102 /* check for weird/broken PCI region reporting */
3103 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3104 netif_err(tp, probe, dev,
3105 "Invalid PCI region size(s), aborting\n");
3106 rc = -ENODEV;
3107 goto err_out_mwi_2;
3108 }
3109
3110 rc = pci_request_regions(pdev, MODULENAME);
3111 if (rc < 0) {
3112 netif_err(tp, probe, dev, "could not request regions\n");
3113 goto err_out_mwi_2;
3114 }
3115
3116 tp->cp_cmd = RxChkSum;
3117
3118 if ((sizeof(dma_addr_t) > 4) &&
3119 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3120 tp->cp_cmd |= PCIDAC;
3121 dev->features |= NETIF_F_HIGHDMA;
3122 } else {
3123 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3124 if (rc < 0) {
3125 netif_err(tp, probe, dev, "DMA configuration failed\n");
3126 goto err_out_free_res_3;
3127 }
3128 }
3129
3130 /* ioremap MMIO region */
3131 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3132 if (!ioaddr) {
3133 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3134 rc = -EIO;
3135 goto err_out_free_res_3;
3136 }
3137
3138 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3139 if (!tp->pcie_cap)
3140 netif_info(tp, probe, dev, "no PCI Express capability\n");
3141
3142 RTL_W16(IntrMask, 0x0000);
3143
3144 /* Soft reset the chip. */
3145 RTL_W8(ChipCmd, CmdReset);
3146
3147 /* Check that the chip has finished the reset. */
3148 for (i = 0; i < 100; i++) {
3149 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3150 break;
3151 msleep_interruptible(1);
3152 }
3153
3154 RTL_W16(IntrStatus, 0xffff);
3155
3156 pci_set_master(pdev);
3157
3158 /* Identify chip attached to board */
3159 rtl8169_get_mac_version(tp, ioaddr);
3160
3161 /*
3162 * Pretend we are using VLANs; This bypasses a nasty bug where
3163 * Interrupts stop flowing on high load on 8110SCd controllers.
3164 */
3165 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3166 tp->cp_cmd |= RxVlan;
3167
3168 rtl_init_mdio_ops(tp);
3169 rtl_init_pll_power_ops(tp);
3170
3171 /* Use appropriate default if unknown */
3172 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3173 netif_notice(tp, probe, dev,
3174 "unknown MAC, using family default\n");
3175 tp->mac_version = cfg->default_ver;
3176 }
3177
3178 rtl8169_print_mac_version(tp);
3179
3180 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3181 if (tp->mac_version == rtl_chip_info[i].mac_version)
3182 break;
3183 }
3184 if (i == ARRAY_SIZE(rtl_chip_info)) {
3185 dev_err(&pdev->dev,
3186 "driver bug, MAC version not found in rtl_chip_info\n");
3187 goto err_out_msi_4;
3188 }
3189 tp->chipset = i;
3190
3191 RTL_W8(Cfg9346, Cfg9346_Unlock);
3192 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3193 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3194 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3195 tp->features |= RTL_FEATURE_WOL;
3196 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3197 tp->features |= RTL_FEATURE_WOL;
3198 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3199 RTL_W8(Cfg9346, Cfg9346_Lock);
3200
3201 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3202 (RTL_R8(PHYstatus) & TBI_Enable)) {
3203 tp->set_speed = rtl8169_set_speed_tbi;
3204 tp->get_settings = rtl8169_gset_tbi;
3205 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3206 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3207 tp->link_ok = rtl8169_tbi_link_ok;
3208 tp->do_ioctl = rtl_tbi_ioctl;
3209
3210 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3211 } else {
3212 tp->set_speed = rtl8169_set_speed_xmii;
3213 tp->get_settings = rtl8169_gset_xmii;
3214 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3215 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3216 tp->link_ok = rtl8169_xmii_link_ok;
3217 tp->do_ioctl = rtl_xmii_ioctl;
3218 }
3219
3220 spin_lock_init(&tp->lock);
3221
3222 tp->mmio_addr = ioaddr;
3223
3224 /* Get MAC address */
3225 for (i = 0; i < MAC_ADDR_LEN; i++)
3226 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3227 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3228
3229 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3230 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3231 dev->irq = pdev->irq;
3232 dev->base_addr = (unsigned long) ioaddr;
3233
3234 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3235
3236 dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO;
3237
3238 tp->intr_mask = 0xffff;
3239 tp->hw_start = cfg->hw_start;
3240 tp->intr_event = cfg->intr_event;
3241 tp->napi_event = cfg->napi_event;
3242
3243 init_timer(&tp->timer);
3244 tp->timer.data = (unsigned long) dev;
3245 tp->timer.function = rtl8169_phy_timer;
3246
3247 tp->fw = RTL_FIRMWARE_UNKNOWN;
3248
3249 rc = register_netdev(dev);
3250 if (rc < 0)
3251 goto err_out_msi_4;
3252
3253 pci_set_drvdata(pdev, dev);
3254
3255 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3256 rtl_chip_info[tp->chipset].name,
3257 dev->base_addr, dev->dev_addr,
3258 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3259
3260 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3261 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3262 rtl8168_driver_start(tp);
3263 }
3264
3265 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3266
3267 if (pci_dev_run_wake(pdev))
3268 pm_runtime_put_noidle(&pdev->dev);
3269
3270 netif_carrier_off(dev);
3271
3272 out:
3273 return rc;
3274
3275 err_out_msi_4:
3276 rtl_disable_msi(pdev, tp);
3277 iounmap(ioaddr);
3278 err_out_free_res_3:
3279 pci_release_regions(pdev);
3280 err_out_mwi_2:
3281 pci_clear_mwi(pdev);
3282 pci_disable_device(pdev);
3283 err_out_free_dev_1:
3284 free_netdev(dev);
3285 goto out;
3286 }
3287
3288 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3289 {
3290 struct net_device *dev = pci_get_drvdata(pdev);
3291 struct rtl8169_private *tp = netdev_priv(dev);
3292
3293 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3294 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3295 rtl8168_driver_stop(tp);
3296 }
3297
3298 cancel_delayed_work_sync(&tp->task);
3299
3300 unregister_netdev(dev);
3301
3302 rtl_release_firmware(tp);
3303
3304 if (pci_dev_run_wake(pdev))
3305 pm_runtime_get_noresume(&pdev->dev);
3306
3307 /* restore original MAC address */
3308 rtl_rar_set(tp, dev->perm_addr);
3309
3310 rtl_disable_msi(pdev, tp);
3311 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3312 pci_set_drvdata(pdev, NULL);
3313 }
3314
3315 static void rtl_request_firmware(struct rtl8169_private *tp)
3316 {
3317 int i;
3318
3319 /* Return early if the firmware is already loaded / cached. */
3320 if (!IS_ERR(tp->fw))
3321 goto out;
3322
3323 for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3324 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3325
3326 if (info->mac_version == tp->mac_version) {
3327 const char *name = info->fw_name;
3328 int rc;
3329
3330 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3331 if (rc < 0) {
3332 netif_warn(tp, ifup, tp->dev, "unable to load "
3333 "firmware patch %s (%d)\n", name, rc);
3334 goto out_disable_request_firmware;
3335 }
3336 goto out;
3337 }
3338 }
3339
3340 out_disable_request_firmware:
3341 tp->fw = NULL;
3342 out:
3343 return;
3344 }
3345
3346 static int rtl8169_open(struct net_device *dev)
3347 {
3348 struct rtl8169_private *tp = netdev_priv(dev);
3349 void __iomem *ioaddr = tp->mmio_addr;
3350 struct pci_dev *pdev = tp->pci_dev;
3351 int retval = -ENOMEM;
3352
3353 pm_runtime_get_sync(&pdev->dev);
3354
3355 /*
3356 * Rx and Tx desscriptors needs 256 bytes alignment.
3357 * dma_alloc_coherent provides more.
3358 */
3359 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3360 &tp->TxPhyAddr, GFP_KERNEL);
3361 if (!tp->TxDescArray)
3362 goto err_pm_runtime_put;
3363
3364 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3365 &tp->RxPhyAddr, GFP_KERNEL);
3366 if (!tp->RxDescArray)
3367 goto err_free_tx_0;
3368
3369 retval = rtl8169_init_ring(dev);
3370 if (retval < 0)
3371 goto err_free_rx_1;
3372
3373 INIT_DELAYED_WORK(&tp->task, NULL);
3374
3375 smp_mb();
3376
3377 rtl_request_firmware(tp);
3378
3379 retval = request_irq(dev->irq, rtl8169_interrupt,
3380 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3381 dev->name, dev);
3382 if (retval < 0)
3383 goto err_release_fw_2;
3384
3385 napi_enable(&tp->napi);
3386
3387 rtl8169_init_phy(dev, tp);
3388
3389 rtl8169_vlan_mode(dev);
3390
3391 rtl_pll_power_up(tp);
3392
3393 rtl_hw_start(dev);
3394
3395 rtl8169_request_timer(dev);
3396
3397 tp->saved_wolopts = 0;
3398 pm_runtime_put_noidle(&pdev->dev);
3399
3400 rtl8169_check_link_status(dev, tp, ioaddr);
3401 out:
3402 return retval;
3403
3404 err_release_fw_2:
3405 rtl_release_firmware(tp);
3406 rtl8169_rx_clear(tp);
3407 err_free_rx_1:
3408 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3409 tp->RxPhyAddr);
3410 tp->RxDescArray = NULL;
3411 err_free_tx_0:
3412 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3413 tp->TxPhyAddr);
3414 tp->TxDescArray = NULL;
3415 err_pm_runtime_put:
3416 pm_runtime_put_noidle(&pdev->dev);
3417 goto out;
3418 }
3419
3420 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3421 {
3422 void __iomem *ioaddr = tp->mmio_addr;
3423
3424 /* Disable interrupts */
3425 rtl8169_irq_mask_and_ack(ioaddr);
3426
3427 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3428 tp->mac_version == RTL_GIGA_MAC_VER_28) {
3429 while (RTL_R8(TxPoll) & NPQ)
3430 udelay(20);
3431
3432 }
3433
3434 /* Reset the chipset */
3435 RTL_W8(ChipCmd, CmdReset);
3436
3437 /* PCI commit */
3438 RTL_R8(ChipCmd);
3439 }
3440
3441 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3442 {
3443 void __iomem *ioaddr = tp->mmio_addr;
3444 u32 cfg = rtl8169_rx_config;
3445
3446 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3447 RTL_W32(RxConfig, cfg);
3448
3449 /* Set DMA burst size and Interframe Gap Time */
3450 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3451 (InterFrameGap << TxInterFrameGapShift));
3452 }
3453
3454 static void rtl_hw_start(struct net_device *dev)
3455 {
3456 struct rtl8169_private *tp = netdev_priv(dev);
3457 void __iomem *ioaddr = tp->mmio_addr;
3458 unsigned int i;
3459
3460 /* Soft reset the chip. */
3461 RTL_W8(ChipCmd, CmdReset);
3462
3463 /* Check that the chip has finished the reset. */
3464 for (i = 0; i < 100; i++) {
3465 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3466 break;
3467 msleep_interruptible(1);
3468 }
3469
3470 tp->hw_start(dev);
3471
3472 netif_start_queue(dev);
3473 }
3474
3475
3476 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3477 void __iomem *ioaddr)
3478 {
3479 /*
3480 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3481 * register to be written before TxDescAddrLow to work.
3482 * Switching from MMIO to I/O access fixes the issue as well.
3483 */
3484 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3485 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3486 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3487 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3488 }
3489
3490 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3491 {
3492 u16 cmd;
3493
3494 cmd = RTL_R16(CPlusCmd);
3495 RTL_W16(CPlusCmd, cmd);
3496 return cmd;
3497 }
3498
3499 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3500 {
3501 /* Low hurts. Let's disable the filtering. */
3502 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3503 }
3504
3505 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3506 {
3507 static const struct {
3508 u32 mac_version;
3509 u32 clk;
3510 u32 val;
3511 } cfg2_info [] = {
3512 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3513 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3514 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3515 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3516 }, *p = cfg2_info;
3517 unsigned int i;
3518 u32 clk;
3519
3520 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3521 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3522 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3523 RTL_W32(0x7c, p->val);
3524 break;
3525 }
3526 }
3527 }
3528
3529 static void rtl_hw_start_8169(struct net_device *dev)
3530 {
3531 struct rtl8169_private *tp = netdev_priv(dev);
3532 void __iomem *ioaddr = tp->mmio_addr;
3533 struct pci_dev *pdev = tp->pci_dev;
3534
3535 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3536 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3537 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3538 }
3539
3540 RTL_W8(Cfg9346, Cfg9346_Unlock);
3541 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3542 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3543 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3544 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3545 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3546
3547 RTL_W8(EarlyTxThres, NoEarlyTx);
3548
3549 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3550
3551 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3552 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3553 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3554 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3555 rtl_set_rx_tx_config_registers(tp);
3556
3557 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3558
3559 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3560 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3561 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3562 "Bit-3 and bit-14 MUST be 1\n");
3563 tp->cp_cmd |= (1 << 14);
3564 }
3565
3566 RTL_W16(CPlusCmd, tp->cp_cmd);
3567
3568 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3569
3570 /*
3571 * Undocumented corner. Supposedly:
3572 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3573 */
3574 RTL_W16(IntrMitigate, 0x0000);
3575
3576 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3577
3578 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3579 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3580 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3581 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3582 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3583 rtl_set_rx_tx_config_registers(tp);
3584 }
3585
3586 RTL_W8(Cfg9346, Cfg9346_Lock);
3587
3588 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3589 RTL_R8(IntrMask);
3590
3591 RTL_W32(RxMissed, 0);
3592
3593 rtl_set_rx_mode(dev);
3594
3595 /* no early-rx interrupts */
3596 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3597
3598 /* Enable all known interrupts by setting the interrupt mask. */
3599 RTL_W16(IntrMask, tp->intr_event);
3600 }
3601
3602 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3603 {
3604 struct net_device *dev = pci_get_drvdata(pdev);
3605 struct rtl8169_private *tp = netdev_priv(dev);
3606 int cap = tp->pcie_cap;
3607
3608 if (cap) {
3609 u16 ctl;
3610
3611 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3612 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3613 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3614 }
3615 }
3616
3617 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3618 {
3619 u32 csi;
3620
3621 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3622 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3623 }
3624
3625 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3626 {
3627 rtl_csi_access_enable(ioaddr, 0x17000000);
3628 }
3629
3630 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3631 {
3632 rtl_csi_access_enable(ioaddr, 0x27000000);
3633 }
3634
3635 struct ephy_info {
3636 unsigned int offset;
3637 u16 mask;
3638 u16 bits;
3639 };
3640
3641 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3642 {
3643 u16 w;
3644
3645 while (len-- > 0) {
3646 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3647 rtl_ephy_write(ioaddr, e->offset, w);
3648 e++;
3649 }
3650 }
3651
3652 static void rtl_disable_clock_request(struct pci_dev *pdev)
3653 {
3654 struct net_device *dev = pci_get_drvdata(pdev);
3655 struct rtl8169_private *tp = netdev_priv(dev);
3656 int cap = tp->pcie_cap;
3657
3658 if (cap) {
3659 u16 ctl;
3660
3661 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3662 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3663 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3664 }
3665 }
3666
3667 static void rtl_enable_clock_request(struct pci_dev *pdev)
3668 {
3669 struct net_device *dev = pci_get_drvdata(pdev);
3670 struct rtl8169_private *tp = netdev_priv(dev);
3671 int cap = tp->pcie_cap;
3672
3673 if (cap) {
3674 u16 ctl;
3675
3676 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3677 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3678 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3679 }
3680 }
3681
3682 #define R8168_CPCMD_QUIRK_MASK (\
3683 EnableBist | \
3684 Mac_dbgo_oe | \
3685 Force_half_dup | \
3686 Force_rxflow_en | \
3687 Force_txflow_en | \
3688 Cxpl_dbg_sel | \
3689 ASF | \
3690 PktCntrDisable | \
3691 Mac_dbgo_sel)
3692
3693 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3694 {
3695 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3696
3697 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3698
3699 rtl_tx_performance_tweak(pdev,
3700 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3701 }
3702
3703 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3704 {
3705 rtl_hw_start_8168bb(ioaddr, pdev);
3706
3707 RTL_W8(MaxTxPacketSize, TxPacketMax);
3708
3709 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3710 }
3711
3712 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3713 {
3714 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3715
3716 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3717
3718 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3719
3720 rtl_disable_clock_request(pdev);
3721
3722 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3723 }
3724
3725 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3726 {
3727 static const struct ephy_info e_info_8168cp[] = {
3728 { 0x01, 0, 0x0001 },
3729 { 0x02, 0x0800, 0x1000 },
3730 { 0x03, 0, 0x0042 },
3731 { 0x06, 0x0080, 0x0000 },
3732 { 0x07, 0, 0x2000 }
3733 };
3734
3735 rtl_csi_access_enable_2(ioaddr);
3736
3737 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3738
3739 __rtl_hw_start_8168cp(ioaddr, pdev);
3740 }
3741
3742 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3743 {
3744 rtl_csi_access_enable_2(ioaddr);
3745
3746 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3747
3748 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3749
3750 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3751 }
3752
3753 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3754 {
3755 rtl_csi_access_enable_2(ioaddr);
3756
3757 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3758
3759 /* Magic. */
3760 RTL_W8(DBG_REG, 0x20);
3761
3762 RTL_W8(MaxTxPacketSize, TxPacketMax);
3763
3764 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3765
3766 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3767 }
3768
3769 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3770 {
3771 static const struct ephy_info e_info_8168c_1[] = {
3772 { 0x02, 0x0800, 0x1000 },
3773 { 0x03, 0, 0x0002 },
3774 { 0x06, 0x0080, 0x0000 }
3775 };
3776
3777 rtl_csi_access_enable_2(ioaddr);
3778
3779 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3780
3781 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3782
3783 __rtl_hw_start_8168cp(ioaddr, pdev);
3784 }
3785
3786 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3787 {
3788 static const struct ephy_info e_info_8168c_2[] = {
3789 { 0x01, 0, 0x0001 },
3790 { 0x03, 0x0400, 0x0220 }
3791 };
3792
3793 rtl_csi_access_enable_2(ioaddr);
3794
3795 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3796
3797 __rtl_hw_start_8168cp(ioaddr, pdev);
3798 }
3799
3800 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3801 {
3802 rtl_hw_start_8168c_2(ioaddr, pdev);
3803 }
3804
3805 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3806 {
3807 rtl_csi_access_enable_2(ioaddr);
3808
3809 __rtl_hw_start_8168cp(ioaddr, pdev);
3810 }
3811
3812 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3813 {
3814 rtl_csi_access_enable_2(ioaddr);
3815
3816 rtl_disable_clock_request(pdev);
3817
3818 RTL_W8(MaxTxPacketSize, TxPacketMax);
3819
3820 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3821
3822 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3823 }
3824
3825 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3826 {
3827 static const struct ephy_info e_info_8168d_4[] = {
3828 { 0x0b, ~0, 0x48 },
3829 { 0x19, 0x20, 0x50 },
3830 { 0x0c, ~0, 0x20 }
3831 };
3832 int i;
3833
3834 rtl_csi_access_enable_1(ioaddr);
3835
3836 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3837
3838 RTL_W8(MaxTxPacketSize, TxPacketMax);
3839
3840 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3841 const struct ephy_info *e = e_info_8168d_4 + i;
3842 u16 w;
3843
3844 w = rtl_ephy_read(ioaddr, e->offset);
3845 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3846 }
3847
3848 rtl_enable_clock_request(pdev);
3849 }
3850
3851 static void rtl_hw_start_8168(struct net_device *dev)
3852 {
3853 struct rtl8169_private *tp = netdev_priv(dev);
3854 void __iomem *ioaddr = tp->mmio_addr;
3855 struct pci_dev *pdev = tp->pci_dev;
3856
3857 RTL_W8(Cfg9346, Cfg9346_Unlock);
3858
3859 RTL_W8(MaxTxPacketSize, TxPacketMax);
3860
3861 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3862
3863 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3864
3865 RTL_W16(CPlusCmd, tp->cp_cmd);
3866
3867 RTL_W16(IntrMitigate, 0x5151);
3868
3869 /* Work around for RxFIFO overflow. */
3870 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3871 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3872 tp->intr_event |= RxFIFOOver | PCSTimeout;
3873 tp->intr_event &= ~RxOverflow;
3874 }
3875
3876 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3877
3878 rtl_set_rx_mode(dev);
3879
3880 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3881 (InterFrameGap << TxInterFrameGapShift));
3882
3883 RTL_R8(IntrMask);
3884
3885 switch (tp->mac_version) {
3886 case RTL_GIGA_MAC_VER_11:
3887 rtl_hw_start_8168bb(ioaddr, pdev);
3888 break;
3889
3890 case RTL_GIGA_MAC_VER_12:
3891 case RTL_GIGA_MAC_VER_17:
3892 rtl_hw_start_8168bef(ioaddr, pdev);
3893 break;
3894
3895 case RTL_GIGA_MAC_VER_18:
3896 rtl_hw_start_8168cp_1(ioaddr, pdev);
3897 break;
3898
3899 case RTL_GIGA_MAC_VER_19:
3900 rtl_hw_start_8168c_1(ioaddr, pdev);
3901 break;
3902
3903 case RTL_GIGA_MAC_VER_20:
3904 rtl_hw_start_8168c_2(ioaddr, pdev);
3905 break;
3906
3907 case RTL_GIGA_MAC_VER_21:
3908 rtl_hw_start_8168c_3(ioaddr, pdev);
3909 break;
3910
3911 case RTL_GIGA_MAC_VER_22:
3912 rtl_hw_start_8168c_4(ioaddr, pdev);
3913 break;
3914
3915 case RTL_GIGA_MAC_VER_23:
3916 rtl_hw_start_8168cp_2(ioaddr, pdev);
3917 break;
3918
3919 case RTL_GIGA_MAC_VER_24:
3920 rtl_hw_start_8168cp_3(ioaddr, pdev);
3921 break;
3922
3923 case RTL_GIGA_MAC_VER_25:
3924 case RTL_GIGA_MAC_VER_26:
3925 case RTL_GIGA_MAC_VER_27:
3926 rtl_hw_start_8168d(ioaddr, pdev);
3927 break;
3928
3929 case RTL_GIGA_MAC_VER_28:
3930 rtl_hw_start_8168d_4(ioaddr, pdev);
3931 break;
3932
3933 default:
3934 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3935 dev->name, tp->mac_version);
3936 break;
3937 }
3938
3939 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3940
3941 RTL_W8(Cfg9346, Cfg9346_Lock);
3942
3943 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3944
3945 RTL_W16(IntrMask, tp->intr_event);
3946 }
3947
3948 #define R810X_CPCMD_QUIRK_MASK (\
3949 EnableBist | \
3950 Mac_dbgo_oe | \
3951 Force_half_dup | \
3952 Force_rxflow_en | \
3953 Force_txflow_en | \
3954 Cxpl_dbg_sel | \
3955 ASF | \
3956 PktCntrDisable | \
3957 Mac_dbgo_sel)
3958
3959 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3960 {
3961 static const struct ephy_info e_info_8102e_1[] = {
3962 { 0x01, 0, 0x6e65 },
3963 { 0x02, 0, 0x091f },
3964 { 0x03, 0, 0xc2f9 },
3965 { 0x06, 0, 0xafb5 },
3966 { 0x07, 0, 0x0e00 },
3967 { 0x19, 0, 0xec80 },
3968 { 0x01, 0, 0x2e65 },
3969 { 0x01, 0, 0x6e65 }
3970 };
3971 u8 cfg1;
3972
3973 rtl_csi_access_enable_2(ioaddr);
3974
3975 RTL_W8(DBG_REG, FIX_NAK_1);
3976
3977 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3978
3979 RTL_W8(Config1,
3980 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3981 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3982
3983 cfg1 = RTL_R8(Config1);
3984 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3985 RTL_W8(Config1, cfg1 & ~LEDS0);
3986
3987 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3988 }
3989
3990 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3991 {
3992 rtl_csi_access_enable_2(ioaddr);
3993
3994 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3995
3996 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3997 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3998 }
3999
4000 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4001 {
4002 rtl_hw_start_8102e_2(ioaddr, pdev);
4003
4004 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4005 }
4006
4007 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4008 {
4009 static const struct ephy_info e_info_8105e_1[] = {
4010 { 0x07, 0, 0x4000 },
4011 { 0x19, 0, 0x0200 },
4012 { 0x19, 0, 0x0020 },
4013 { 0x1e, 0, 0x2000 },
4014 { 0x03, 0, 0x0001 },
4015 { 0x19, 0, 0x0100 },
4016 { 0x19, 0, 0x0004 },
4017 { 0x0a, 0, 0x0020 }
4018 };
4019
4020 /* Force LAN exit from ASPM if Rx/Tx are not idel */
4021 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4022
4023 /* disable Early Tally Counter */
4024 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4025
4026 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4027 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4028
4029 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4030 }
4031
4032 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4033 {
4034 rtl_hw_start_8105e_1(ioaddr, pdev);
4035 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4036 }
4037
4038 static void rtl_hw_start_8101(struct net_device *dev)
4039 {
4040 struct rtl8169_private *tp = netdev_priv(dev);
4041 void __iomem *ioaddr = tp->mmio_addr;
4042 struct pci_dev *pdev = tp->pci_dev;
4043
4044 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4045 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
4046 int cap = tp->pcie_cap;
4047
4048 if (cap) {
4049 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4050 PCI_EXP_DEVCTL_NOSNOOP_EN);
4051 }
4052 }
4053
4054 RTL_W8(Cfg9346, Cfg9346_Unlock);
4055
4056 switch (tp->mac_version) {
4057 case RTL_GIGA_MAC_VER_07:
4058 rtl_hw_start_8102e_1(ioaddr, pdev);
4059 break;
4060
4061 case RTL_GIGA_MAC_VER_08:
4062 rtl_hw_start_8102e_3(ioaddr, pdev);
4063 break;
4064
4065 case RTL_GIGA_MAC_VER_09:
4066 rtl_hw_start_8102e_2(ioaddr, pdev);
4067 break;
4068
4069 case RTL_GIGA_MAC_VER_29:
4070 rtl_hw_start_8105e_1(ioaddr, pdev);
4071 break;
4072 case RTL_GIGA_MAC_VER_30:
4073 rtl_hw_start_8105e_2(ioaddr, pdev);
4074 break;
4075 }
4076
4077 RTL_W8(Cfg9346, Cfg9346_Lock);
4078
4079 RTL_W8(MaxTxPacketSize, TxPacketMax);
4080
4081 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4082
4083 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4084 RTL_W16(CPlusCmd, tp->cp_cmd);
4085
4086 RTL_W16(IntrMitigate, 0x0000);
4087
4088 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4089
4090 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4091 rtl_set_rx_tx_config_registers(tp);
4092
4093 RTL_R8(IntrMask);
4094
4095 rtl_set_rx_mode(dev);
4096
4097 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4098
4099 RTL_W16(IntrMask, tp->intr_event);
4100 }
4101
4102 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4103 {
4104 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4105 return -EINVAL;
4106
4107 dev->mtu = new_mtu;
4108 return 0;
4109 }
4110
4111 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4112 {
4113 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4114 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4115 }
4116
4117 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4118 void **data_buff, struct RxDesc *desc)
4119 {
4120 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4121 DMA_FROM_DEVICE);
4122
4123 kfree(*data_buff);
4124 *data_buff = NULL;
4125 rtl8169_make_unusable_by_asic(desc);
4126 }
4127
4128 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4129 {
4130 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4131
4132 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4133 }
4134
4135 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4136 u32 rx_buf_sz)
4137 {
4138 desc->addr = cpu_to_le64(mapping);
4139 wmb();
4140 rtl8169_mark_to_asic(desc, rx_buf_sz);
4141 }
4142
4143 static inline void *rtl8169_align(void *data)
4144 {
4145 return (void *)ALIGN((long)data, 16);
4146 }
4147
4148 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4149 struct RxDesc *desc)
4150 {
4151 void *data;
4152 dma_addr_t mapping;
4153 struct device *d = &tp->pci_dev->dev;
4154 struct net_device *dev = tp->dev;
4155 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4156
4157 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4158 if (!data)
4159 return NULL;
4160
4161 if (rtl8169_align(data) != data) {
4162 kfree(data);
4163 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4164 if (!data)
4165 return NULL;
4166 }
4167
4168 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4169 DMA_FROM_DEVICE);
4170 if (unlikely(dma_mapping_error(d, mapping))) {
4171 if (net_ratelimit())
4172 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4173 goto err_out;
4174 }
4175
4176 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4177 return data;
4178
4179 err_out:
4180 kfree(data);
4181 return NULL;
4182 }
4183
4184 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4185 {
4186 unsigned int i;
4187
4188 for (i = 0; i < NUM_RX_DESC; i++) {
4189 if (tp->Rx_databuff[i]) {
4190 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4191 tp->RxDescArray + i);
4192 }
4193 }
4194 }
4195
4196 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4197 {
4198 desc->opts1 |= cpu_to_le32(RingEnd);
4199 }
4200
4201 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4202 {
4203 unsigned int i;
4204
4205 for (i = 0; i < NUM_RX_DESC; i++) {
4206 void *data;
4207
4208 if (tp->Rx_databuff[i])
4209 continue;
4210
4211 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4212 if (!data) {
4213 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4214 goto err_out;
4215 }
4216 tp->Rx_databuff[i] = data;
4217 }
4218
4219 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4220 return 0;
4221
4222 err_out:
4223 rtl8169_rx_clear(tp);
4224 return -ENOMEM;
4225 }
4226
4227 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4228 {
4229 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4230 }
4231
4232 static int rtl8169_init_ring(struct net_device *dev)
4233 {
4234 struct rtl8169_private *tp = netdev_priv(dev);
4235
4236 rtl8169_init_ring_indexes(tp);
4237
4238 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4239 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4240
4241 return rtl8169_rx_fill(tp);
4242 }
4243
4244 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4245 struct TxDesc *desc)
4246 {
4247 unsigned int len = tx_skb->len;
4248
4249 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4250
4251 desc->opts1 = 0x00;
4252 desc->opts2 = 0x00;
4253 desc->addr = 0x00;
4254 tx_skb->len = 0;
4255 }
4256
4257 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4258 unsigned int n)
4259 {
4260 unsigned int i;
4261
4262 for (i = 0; i < n; i++) {
4263 unsigned int entry = (start + i) % NUM_TX_DESC;
4264 struct ring_info *tx_skb = tp->tx_skb + entry;
4265 unsigned int len = tx_skb->len;
4266
4267 if (len) {
4268 struct sk_buff *skb = tx_skb->skb;
4269
4270 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4271 tp->TxDescArray + entry);
4272 if (skb) {
4273 tp->dev->stats.tx_dropped++;
4274 dev_kfree_skb(skb);
4275 tx_skb->skb = NULL;
4276 }
4277 }
4278 }
4279 }
4280
4281 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4282 {
4283 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4284 tp->cur_tx = tp->dirty_tx = 0;
4285 }
4286
4287 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4288 {
4289 struct rtl8169_private *tp = netdev_priv(dev);
4290
4291 PREPARE_DELAYED_WORK(&tp->task, task);
4292 schedule_delayed_work(&tp->task, 4);
4293 }
4294
4295 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4296 {
4297 struct rtl8169_private *tp = netdev_priv(dev);
4298 void __iomem *ioaddr = tp->mmio_addr;
4299
4300 synchronize_irq(dev->irq);
4301
4302 /* Wait for any pending NAPI task to complete */
4303 napi_disable(&tp->napi);
4304
4305 rtl8169_irq_mask_and_ack(ioaddr);
4306
4307 tp->intr_mask = 0xffff;
4308 RTL_W16(IntrMask, tp->intr_event);
4309 napi_enable(&tp->napi);
4310 }
4311
4312 static void rtl8169_reinit_task(struct work_struct *work)
4313 {
4314 struct rtl8169_private *tp =
4315 container_of(work, struct rtl8169_private, task.work);
4316 struct net_device *dev = tp->dev;
4317 int ret;
4318
4319 rtnl_lock();
4320
4321 if (!netif_running(dev))
4322 goto out_unlock;
4323
4324 rtl8169_wait_for_quiescence(dev);
4325 rtl8169_close(dev);
4326
4327 ret = rtl8169_open(dev);
4328 if (unlikely(ret < 0)) {
4329 if (net_ratelimit())
4330 netif_err(tp, drv, dev,
4331 "reinit failure (status = %d). Rescheduling\n",
4332 ret);
4333 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4334 }
4335
4336 out_unlock:
4337 rtnl_unlock();
4338 }
4339
4340 static void rtl8169_reset_task(struct work_struct *work)
4341 {
4342 struct rtl8169_private *tp =
4343 container_of(work, struct rtl8169_private, task.work);
4344 struct net_device *dev = tp->dev;
4345
4346 rtnl_lock();
4347
4348 if (!netif_running(dev))
4349 goto out_unlock;
4350
4351 rtl8169_wait_for_quiescence(dev);
4352
4353 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4354 rtl8169_tx_clear(tp);
4355
4356 if (tp->dirty_rx == tp->cur_rx) {
4357 rtl8169_init_ring_indexes(tp);
4358 rtl_hw_start(dev);
4359 netif_wake_queue(dev);
4360 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4361 } else {
4362 if (net_ratelimit())
4363 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4364 rtl8169_schedule_work(dev, rtl8169_reset_task);
4365 }
4366
4367 out_unlock:
4368 rtnl_unlock();
4369 }
4370
4371 static void rtl8169_tx_timeout(struct net_device *dev)
4372 {
4373 struct rtl8169_private *tp = netdev_priv(dev);
4374
4375 rtl8169_hw_reset(tp);
4376
4377 /* Let's wait a bit while any (async) irq lands on */
4378 rtl8169_schedule_work(dev, rtl8169_reset_task);
4379 }
4380
4381 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4382 u32 opts1)
4383 {
4384 struct skb_shared_info *info = skb_shinfo(skb);
4385 unsigned int cur_frag, entry;
4386 struct TxDesc * uninitialized_var(txd);
4387 struct device *d = &tp->pci_dev->dev;
4388
4389 entry = tp->cur_tx;
4390 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4391 skb_frag_t *frag = info->frags + cur_frag;
4392 dma_addr_t mapping;
4393 u32 status, len;
4394 void *addr;
4395
4396 entry = (entry + 1) % NUM_TX_DESC;
4397
4398 txd = tp->TxDescArray + entry;
4399 len = frag->size;
4400 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4401 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4402 if (unlikely(dma_mapping_error(d, mapping))) {
4403 if (net_ratelimit())
4404 netif_err(tp, drv, tp->dev,
4405 "Failed to map TX fragments DMA!\n");
4406 goto err_out;
4407 }
4408
4409 /* anti gcc 2.95.3 bugware (sic) */
4410 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4411
4412 txd->opts1 = cpu_to_le32(status);
4413 txd->addr = cpu_to_le64(mapping);
4414
4415 tp->tx_skb[entry].len = len;
4416 }
4417
4418 if (cur_frag) {
4419 tp->tx_skb[entry].skb = skb;
4420 txd->opts1 |= cpu_to_le32(LastFrag);
4421 }
4422
4423 return cur_frag;
4424
4425 err_out:
4426 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4427 return -EIO;
4428 }
4429
4430 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4431 {
4432 if (dev->features & NETIF_F_TSO) {
4433 u32 mss = skb_shinfo(skb)->gso_size;
4434
4435 if (mss)
4436 return LargeSend | ((mss & MSSMask) << MSSShift);
4437 }
4438 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4439 const struct iphdr *ip = ip_hdr(skb);
4440
4441 if (ip->protocol == IPPROTO_TCP)
4442 return IPCS | TCPCS;
4443 else if (ip->protocol == IPPROTO_UDP)
4444 return IPCS | UDPCS;
4445 WARN_ON(1); /* we need a WARN() */
4446 }
4447 return 0;
4448 }
4449
4450 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4451 struct net_device *dev)
4452 {
4453 struct rtl8169_private *tp = netdev_priv(dev);
4454 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4455 struct TxDesc *txd = tp->TxDescArray + entry;
4456 void __iomem *ioaddr = tp->mmio_addr;
4457 struct device *d = &tp->pci_dev->dev;
4458 dma_addr_t mapping;
4459 u32 status, len;
4460 u32 opts1;
4461 int frags;
4462
4463 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4464 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4465 goto err_stop_0;
4466 }
4467
4468 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4469 goto err_stop_0;
4470
4471 len = skb_headlen(skb);
4472 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4473 if (unlikely(dma_mapping_error(d, mapping))) {
4474 if (net_ratelimit())
4475 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4476 goto err_dma_0;
4477 }
4478
4479 tp->tx_skb[entry].len = len;
4480 txd->addr = cpu_to_le64(mapping);
4481 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4482
4483 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4484
4485 frags = rtl8169_xmit_frags(tp, skb, opts1);
4486 if (frags < 0)
4487 goto err_dma_1;
4488 else if (frags)
4489 opts1 |= FirstFrag;
4490 else {
4491 opts1 |= FirstFrag | LastFrag;
4492 tp->tx_skb[entry].skb = skb;
4493 }
4494
4495 wmb();
4496
4497 /* anti gcc 2.95.3 bugware (sic) */
4498 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4499 txd->opts1 = cpu_to_le32(status);
4500
4501 tp->cur_tx += frags + 1;
4502
4503 wmb();
4504
4505 RTL_W8(TxPoll, NPQ); /* set polling bit */
4506
4507 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4508 netif_stop_queue(dev);
4509 smp_rmb();
4510 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4511 netif_wake_queue(dev);
4512 }
4513
4514 return NETDEV_TX_OK;
4515
4516 err_dma_1:
4517 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4518 err_dma_0:
4519 dev_kfree_skb(skb);
4520 dev->stats.tx_dropped++;
4521 return NETDEV_TX_OK;
4522
4523 err_stop_0:
4524 netif_stop_queue(dev);
4525 dev->stats.tx_dropped++;
4526 return NETDEV_TX_BUSY;
4527 }
4528
4529 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4530 {
4531 struct rtl8169_private *tp = netdev_priv(dev);
4532 struct pci_dev *pdev = tp->pci_dev;
4533 u16 pci_status, pci_cmd;
4534
4535 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4536 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4537
4538 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4539 pci_cmd, pci_status);
4540
4541 /*
4542 * The recovery sequence below admits a very elaborated explanation:
4543 * - it seems to work;
4544 * - I did not see what else could be done;
4545 * - it makes iop3xx happy.
4546 *
4547 * Feel free to adjust to your needs.
4548 */
4549 if (pdev->broken_parity_status)
4550 pci_cmd &= ~PCI_COMMAND_PARITY;
4551 else
4552 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4553
4554 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4555
4556 pci_write_config_word(pdev, PCI_STATUS,
4557 pci_status & (PCI_STATUS_DETECTED_PARITY |
4558 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4559 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4560
4561 /* The infamous DAC f*ckup only happens at boot time */
4562 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4563 void __iomem *ioaddr = tp->mmio_addr;
4564
4565 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4566 tp->cp_cmd &= ~PCIDAC;
4567 RTL_W16(CPlusCmd, tp->cp_cmd);
4568 dev->features &= ~NETIF_F_HIGHDMA;
4569 }
4570
4571 rtl8169_hw_reset(tp);
4572
4573 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4574 }
4575
4576 static void rtl8169_tx_interrupt(struct net_device *dev,
4577 struct rtl8169_private *tp,
4578 void __iomem *ioaddr)
4579 {
4580 unsigned int dirty_tx, tx_left;
4581
4582 dirty_tx = tp->dirty_tx;
4583 smp_rmb();
4584 tx_left = tp->cur_tx - dirty_tx;
4585
4586 while (tx_left > 0) {
4587 unsigned int entry = dirty_tx % NUM_TX_DESC;
4588 struct ring_info *tx_skb = tp->tx_skb + entry;
4589 u32 status;
4590
4591 rmb();
4592 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4593 if (status & DescOwn)
4594 break;
4595
4596 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4597 tp->TxDescArray + entry);
4598 if (status & LastFrag) {
4599 dev->stats.tx_packets++;
4600 dev->stats.tx_bytes += tx_skb->skb->len;
4601 dev_kfree_skb(tx_skb->skb);
4602 tx_skb->skb = NULL;
4603 }
4604 dirty_tx++;
4605 tx_left--;
4606 }
4607
4608 if (tp->dirty_tx != dirty_tx) {
4609 tp->dirty_tx = dirty_tx;
4610 smp_wmb();
4611 if (netif_queue_stopped(dev) &&
4612 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4613 netif_wake_queue(dev);
4614 }
4615 /*
4616 * 8168 hack: TxPoll requests are lost when the Tx packets are
4617 * too close. Let's kick an extra TxPoll request when a burst
4618 * of start_xmit activity is detected (if it is not detected,
4619 * it is slow enough). -- FR
4620 */
4621 smp_rmb();
4622 if (tp->cur_tx != dirty_tx)
4623 RTL_W8(TxPoll, NPQ);
4624 }
4625 }
4626
4627 static inline int rtl8169_fragmented_frame(u32 status)
4628 {
4629 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4630 }
4631
4632 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4633 {
4634 u32 status = opts1 & RxProtoMask;
4635
4636 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4637 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4638 skb->ip_summed = CHECKSUM_UNNECESSARY;
4639 else
4640 skb_checksum_none_assert(skb);
4641 }
4642
4643 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4644 struct rtl8169_private *tp,
4645 int pkt_size,
4646 dma_addr_t addr)
4647 {
4648 struct sk_buff *skb;
4649 struct device *d = &tp->pci_dev->dev;
4650
4651 data = rtl8169_align(data);
4652 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4653 prefetch(data);
4654 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4655 if (skb)
4656 memcpy(skb->data, data, pkt_size);
4657 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4658
4659 return skb;
4660 }
4661
4662 /*
4663 * Warning : rtl8169_rx_interrupt() might be called :
4664 * 1) from NAPI (softirq) context
4665 * (polling = 1 : we should call netif_receive_skb())
4666 * 2) from process context (rtl8169_reset_task())
4667 * (polling = 0 : we must call netif_rx() instead)
4668 */
4669 static int rtl8169_rx_interrupt(struct net_device *dev,
4670 struct rtl8169_private *tp,
4671 void __iomem *ioaddr, u32 budget)
4672 {
4673 unsigned int cur_rx, rx_left;
4674 unsigned int count;
4675 int polling = (budget != ~(u32)0) ? 1 : 0;
4676
4677 cur_rx = tp->cur_rx;
4678 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4679 rx_left = min(rx_left, budget);
4680
4681 for (; rx_left > 0; rx_left--, cur_rx++) {
4682 unsigned int entry = cur_rx % NUM_RX_DESC;
4683 struct RxDesc *desc = tp->RxDescArray + entry;
4684 u32 status;
4685
4686 rmb();
4687 status = le32_to_cpu(desc->opts1);
4688
4689 if (status & DescOwn)
4690 break;
4691 if (unlikely(status & RxRES)) {
4692 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4693 status);
4694 dev->stats.rx_errors++;
4695 if (status & (RxRWT | RxRUNT))
4696 dev->stats.rx_length_errors++;
4697 if (status & RxCRC)
4698 dev->stats.rx_crc_errors++;
4699 if (status & RxFOVF) {
4700 rtl8169_schedule_work(dev, rtl8169_reset_task);
4701 dev->stats.rx_fifo_errors++;
4702 }
4703 rtl8169_mark_to_asic(desc, rx_buf_sz);
4704 } else {
4705 struct sk_buff *skb;
4706 dma_addr_t addr = le64_to_cpu(desc->addr);
4707 int pkt_size = (status & 0x00001FFF) - 4;
4708
4709 /*
4710 * The driver does not support incoming fragmented
4711 * frames. They are seen as a symptom of over-mtu
4712 * sized frames.
4713 */
4714 if (unlikely(rtl8169_fragmented_frame(status))) {
4715 dev->stats.rx_dropped++;
4716 dev->stats.rx_length_errors++;
4717 rtl8169_mark_to_asic(desc, rx_buf_sz);
4718 continue;
4719 }
4720
4721 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4722 tp, pkt_size, addr);
4723 rtl8169_mark_to_asic(desc, rx_buf_sz);
4724 if (!skb) {
4725 dev->stats.rx_dropped++;
4726 continue;
4727 }
4728
4729 rtl8169_rx_csum(skb, status);
4730 skb_put(skb, pkt_size);
4731 skb->protocol = eth_type_trans(skb, dev);
4732
4733 rtl8169_rx_vlan_tag(desc, skb);
4734
4735 if (likely(polling))
4736 napi_gro_receive(&tp->napi, skb);
4737 else
4738 netif_rx(skb);
4739
4740 dev->stats.rx_bytes += pkt_size;
4741 dev->stats.rx_packets++;
4742 }
4743
4744 /* Work around for AMD plateform. */
4745 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4746 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4747 desc->opts2 = 0;
4748 cur_rx++;
4749 }
4750 }
4751
4752 count = cur_rx - tp->cur_rx;
4753 tp->cur_rx = cur_rx;
4754
4755 tp->dirty_rx += count;
4756
4757 return count;
4758 }
4759
4760 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4761 {
4762 struct net_device *dev = dev_instance;
4763 struct rtl8169_private *tp = netdev_priv(dev);
4764 void __iomem *ioaddr = tp->mmio_addr;
4765 int handled = 0;
4766 int status;
4767
4768 /* loop handling interrupts until we have no new ones or
4769 * we hit a invalid/hotplug case.
4770 */
4771 status = RTL_R16(IntrStatus);
4772 while (status && status != 0xffff) {
4773 handled = 1;
4774
4775 /* Handle all of the error cases first. These will reset
4776 * the chip, so just exit the loop.
4777 */
4778 if (unlikely(!netif_running(dev))) {
4779 rtl8169_asic_down(ioaddr);
4780 break;
4781 }
4782
4783 if (unlikely(status & RxFIFOOver)) {
4784 switch (tp->mac_version) {
4785 /* Work around for rx fifo overflow */
4786 case RTL_GIGA_MAC_VER_11:
4787 case RTL_GIGA_MAC_VER_22:
4788 case RTL_GIGA_MAC_VER_26:
4789 netif_stop_queue(dev);
4790 rtl8169_tx_timeout(dev);
4791 goto done;
4792 /* Testers needed. */
4793 case RTL_GIGA_MAC_VER_17:
4794 case RTL_GIGA_MAC_VER_19:
4795 case RTL_GIGA_MAC_VER_20:
4796 case RTL_GIGA_MAC_VER_21:
4797 case RTL_GIGA_MAC_VER_23:
4798 case RTL_GIGA_MAC_VER_24:
4799 case RTL_GIGA_MAC_VER_27:
4800 case RTL_GIGA_MAC_VER_28:
4801 /* Experimental science. Pktgen proof. */
4802 case RTL_GIGA_MAC_VER_12:
4803 case RTL_GIGA_MAC_VER_25:
4804 if (status == RxFIFOOver)
4805 goto done;
4806 break;
4807 default:
4808 break;
4809 }
4810 }
4811
4812 if (unlikely(status & SYSErr)) {
4813 rtl8169_pcierr_interrupt(dev);
4814 break;
4815 }
4816
4817 if (status & LinkChg)
4818 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4819
4820 /* We need to see the lastest version of tp->intr_mask to
4821 * avoid ignoring an MSI interrupt and having to wait for
4822 * another event which may never come.
4823 */
4824 smp_rmb();
4825 if (status & tp->intr_mask & tp->napi_event) {
4826 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4827 tp->intr_mask = ~tp->napi_event;
4828
4829 if (likely(napi_schedule_prep(&tp->napi)))
4830 __napi_schedule(&tp->napi);
4831 else
4832 netif_info(tp, intr, dev,
4833 "interrupt %04x in poll\n", status);
4834 }
4835
4836 /* We only get a new MSI interrupt when all active irq
4837 * sources on the chip have been acknowledged. So, ack
4838 * everything we've seen and check if new sources have become
4839 * active to avoid blocking all interrupts from the chip.
4840 */
4841 RTL_W16(IntrStatus,
4842 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4843 status = RTL_R16(IntrStatus);
4844 }
4845 done:
4846 return IRQ_RETVAL(handled);
4847 }
4848
4849 static int rtl8169_poll(struct napi_struct *napi, int budget)
4850 {
4851 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4852 struct net_device *dev = tp->dev;
4853 void __iomem *ioaddr = tp->mmio_addr;
4854 int work_done;
4855
4856 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4857 rtl8169_tx_interrupt(dev, tp, ioaddr);
4858
4859 if (work_done < budget) {
4860 napi_complete(napi);
4861
4862 /* We need for force the visibility of tp->intr_mask
4863 * for other CPUs, as we can loose an MSI interrupt
4864 * and potentially wait for a retransmit timeout if we don't.
4865 * The posted write to IntrMask is safe, as it will
4866 * eventually make it to the chip and we won't loose anything
4867 * until it does.
4868 */
4869 tp->intr_mask = 0xffff;
4870 wmb();
4871 RTL_W16(IntrMask, tp->intr_event);
4872 }
4873
4874 return work_done;
4875 }
4876
4877 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4878 {
4879 struct rtl8169_private *tp = netdev_priv(dev);
4880
4881 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4882 return;
4883
4884 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4885 RTL_W32(RxMissed, 0);
4886 }
4887
4888 static void rtl8169_down(struct net_device *dev)
4889 {
4890 struct rtl8169_private *tp = netdev_priv(dev);
4891 void __iomem *ioaddr = tp->mmio_addr;
4892
4893 rtl8169_delete_timer(dev);
4894
4895 netif_stop_queue(dev);
4896
4897 napi_disable(&tp->napi);
4898
4899 spin_lock_irq(&tp->lock);
4900
4901 rtl8169_asic_down(ioaddr);
4902 /*
4903 * At this point device interrupts can not be enabled in any function,
4904 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4905 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4906 */
4907 rtl8169_rx_missed(dev, ioaddr);
4908
4909 spin_unlock_irq(&tp->lock);
4910
4911 synchronize_irq(dev->irq);
4912
4913 /* Give a racing hard_start_xmit a few cycles to complete. */
4914 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4915
4916 rtl8169_tx_clear(tp);
4917
4918 rtl8169_rx_clear(tp);
4919
4920 rtl_pll_power_down(tp);
4921 }
4922
4923 static int rtl8169_close(struct net_device *dev)
4924 {
4925 struct rtl8169_private *tp = netdev_priv(dev);
4926 struct pci_dev *pdev = tp->pci_dev;
4927
4928 pm_runtime_get_sync(&pdev->dev);
4929
4930 /* update counters before going down */
4931 rtl8169_update_counters(dev);
4932
4933 rtl8169_down(dev);
4934
4935 free_irq(dev->irq, dev);
4936
4937 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4938 tp->RxPhyAddr);
4939 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4940 tp->TxPhyAddr);
4941 tp->TxDescArray = NULL;
4942 tp->RxDescArray = NULL;
4943
4944 pm_runtime_put_sync(&pdev->dev);
4945
4946 return 0;
4947 }
4948
4949 static void rtl_set_rx_mode(struct net_device *dev)
4950 {
4951 struct rtl8169_private *tp = netdev_priv(dev);
4952 void __iomem *ioaddr = tp->mmio_addr;
4953 unsigned long flags;
4954 u32 mc_filter[2]; /* Multicast hash filter */
4955 int rx_mode;
4956 u32 tmp = 0;
4957
4958 if (dev->flags & IFF_PROMISC) {
4959 /* Unconditionally log net taps. */
4960 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4961 rx_mode =
4962 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4963 AcceptAllPhys;
4964 mc_filter[1] = mc_filter[0] = 0xffffffff;
4965 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4966 (dev->flags & IFF_ALLMULTI)) {
4967 /* Too many to filter perfectly -- accept all multicasts. */
4968 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4969 mc_filter[1] = mc_filter[0] = 0xffffffff;
4970 } else {
4971 struct netdev_hw_addr *ha;
4972
4973 rx_mode = AcceptBroadcast | AcceptMyPhys;
4974 mc_filter[1] = mc_filter[0] = 0;
4975 netdev_for_each_mc_addr(ha, dev) {
4976 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4977 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4978 rx_mode |= AcceptMulticast;
4979 }
4980 }
4981
4982 spin_lock_irqsave(&tp->lock, flags);
4983
4984 tmp = rtl8169_rx_config | rx_mode |
4985 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4986
4987 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4988 u32 data = mc_filter[0];
4989
4990 mc_filter[0] = swab32(mc_filter[1]);
4991 mc_filter[1] = swab32(data);
4992 }
4993
4994 RTL_W32(MAR0 + 4, mc_filter[1]);
4995 RTL_W32(MAR0 + 0, mc_filter[0]);
4996
4997 RTL_W32(RxConfig, tmp);
4998
4999 spin_unlock_irqrestore(&tp->lock, flags);
5000 }
5001
5002 /**
5003 * rtl8169_get_stats - Get rtl8169 read/write statistics
5004 * @dev: The Ethernet Device to get statistics for
5005 *
5006 * Get TX/RX statistics for rtl8169
5007 */
5008 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5009 {
5010 struct rtl8169_private *tp = netdev_priv(dev);
5011 void __iomem *ioaddr = tp->mmio_addr;
5012 unsigned long flags;
5013
5014 if (netif_running(dev)) {
5015 spin_lock_irqsave(&tp->lock, flags);
5016 rtl8169_rx_missed(dev, ioaddr);
5017 spin_unlock_irqrestore(&tp->lock, flags);
5018 }
5019
5020 return &dev->stats;
5021 }
5022
5023 static void rtl8169_net_suspend(struct net_device *dev)
5024 {
5025 struct rtl8169_private *tp = netdev_priv(dev);
5026
5027 if (!netif_running(dev))
5028 return;
5029
5030 rtl_pll_power_down(tp);
5031
5032 netif_device_detach(dev);
5033 netif_stop_queue(dev);
5034 }
5035
5036 #ifdef CONFIG_PM
5037
5038 static int rtl8169_suspend(struct device *device)
5039 {
5040 struct pci_dev *pdev = to_pci_dev(device);
5041 struct net_device *dev = pci_get_drvdata(pdev);
5042
5043 rtl8169_net_suspend(dev);
5044
5045 return 0;
5046 }
5047
5048 static void __rtl8169_resume(struct net_device *dev)
5049 {
5050 struct rtl8169_private *tp = netdev_priv(dev);
5051
5052 netif_device_attach(dev);
5053
5054 rtl_pll_power_up(tp);
5055
5056 rtl8169_schedule_work(dev, rtl8169_reset_task);
5057 }
5058
5059 static int rtl8169_resume(struct device *device)
5060 {
5061 struct pci_dev *pdev = to_pci_dev(device);
5062 struct net_device *dev = pci_get_drvdata(pdev);
5063 struct rtl8169_private *tp = netdev_priv(dev);
5064
5065 rtl8169_init_phy(dev, tp);
5066
5067 if (netif_running(dev))
5068 __rtl8169_resume(dev);
5069
5070 return 0;
5071 }
5072
5073 static int rtl8169_runtime_suspend(struct device *device)
5074 {
5075 struct pci_dev *pdev = to_pci_dev(device);
5076 struct net_device *dev = pci_get_drvdata(pdev);
5077 struct rtl8169_private *tp = netdev_priv(dev);
5078
5079 if (!tp->TxDescArray)
5080 return 0;
5081
5082 spin_lock_irq(&tp->lock);
5083 tp->saved_wolopts = __rtl8169_get_wol(tp);
5084 __rtl8169_set_wol(tp, WAKE_ANY);
5085 spin_unlock_irq(&tp->lock);
5086
5087 rtl8169_net_suspend(dev);
5088
5089 return 0;
5090 }
5091
5092 static int rtl8169_runtime_resume(struct device *device)
5093 {
5094 struct pci_dev *pdev = to_pci_dev(device);
5095 struct net_device *dev = pci_get_drvdata(pdev);
5096 struct rtl8169_private *tp = netdev_priv(dev);
5097
5098 if (!tp->TxDescArray)
5099 return 0;
5100
5101 spin_lock_irq(&tp->lock);
5102 __rtl8169_set_wol(tp, tp->saved_wolopts);
5103 tp->saved_wolopts = 0;
5104 spin_unlock_irq(&tp->lock);
5105
5106 rtl8169_init_phy(dev, tp);
5107
5108 __rtl8169_resume(dev);
5109
5110 return 0;
5111 }
5112
5113 static int rtl8169_runtime_idle(struct device *device)
5114 {
5115 struct pci_dev *pdev = to_pci_dev(device);
5116 struct net_device *dev = pci_get_drvdata(pdev);
5117 struct rtl8169_private *tp = netdev_priv(dev);
5118
5119 return tp->TxDescArray ? -EBUSY : 0;
5120 }
5121
5122 static const struct dev_pm_ops rtl8169_pm_ops = {
5123 .suspend = rtl8169_suspend,
5124 .resume = rtl8169_resume,
5125 .freeze = rtl8169_suspend,
5126 .thaw = rtl8169_resume,
5127 .poweroff = rtl8169_suspend,
5128 .restore = rtl8169_resume,
5129 .runtime_suspend = rtl8169_runtime_suspend,
5130 .runtime_resume = rtl8169_runtime_resume,
5131 .runtime_idle = rtl8169_runtime_idle,
5132 };
5133
5134 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5135
5136 #else /* !CONFIG_PM */
5137
5138 #define RTL8169_PM_OPS NULL
5139
5140 #endif /* !CONFIG_PM */
5141
5142 static void rtl_shutdown(struct pci_dev *pdev)
5143 {
5144 struct net_device *dev = pci_get_drvdata(pdev);
5145 struct rtl8169_private *tp = netdev_priv(dev);
5146 void __iomem *ioaddr = tp->mmio_addr;
5147
5148 rtl8169_net_suspend(dev);
5149
5150 /* restore original MAC address */
5151 rtl_rar_set(tp, dev->perm_addr);
5152
5153 spin_lock_irq(&tp->lock);
5154
5155 rtl8169_asic_down(ioaddr);
5156
5157 spin_unlock_irq(&tp->lock);
5158
5159 if (system_state == SYSTEM_POWER_OFF) {
5160 /* WoL fails with some 8168 when the receiver is disabled. */
5161 if (tp->features & RTL_FEATURE_WOL) {
5162 pci_clear_master(pdev);
5163
5164 RTL_W8(ChipCmd, CmdRxEnb);
5165 /* PCI commit */
5166 RTL_R8(ChipCmd);
5167 }
5168
5169 pci_wake_from_d3(pdev, true);
5170 pci_set_power_state(pdev, PCI_D3hot);
5171 }
5172 }
5173
5174 static struct pci_driver rtl8169_pci_driver = {
5175 .name = MODULENAME,
5176 .id_table = rtl8169_pci_tbl,
5177 .probe = rtl8169_init_one,
5178 .remove = __devexit_p(rtl8169_remove_one),
5179 .shutdown = rtl_shutdown,
5180 .driver.pm = RTL8169_PM_OPS,
5181 };
5182
5183 static int __init rtl8169_init_module(void)
5184 {
5185 return pci_register_driver(&rtl8169_pci_driver);
5186 }
5187
5188 static void __exit rtl8169_cleanup_module(void)
5189 {
5190 pci_unregister_driver(&rtl8169_pci_driver);
5191 }
5192
5193 module_init(rtl8169_init_module);
5194 module_exit(rtl8169_cleanup_module);
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