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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / usb / gadget / pch_udc.c
blob3e4b35e50c2446b8926a687b1cb39e61d473cdff
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/list.h>
24 #include <linux/interrupt.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27
28 /* Address offset of Registers */
29 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
30
31 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
32 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
33 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
34 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
35 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
36 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
37 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
38
39 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
40 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
41 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
42 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
43 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
44 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
45 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
46 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
47 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
48 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
49 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
50
51 /* Endpoint control register */
52 /* Bit position */
53 #define UDC_EPCTL_MRXFLUSH (1 << 12)
54 #define UDC_EPCTL_RRDY (1 << 9)
55 #define UDC_EPCTL_CNAK (1 << 8)
56 #define UDC_EPCTL_SNAK (1 << 7)
57 #define UDC_EPCTL_NAK (1 << 6)
58 #define UDC_EPCTL_P (1 << 3)
59 #define UDC_EPCTL_F (1 << 1)
60 #define UDC_EPCTL_S (1 << 0)
61 #define UDC_EPCTL_ET_SHIFT 4
62 /* Mask patern */
63 #define UDC_EPCTL_ET_MASK 0x00000030
64 /* Value for ET field */
65 #define UDC_EPCTL_ET_CONTROL 0
66 #define UDC_EPCTL_ET_ISO 1
67 #define UDC_EPCTL_ET_BULK 2
68 #define UDC_EPCTL_ET_INTERRUPT 3
69
70 /* Endpoint status register */
71 /* Bit position */
72 #define UDC_EPSTS_XFERDONE (1 << 27)
73 #define UDC_EPSTS_RSS (1 << 26)
74 #define UDC_EPSTS_RCS (1 << 25)
75 #define UDC_EPSTS_TXEMPTY (1 << 24)
76 #define UDC_EPSTS_TDC (1 << 10)
77 #define UDC_EPSTS_HE (1 << 9)
78 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
79 #define UDC_EPSTS_BNA (1 << 7)
80 #define UDC_EPSTS_IN (1 << 6)
81 #define UDC_EPSTS_OUT_SHIFT 4
82 /* Mask patern */
83 #define UDC_EPSTS_OUT_MASK 0x00000030
84 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
85 /* Value for OUT field */
86 #define UDC_EPSTS_OUT_SETUP 2
87 #define UDC_EPSTS_OUT_DATA 1
88
89 /* Device configuration register */
90 /* Bit position */
91 #define UDC_DEVCFG_CSR_PRG (1 << 17)
92 #define UDC_DEVCFG_SP (1 << 3)
93 /* SPD Valee */
94 #define UDC_DEVCFG_SPD_HS 0x0
95 #define UDC_DEVCFG_SPD_FS 0x1
96 #define UDC_DEVCFG_SPD_LS 0x2
97
98 /* Device control register */
99 /* Bit position */
100 #define UDC_DEVCTL_THLEN_SHIFT 24
101 #define UDC_DEVCTL_BRLEN_SHIFT 16
102 #define UDC_DEVCTL_CSR_DONE (1 << 13)
103 #define UDC_DEVCTL_SD (1 << 10)
104 #define UDC_DEVCTL_MODE (1 << 9)
105 #define UDC_DEVCTL_BREN (1 << 8)
106 #define UDC_DEVCTL_THE (1 << 7)
107 #define UDC_DEVCTL_DU (1 << 4)
108 #define UDC_DEVCTL_TDE (1 << 3)
109 #define UDC_DEVCTL_RDE (1 << 2)
110 #define UDC_DEVCTL_RES (1 << 0)
111
112 /* Device status register */
113 /* Bit position */
114 #define UDC_DEVSTS_TS_SHIFT 18
115 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
116 #define UDC_DEVSTS_ALT_SHIFT 8
117 #define UDC_DEVSTS_INTF_SHIFT 4
118 #define UDC_DEVSTS_CFG_SHIFT 0
119 /* Mask patern */
120 #define UDC_DEVSTS_TS_MASK 0xfffc0000
121 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
122 #define UDC_DEVSTS_ALT_MASK 0x00000f00
123 #define UDC_DEVSTS_INTF_MASK 0x000000f0
124 #define UDC_DEVSTS_CFG_MASK 0x0000000f
125 /* value for maximum speed for SPEED field */
126 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
127 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
128 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
129 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
130
131 /* Device irq register */
132 /* Bit position */
133 #define UDC_DEVINT_RWKP (1 << 7)
134 #define UDC_DEVINT_ENUM (1 << 6)
135 #define UDC_DEVINT_SOF (1 << 5)
136 #define UDC_DEVINT_US (1 << 4)
137 #define UDC_DEVINT_UR (1 << 3)
138 #define UDC_DEVINT_ES (1 << 2)
139 #define UDC_DEVINT_SI (1 << 1)
140 #define UDC_DEVINT_SC (1 << 0)
141 /* Mask patern */
142 #define UDC_DEVINT_MSK 0x7f
143
144 /* Endpoint irq register */
145 /* Bit position */
146 #define UDC_EPINT_IN_SHIFT 0
147 #define UDC_EPINT_OUT_SHIFT 16
148 #define UDC_EPINT_IN_EP0 (1 << 0)
149 #define UDC_EPINT_OUT_EP0 (1 << 16)
150 /* Mask patern */
151 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
152
153 /* UDC_CSR_BUSY Status register */
154 /* Bit position */
155 #define UDC_CSR_BUSY (1 << 0)
156
157 /* SOFT RESET register */
158 /* Bit position */
159 #define UDC_PSRST (1 << 1)
160 #define UDC_SRST (1 << 0)
161
162 /* USB_DEVICE endpoint register */
163 /* Bit position */
164 #define UDC_CSR_NE_NUM_SHIFT 0
165 #define UDC_CSR_NE_DIR_SHIFT 4
166 #define UDC_CSR_NE_TYPE_SHIFT 5
167 #define UDC_CSR_NE_CFG_SHIFT 7
168 #define UDC_CSR_NE_INTF_SHIFT 11
169 #define UDC_CSR_NE_ALT_SHIFT 15
170 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
171 /* Mask patern */
172 #define UDC_CSR_NE_NUM_MASK 0x0000000f
173 #define UDC_CSR_NE_DIR_MASK 0x00000010
174 #define UDC_CSR_NE_TYPE_MASK 0x00000060
175 #define UDC_CSR_NE_CFG_MASK 0x00000780
176 #define UDC_CSR_NE_INTF_MASK 0x00007800
177 #define UDC_CSR_NE_ALT_MASK 0x00078000
178 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
179
180 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
181 #define PCH_UDC_EPINT(in, num)\
182 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
183
184 /* Index of endpoint */
185 #define UDC_EP0IN_IDX 0
186 #define UDC_EP0OUT_IDX 1
187 #define UDC_EPIN_IDX(ep) (ep * 2)
188 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
189 #define PCH_UDC_EP0 0
190 #define PCH_UDC_EP1 1
191 #define PCH_UDC_EP2 2
192 #define PCH_UDC_EP3 3
193
194 /* Number of endpoint */
195 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
196 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
197 /* Length Value */
198 #define PCH_UDC_BRLEN 0x0F /* Burst length */
199 #define PCH_UDC_THLEN 0x1F /* Threshold length */
200 /* Value of EP Buffer Size */
201 #define UDC_EP0IN_BUFF_SIZE 16
202 #define UDC_EPIN_BUFF_SIZE 256
203 #define UDC_EP0OUT_BUFF_SIZE 16
204 #define UDC_EPOUT_BUFF_SIZE 256
205 /* Value of EP maximum packet size */
206 #define UDC_EP0IN_MAX_PKT_SIZE 64
207 #define UDC_EP0OUT_MAX_PKT_SIZE 64
208 #define UDC_BULK_MAX_PKT_SIZE 512
209
210 /* DMA */
211 #define DMA_DIR_RX 1 /* DMA for data receive */
212 #define DMA_DIR_TX 2 /* DMA for data transmit */
213 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
214 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
215
216 /**
217 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
218 * for data
219 * @status: Status quadlet
220 * @reserved: Reserved
221 * @dataptr: Buffer descriptor
222 * @next: Next descriptor
223 */
224 struct pch_udc_data_dma_desc {
225 u32 status;
226 u32 reserved;
227 u32 dataptr;
228 u32 next;
229 };
230
231 /**
232 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
233 * for control data
234 * @status: Status
235 * @reserved: Reserved
236 * @data12: First setup word
237 * @data34: Second setup word
238 */
239 struct pch_udc_stp_dma_desc {
240 u32 status;
241 u32 reserved;
242 struct usb_ctrlrequest request;
243 } __attribute((packed));
244
245 /* DMA status definitions */
246 /* Buffer status */
247 #define PCH_UDC_BUFF_STS 0xC0000000
248 #define PCH_UDC_BS_HST_RDY 0x00000000
249 #define PCH_UDC_BS_DMA_BSY 0x40000000
250 #define PCH_UDC_BS_DMA_DONE 0x80000000
251 #define PCH_UDC_BS_HST_BSY 0xC0000000
252 /* Rx/Tx Status */
253 #define PCH_UDC_RXTX_STS 0x30000000
254 #define PCH_UDC_RTS_SUCC 0x00000000
255 #define PCH_UDC_RTS_DESERR 0x10000000
256 #define PCH_UDC_RTS_BUFERR 0x30000000
257 /* Last Descriptor Indication */
258 #define PCH_UDC_DMA_LAST 0x08000000
259 /* Number of Rx/Tx Bytes Mask */
260 #define PCH_UDC_RXTX_BYTES 0x0000ffff
261
262 /**
263 * struct pch_udc_cfg_data - Structure to hold current configuration
264 * and interface information
265 * @cur_cfg: current configuration in use
266 * @cur_intf: current interface in use
267 * @cur_alt: current alt interface in use
268 */
269 struct pch_udc_cfg_data {
270 u16 cur_cfg;
271 u16 cur_intf;
272 u16 cur_alt;
273 };
274
275 /**
276 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
277 * @ep: embedded ep request
278 * @td_stp_phys: for setup request
279 * @td_data_phys: for data request
280 * @td_stp: for setup request
281 * @td_data: for data request
282 * @dev: reference to device struct
283 * @offset_addr: offset address of ep register
284 * @desc: for this ep
285 * @queue: queue for requests
286 * @num: endpoint number
287 * @in: endpoint is IN
288 * @halted: endpoint halted?
289 * @epsts: Endpoint status
290 */
291 struct pch_udc_ep {
292 struct usb_ep ep;
293 dma_addr_t td_stp_phys;
294 dma_addr_t td_data_phys;
295 struct pch_udc_stp_dma_desc *td_stp;
296 struct pch_udc_data_dma_desc *td_data;
297 struct pch_udc_dev *dev;
298 unsigned long offset_addr;
299 const struct usb_endpoint_descriptor *desc;
300 struct list_head queue;
301 unsigned num:5,
302 in:1,
303 halted:1;
304 unsigned long epsts;
305 };
306
307 /**
308 * struct pch_udc_dev - Structure holding complete information
309 * of the PCH USB device
310 * @gadget: gadget driver data
311 * @driver: reference to gadget driver bound
312 * @pdev: reference to the PCI device
313 * @ep: array of endpoints
314 * @lock: protects all state
315 * @active: enabled the PCI device
316 * @stall: stall requested
317 * @prot_stall: protcol stall requested
318 * @irq_registered: irq registered with system
319 * @mem_region: device memory mapped
320 * @registered: driver regsitered with system
321 * @suspended: driver in suspended state
322 * @connected: gadget driver associated
323 * @set_cfg_not_acked: pending acknowledgement 4 setup
324 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
325 * @data_requests: DMA pool for data requests
326 * @stp_requests: DMA pool for setup requests
327 * @dma_addr: DMA pool for received
328 * @ep0out_buf: Buffer for DMA
329 * @setup_data: Received setup data
330 * @phys_addr: of device memory
331 * @base_addr: for mapped device memory
332 * @irq: IRQ line for the device
333 * @cfg_data: current cfg, intf, and alt in use
334 */
335 struct pch_udc_dev {
336 struct usb_gadget gadget;
337 struct usb_gadget_driver *driver;
338 struct pci_dev *pdev;
339 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
340 spinlock_t lock; /* protects all state */
341 unsigned active:1,
342 stall:1,
343 prot_stall:1,
344 irq_registered:1,
345 mem_region:1,
346 registered:1,
347 suspended:1,
348 connected:1,
349 set_cfg_not_acked:1,
350 waiting_zlp_ack:1;
351 struct pci_pool *data_requests;
352 struct pci_pool *stp_requests;
353 dma_addr_t dma_addr;
354 void *ep0out_buf;
355 struct usb_ctrlrequest setup_data;
356 unsigned long phys_addr;
357 void __iomem *base_addr;
358 unsigned irq;
359 struct pch_udc_cfg_data cfg_data;
360 };
361
362 #define PCH_UDC_PCI_BAR 1
363 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
364 #define PCI_VENDOR_ID_ROHM 0x10DB
365 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
366
367 static const char ep0_string[] = "ep0in";
368 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
369 struct pch_udc_dev *pch_udc; /* pointer to device object */
370 static int speed_fs;
371 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
372 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
373
374 /**
375 * struct pch_udc_request - Structure holding a PCH USB device request packet
376 * @req: embedded ep request
377 * @td_data_phys: phys. address
378 * @td_data: first dma desc. of chain
379 * @td_data_last: last dma desc. of chain
380 * @queue: associated queue
381 * @dma_going: DMA in progress for request
382 * @dma_mapped: DMA memory mapped for request
383 * @dma_done: DMA completed for request
384 * @chain_len: chain length
385 * @buf: Buffer memory for align adjustment
386 * @dma: DMA memory for align adjustment
387 */
388 struct pch_udc_request {
389 struct usb_request req;
390 dma_addr_t td_data_phys;
391 struct pch_udc_data_dma_desc *td_data;
392 struct pch_udc_data_dma_desc *td_data_last;
393 struct list_head queue;
394 unsigned dma_going:1,
395 dma_mapped:1,
396 dma_done:1;
397 unsigned chain_len;
398 void *buf;
399 dma_addr_t dma;
400 };
401
402 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
403 {
404 return ioread32(dev->base_addr + reg);
405 }
406
407 static inline void pch_udc_writel(struct pch_udc_dev *dev,
408 unsigned long val, unsigned long reg)
409 {
410 iowrite32(val, dev->base_addr + reg);
411 }
412
413 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
414 unsigned long reg,
415 unsigned long bitmask)
416 {
417 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
418 }
419
420 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
421 unsigned long reg,
422 unsigned long bitmask)
423 {
424 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
425 }
426
427 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
428 {
429 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
430 }
431
432 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
433 unsigned long val, unsigned long reg)
434 {
435 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
436 }
437
438 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
439 unsigned long reg,
440 unsigned long bitmask)
441 {
442 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
443 }
444
445 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
446 unsigned long reg,
447 unsigned long bitmask)
448 {
449 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
450 }
451
452 /**
453 * pch_udc_csr_busy() - Wait till idle.
454 * @dev: Reference to pch_udc_dev structure
455 */
456 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
457 {
458 unsigned int count = 200;
459
460 /* Wait till idle */
461 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
462 && --count)
463 cpu_relax();
464 if (!count)
465 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
466 }
467
468 /**
469 * pch_udc_write_csr() - Write the command and status registers.
470 * @dev: Reference to pch_udc_dev structure
471 * @val: value to be written to CSR register
472 * @addr: address of CSR register
473 */
474 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
475 unsigned int ep)
476 {
477 unsigned long reg = PCH_UDC_CSR(ep);
478
479 pch_udc_csr_busy(dev); /* Wait till idle */
480 pch_udc_writel(dev, val, reg);
481 pch_udc_csr_busy(dev); /* Wait till idle */
482 }
483
484 /**
485 * pch_udc_read_csr() - Read the command and status registers.
486 * @dev: Reference to pch_udc_dev structure
487 * @addr: address of CSR register
488 *
489 * Return codes: content of CSR register
490 */
491 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
492 {
493 unsigned long reg = PCH_UDC_CSR(ep);
494
495 pch_udc_csr_busy(dev); /* Wait till idle */
496 pch_udc_readl(dev, reg); /* Dummy read */
497 pch_udc_csr_busy(dev); /* Wait till idle */
498 return pch_udc_readl(dev, reg);
499 }
500
501 /**
502 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
503 * @dev: Reference to pch_udc_dev structure
504 */
505 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
506 {
507 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
508 mdelay(1);
509 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
510 }
511
512 /**
513 * pch_udc_get_frame() - Get the current frame from device status register
514 * @dev: Reference to pch_udc_dev structure
515 * Retern current frame
516 */
517 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
518 {
519 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
520 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
521 }
522
523 /**
524 * pch_udc_clear_selfpowered() - Clear the self power control
525 * @dev: Reference to pch_udc_regs structure
526 */
527 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
528 {
529 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
530 }
531
532 /**
533 * pch_udc_set_selfpowered() - Set the self power control
534 * @dev: Reference to pch_udc_regs structure
535 */
536 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
537 {
538 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
539 }
540
541 /**
542 * pch_udc_set_disconnect() - Set the disconnect status.
543 * @dev: Reference to pch_udc_regs structure
544 */
545 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
546 {
547 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
548 }
549
550 /**
551 * pch_udc_clear_disconnect() - Clear the disconnect status.
552 * @dev: Reference to pch_udc_regs structure
553 */
554 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
555 {
556 /* Clear the disconnect */
557 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
558 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
559 mdelay(1);
560 /* Resume USB signalling */
561 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
562 }
563
564 /**
565 * pch_udc_vbus_session() - set or clearr the disconnect status.
566 * @dev: Reference to pch_udc_regs structure
567 * @is_active: Parameter specifying the action
568 * 0: indicating VBUS power is ending
569 * !0: indicating VBUS power is starting
570 */
571 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
572 int is_active)
573 {
574 if (is_active)
575 pch_udc_clear_disconnect(dev);
576 else
577 pch_udc_set_disconnect(dev);
578 }
579
580 /**
581 * pch_udc_ep_set_stall() - Set the stall of endpoint
582 * @ep: Reference to structure of type pch_udc_ep_regs
583 */
584 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
585 {
586 if (ep->in) {
587 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
588 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
589 } else {
590 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
591 }
592 }
593
594 /**
595 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
596 * @ep: Reference to structure of type pch_udc_ep_regs
597 */
598 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
599 {
600 /* Clear the stall */
601 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
602 /* Clear NAK by writing CNAK */
603 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
604 }
605
606 /**
607 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
608 * @ep: Reference to structure of type pch_udc_ep_regs
609 * @type: Type of endpoint
610 */
611 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
612 u8 type)
613 {
614 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
615 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
616 }
617
618 /**
619 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
620 * @ep: Reference to structure of type pch_udc_ep_regs
621 * @buf_size: The buffer word size
622 */
623 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
624 u32 buf_size, u32 ep_in)
625 {
626 u32 data;
627 if (ep_in) {
628 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
629 data = (data & 0xffff0000) | (buf_size & 0xffff);
630 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
631 } else {
632 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
633 data = (buf_size << 16) | (data & 0xffff);
634 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
635 }
636 }
637
638 /**
639 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
640 * @ep: Reference to structure of type pch_udc_ep_regs
641 * @pkt_size: The packet byte size
642 */
643 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
644 {
645 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
646 data = (data & 0xffff0000) | (pkt_size & 0xffff);
647 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
648 }
649
650 /**
651 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
652 * @ep: Reference to structure of type pch_udc_ep_regs
653 * @addr: Address of the register
654 */
655 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
656 {
657 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
658 }
659
660 /**
661 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
662 * @ep: Reference to structure of type pch_udc_ep_regs
663 * @addr: Address of the register
664 */
665 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
666 {
667 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
668 }
669
670 /**
671 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
672 * @ep: Reference to structure of type pch_udc_ep_regs
673 */
674 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
675 {
676 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
677 }
678
679 /**
680 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
681 * @ep: Reference to structure of type pch_udc_ep_regs
682 */
683 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
684 {
685 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
686 }
687
688 /**
689 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
690 * @ep: Reference to structure of type pch_udc_ep_regs
691 */
692 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
693 {
694 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
695 }
696
697 /**
698 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
699 * register depending on the direction specified
700 * @dev: Reference to structure of type pch_udc_regs
701 * @dir: whether Tx or Rx
702 * DMA_DIR_RX: Receive
703 * DMA_DIR_TX: Transmit
704 */
705 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
706 {
707 if (dir == DMA_DIR_RX)
708 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
709 else if (dir == DMA_DIR_TX)
710 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
711 }
712
713 /**
714 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
715 * register depending on the direction specified
716 * @dev: Reference to structure of type pch_udc_regs
717 * @dir: Whether Tx or Rx
718 * DMA_DIR_RX: Receive
719 * DMA_DIR_TX: Transmit
720 */
721 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
722 {
723 if (dir == DMA_DIR_RX)
724 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
725 else if (dir == DMA_DIR_TX)
726 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
727 }
728
729 /**
730 * pch_udc_set_csr_done() - Set the device control register
731 * CSR done field (bit 13)
732 * @dev: reference to structure of type pch_udc_regs
733 */
734 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
735 {
736 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
737 }
738
739 /**
740 * pch_udc_disable_interrupts() - Disables the specified interrupts
741 * @dev: Reference to structure of type pch_udc_regs
742 * @mask: Mask to disable interrupts
743 */
744 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
745 u32 mask)
746 {
747 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
748 }
749
750 /**
751 * pch_udc_enable_interrupts() - Enable the specified interrupts
752 * @dev: Reference to structure of type pch_udc_regs
753 * @mask: Mask to enable interrupts
754 */
755 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
756 u32 mask)
757 {
758 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
759 }
760
761 /**
762 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
763 * @dev: Reference to structure of type pch_udc_regs
764 * @mask: Mask to disable interrupts
765 */
766 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
767 u32 mask)
768 {
769 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
770 }
771
772 /**
773 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
774 * @dev: Reference to structure of type pch_udc_regs
775 * @mask: Mask to enable interrupts
776 */
777 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
778 u32 mask)
779 {
780 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
781 }
782
783 /**
784 * pch_udc_read_device_interrupts() - Read the device interrupts
785 * @dev: Reference to structure of type pch_udc_regs
786 * Retern The device interrupts
787 */
788 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
789 {
790 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
791 }
792
793 /**
794 * pch_udc_write_device_interrupts() - Write device interrupts
795 * @dev: Reference to structure of type pch_udc_regs
796 * @val: The value to be written to interrupt register
797 */
798 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
799 u32 val)
800 {
801 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
802 }
803
804 /**
805 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
806 * @dev: Reference to structure of type pch_udc_regs
807 * Retern The endpoint interrupt
808 */
809 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
810 {
811 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
812 }
813
814 /**
815 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
816 * @dev: Reference to structure of type pch_udc_regs
817 * @val: The value to be written to interrupt register
818 */
819 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
820 u32 val)
821 {
822 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
823 }
824
825 /**
826 * pch_udc_read_device_status() - Read the device status
827 * @dev: Reference to structure of type pch_udc_regs
828 * Retern The device status
829 */
830 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
831 {
832 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
833 }
834
835 /**
836 * pch_udc_read_ep_control() - Read the endpoint control
837 * @ep: Reference to structure of type pch_udc_ep_regs
838 * Retern The endpoint control register value
839 */
840 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
841 {
842 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
843 }
844
845 /**
846 * pch_udc_clear_ep_control() - Clear the endpoint control register
847 * @ep: Reference to structure of type pch_udc_ep_regs
848 * Retern The endpoint control register value
849 */
850 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
851 {
852 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
853 }
854
855 /**
856 * pch_udc_read_ep_status() - Read the endpoint status
857 * @ep: Reference to structure of type pch_udc_ep_regs
858 * Retern The endpoint status
859 */
860 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
861 {
862 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
863 }
864
865 /**
866 * pch_udc_clear_ep_status() - Clear the endpoint status
867 * @ep: Reference to structure of type pch_udc_ep_regs
868 * @stat: Endpoint status
869 */
870 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
871 u32 stat)
872 {
873 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
874 }
875
876 /**
877 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
878 * of the endpoint control register
879 * @ep: Reference to structure of type pch_udc_ep_regs
880 */
881 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
882 {
883 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
884 }
885
886 /**
887 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
888 * of the endpoint control register
889 * @ep: reference to structure of type pch_udc_ep_regs
890 */
891 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
892 {
893 unsigned int loopcnt = 0;
894 struct pch_udc_dev *dev = ep->dev;
895
896 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
897 return;
898 if (!ep->in) {
899 loopcnt = 10000;
900 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
901 --loopcnt)
902 udelay(5);
903 if (!loopcnt)
904 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
905 __func__);
906 }
907 loopcnt = 10000;
908 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
909 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
910 udelay(5);
911 }
912 if (!loopcnt)
913 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
914 __func__, ep->num, (ep->in ? "in" : "out"));
915 }
916
917 /**
918 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
919 * @ep: reference to structure of type pch_udc_ep_regs
920 * @dir: direction of endpoint
921 * 0: endpoint is OUT
922 * !0: endpoint is IN
923 */
924 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
925 {
926 if (dir) { /* IN ep */
927 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
928 return;
929 }
930 }
931
932 /**
933 * pch_udc_ep_enable() - This api enables endpoint
934 * @regs: Reference to structure pch_udc_ep_regs
935 * @desc: endpoint descriptor
936 */
937 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
938 struct pch_udc_cfg_data *cfg,
939 const struct usb_endpoint_descriptor *desc)
940 {
941 u32 val = 0;
942 u32 buff_size = 0;
943
944 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
945 if (ep->in)
946 buff_size = UDC_EPIN_BUFF_SIZE;
947 else
948 buff_size = UDC_EPOUT_BUFF_SIZE;
949 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
950 pch_udc_ep_set_maxpkt(ep, le16_to_cpu(desc->wMaxPacketSize));
951 pch_udc_ep_set_nak(ep);
952 pch_udc_ep_fifo_flush(ep, ep->in);
953 /* Configure the endpoint */
954 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
955 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
956 UDC_CSR_NE_TYPE_SHIFT) |
957 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
958 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
959 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
960 le16_to_cpu(desc->wMaxPacketSize) << UDC_CSR_NE_MAX_PKT_SHIFT;
961
962 if (ep->in)
963 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
964 else
965 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
966 }
967
968 /**
969 * pch_udc_ep_disable() - This api disables endpoint
970 * @regs: Reference to structure pch_udc_ep_regs
971 */
972 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
973 {
974 if (ep->in) {
975 /* flush the fifo */
976 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
977 /* set NAK */
978 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
979 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
980 } else {
981 /* set NAK */
982 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
983 }
984 /* reset desc pointer */
985 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
986 }
987
988 /**
989 * pch_udc_wait_ep_stall() - Wait EP stall.
990 * @dev: Reference to pch_udc_dev structure
991 */
992 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
993 {
994 unsigned int count = 10000;
995
996 /* Wait till idle */
997 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
998 udelay(5);
999 if (!count)
1000 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1001 }
1002
1003 /**
1004 * pch_udc_init() - This API initializes usb device controller
1005 * @dev: Rreference to pch_udc_regs structure
1006 */
1007 static void pch_udc_init(struct pch_udc_dev *dev)
1008 {
1009 if (NULL == dev) {
1010 pr_err("%s: Invalid address\n", __func__);
1011 return;
1012 }
1013 /* Soft Reset and Reset PHY */
1014 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1015 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1016 mdelay(1);
1017 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1018 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1019 mdelay(1);
1020 /* mask and clear all device interrupts */
1021 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1022 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1023
1024 /* mask and clear all ep interrupts */
1025 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1026 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1027
1028 /* enable dynamic CSR programmingi, self powered and device speed */
1029 if (speed_fs)
1030 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1031 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1032 else /* defaul high speed */
1033 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1034 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1035 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1036 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1037 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1038 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1039 UDC_DEVCTL_THE);
1040 }
1041
1042 /**
1043 * pch_udc_exit() - This API exit usb device controller
1044 * @dev: Reference to pch_udc_regs structure
1045 */
1046 static void pch_udc_exit(struct pch_udc_dev *dev)
1047 {
1048 /* mask all device interrupts */
1049 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1050 /* mask all ep interrupts */
1051 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1052 /* put device in disconnected state */
1053 pch_udc_set_disconnect(dev);
1054 }
1055
1056 /**
1057 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1058 * @gadget: Reference to the gadget driver
1059 *
1060 * Return codes:
1061 * 0: Success
1062 * -EINVAL: If the gadget passed is NULL
1063 */
1064 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1065 {
1066 struct pch_udc_dev *dev;
1067
1068 if (!gadget)
1069 return -EINVAL;
1070 dev = container_of(gadget, struct pch_udc_dev, gadget);
1071 return pch_udc_get_frame(dev);
1072 }
1073
1074 /**
1075 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1076 * @gadget: Reference to the gadget driver
1077 *
1078 * Return codes:
1079 * 0: Success
1080 * -EINVAL: If the gadget passed is NULL
1081 */
1082 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1083 {
1084 struct pch_udc_dev *dev;
1085 unsigned long flags;
1086
1087 if (!gadget)
1088 return -EINVAL;
1089 dev = container_of(gadget, struct pch_udc_dev, gadget);
1090 spin_lock_irqsave(&dev->lock, flags);
1091 pch_udc_rmt_wakeup(dev);
1092 spin_unlock_irqrestore(&dev->lock, flags);
1093 return 0;
1094 }
1095
1096 /**
1097 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1098 * is self powered or not
1099 * @gadget: Reference to the gadget driver
1100 * @value: Specifies self powered or not
1101 *
1102 * Return codes:
1103 * 0: Success
1104 * -EINVAL: If the gadget passed is NULL
1105 */
1106 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1107 {
1108 struct pch_udc_dev *dev;
1109
1110 if (!gadget)
1111 return -EINVAL;
1112 dev = container_of(gadget, struct pch_udc_dev, gadget);
1113 if (value)
1114 pch_udc_set_selfpowered(dev);
1115 else
1116 pch_udc_clear_selfpowered(dev);
1117 return 0;
1118 }
1119
1120 /**
1121 * pch_udc_pcd_pullup() - This API is invoked to make the device
1122 * visible/invisible to the host
1123 * @gadget: Reference to the gadget driver
1124 * @is_on: Specifies whether the pull up is made active or inactive
1125 *
1126 * Return codes:
1127 * 0: Success
1128 * -EINVAL: If the gadget passed is NULL
1129 */
1130 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1131 {
1132 struct pch_udc_dev *dev;
1133
1134 if (!gadget)
1135 return -EINVAL;
1136 dev = container_of(gadget, struct pch_udc_dev, gadget);
1137 pch_udc_vbus_session(dev, is_on);
1138 return 0;
1139 }
1140
1141 /**
1142 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1143 * transceiver (or GPIO) that
1144 * detects a VBUS power session starting/ending
1145 * @gadget: Reference to the gadget driver
1146 * @is_active: specifies whether the session is starting or ending
1147 *
1148 * Return codes:
1149 * 0: Success
1150 * -EINVAL: If the gadget passed is NULL
1151 */
1152 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1153 {
1154 struct pch_udc_dev *dev;
1155
1156 if (!gadget)
1157 return -EINVAL;
1158 dev = container_of(gadget, struct pch_udc_dev, gadget);
1159 pch_udc_vbus_session(dev, is_active);
1160 return 0;
1161 }
1162
1163 /**
1164 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1165 * SET_CONFIGURATION calls to
1166 * specify how much power the device can consume
1167 * @gadget: Reference to the gadget driver
1168 * @mA: specifies the current limit in 2mA unit
1169 *
1170 * Return codes:
1171 * -EINVAL: If the gadget passed is NULL
1172 * -EOPNOTSUPP:
1173 */
1174 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1175 {
1176 return -EOPNOTSUPP;
1177 }
1178
1179 static const struct usb_gadget_ops pch_udc_ops = {
1180 .get_frame = pch_udc_pcd_get_frame,
1181 .wakeup = pch_udc_pcd_wakeup,
1182 .set_selfpowered = pch_udc_pcd_selfpowered,
1183 .pullup = pch_udc_pcd_pullup,
1184 .vbus_session = pch_udc_pcd_vbus_session,
1185 .vbus_draw = pch_udc_pcd_vbus_draw,
1186 };
1187
1188 /**
1189 * complete_req() - This API is invoked from the driver when processing
1190 * of a request is complete
1191 * @ep: Reference to the endpoint structure
1192 * @req: Reference to the request structure
1193 * @status: Indicates the success/failure of completion
1194 */
1195 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1196 int status)
1197 {
1198 struct pch_udc_dev *dev;
1199 unsigned halted = ep->halted;
1200
1201 list_del_init(&req->queue);
1202
1203 /* set new status if pending */
1204 if (req->req.status == -EINPROGRESS)
1205 req->req.status = status;
1206 else
1207 status = req->req.status;
1208
1209 dev = ep->dev;
1210 if (req->dma_mapped) {
1211 if (req->dma == DMA_ADDR_INVALID) {
1212 if (ep->in)
1213 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1214 req->req.length,
1215 DMA_TO_DEVICE);
1216 else
1217 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1218 req->req.length,
1219 DMA_FROM_DEVICE);
1220 req->req.dma = DMA_ADDR_INVALID;
1221 } else {
1222 if (ep->in)
1223 dma_unmap_single(&dev->pdev->dev, req->dma,
1224 req->req.length,
1225 DMA_TO_DEVICE);
1226 else {
1227 dma_unmap_single(&dev->pdev->dev, req->dma,
1228 req->req.length,
1229 DMA_FROM_DEVICE);
1230 memcpy(req->req.buf, req->buf, req->req.length);
1231 }
1232 kfree(req->buf);
1233 req->dma = DMA_ADDR_INVALID;
1234 }
1235 req->dma_mapped = 0;
1236 }
1237 ep->halted = 1;
1238 spin_unlock(&dev->lock);
1239 if (!ep->in)
1240 pch_udc_ep_clear_rrdy(ep);
1241 req->req.complete(&ep->ep, &req->req);
1242 spin_lock(&dev->lock);
1243 ep->halted = halted;
1244 }
1245
1246 /**
1247 * empty_req_queue() - This API empties the request queue of an endpoint
1248 * @ep: Reference to the endpoint structure
1249 */
1250 static void empty_req_queue(struct pch_udc_ep *ep)
1251 {
1252 struct pch_udc_request *req;
1253
1254 ep->halted = 1;
1255 while (!list_empty(&ep->queue)) {
1256 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1257 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1258 }
1259 }
1260
1261 /**
1262 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1263 * for the request
1264 * @dev Reference to the driver structure
1265 * @req Reference to the request to be freed
1266 *
1267 * Return codes:
1268 * 0: Success
1269 */
1270 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1271 struct pch_udc_request *req)
1272 {
1273 struct pch_udc_data_dma_desc *td = req->td_data;
1274 unsigned i = req->chain_len;
1275
1276 dma_addr_t addr2;
1277 dma_addr_t addr = (dma_addr_t)td->next;
1278 td->next = 0x00;
1279 for (; i > 1; --i) {
1280 /* do not free first desc., will be done by free for request */
1281 td = phys_to_virt(addr);
1282 addr2 = (dma_addr_t)td->next;
1283 pci_pool_free(dev->data_requests, td, addr);
1284 td->next = 0x00;
1285 addr = addr2;
1286 }
1287 req->chain_len = 1;
1288 }
1289
1290 /**
1291 * pch_udc_create_dma_chain() - This function creates or reinitializes
1292 * a DMA chain
1293 * @ep: Reference to the endpoint structure
1294 * @req: Reference to the request
1295 * @buf_len: The buffer length
1296 * @gfp_flags: Flags to be used while mapping the data buffer
1297 *
1298 * Return codes:
1299 * 0: success,
1300 * -ENOMEM: pci_pool_alloc invocation fails
1301 */
1302 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1303 struct pch_udc_request *req,
1304 unsigned long buf_len,
1305 gfp_t gfp_flags)
1306 {
1307 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1308 unsigned long bytes = req->req.length, i = 0;
1309 dma_addr_t dma_addr;
1310 unsigned len = 1;
1311
1312 if (req->chain_len > 1)
1313 pch_udc_free_dma_chain(ep->dev, req);
1314
1315 if (req->dma == DMA_ADDR_INVALID)
1316 td->dataptr = req->req.dma;
1317 else
1318 td->dataptr = req->dma;
1319
1320 td->status = PCH_UDC_BS_HST_BSY;
1321 for (; ; bytes -= buf_len, ++len) {
1322 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1323 if (bytes <= buf_len)
1324 break;
1325 last = td;
1326 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1327 &dma_addr);
1328 if (!td)
1329 goto nomem;
1330 i += buf_len;
1331 td->dataptr = req->td_data->dataptr + i;
1332 last->next = dma_addr;
1333 }
1334
1335 req->td_data_last = td;
1336 td->status |= PCH_UDC_DMA_LAST;
1337 td->next = req->td_data_phys;
1338 req->chain_len = len;
1339 return 0;
1340
1341 nomem:
1342 if (len > 1) {
1343 req->chain_len = len;
1344 pch_udc_free_dma_chain(ep->dev, req);
1345 }
1346 req->chain_len = 1;
1347 return -ENOMEM;
1348 }
1349
1350 /**
1351 * prepare_dma() - This function creates and initializes the DMA chain
1352 * for the request
1353 * @ep: Reference to the endpoint structure
1354 * @req: Reference to the request
1355 * @gfp: Flag to be used while mapping the data buffer
1356 *
1357 * Return codes:
1358 * 0: Success
1359 * Other 0: linux error number on failure
1360 */
1361 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1362 gfp_t gfp)
1363 {
1364 int retval;
1365
1366 /* Allocate and create a DMA chain */
1367 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1368 if (retval) {
1369 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1370 return retval;
1371 }
1372 if (ep->in)
1373 req->td_data->status = (req->td_data->status &
1374 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1375 return 0;
1376 }
1377
1378 /**
1379 * process_zlp() - This function process zero length packets
1380 * from the gadget driver
1381 * @ep: Reference to the endpoint structure
1382 * @req: Reference to the request
1383 */
1384 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1385 {
1386 struct pch_udc_dev *dev = ep->dev;
1387
1388 /* IN zlp's are handled by hardware */
1389 complete_req(ep, req, 0);
1390
1391 /* if set_config or set_intf is waiting for ack by zlp
1392 * then set CSR_DONE
1393 */
1394 if (dev->set_cfg_not_acked) {
1395 pch_udc_set_csr_done(dev);
1396 dev->set_cfg_not_acked = 0;
1397 }
1398 /* setup command is ACK'ed now by zlp */
1399 if (!dev->stall && dev->waiting_zlp_ack) {
1400 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1401 dev->waiting_zlp_ack = 0;
1402 }
1403 }
1404
1405 /**
1406 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1407 * @ep: Reference to the endpoint structure
1408 * @req: Reference to the request structure
1409 */
1410 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1411 struct pch_udc_request *req)
1412 {
1413 struct pch_udc_data_dma_desc *td_data;
1414
1415 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1416 td_data = req->td_data;
1417 /* Set the status bits for all descriptors */
1418 while (1) {
1419 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1420 PCH_UDC_BS_HST_RDY;
1421 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1422 break;
1423 td_data = phys_to_virt(td_data->next);
1424 }
1425 /* Write the descriptor pointer */
1426 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1427 req->dma_going = 1;
1428 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1429 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1430 pch_udc_ep_clear_nak(ep);
1431 pch_udc_ep_set_rrdy(ep);
1432 }
1433
1434 /**
1435 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1436 * from gadget driver
1437 * @usbep: Reference to the USB endpoint structure
1438 * @desc: Reference to the USB endpoint descriptor structure
1439 *
1440 * Return codes:
1441 * 0: Success
1442 * -EINVAL:
1443 * -ESHUTDOWN:
1444 */
1445 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1446 const struct usb_endpoint_descriptor *desc)
1447 {
1448 struct pch_udc_ep *ep;
1449 struct pch_udc_dev *dev;
1450 unsigned long iflags;
1451
1452 if (!usbep || (usbep->name == ep0_string) || !desc ||
1453 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1454 return -EINVAL;
1455
1456 ep = container_of(usbep, struct pch_udc_ep, ep);
1457 dev = ep->dev;
1458 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1459 return -ESHUTDOWN;
1460 spin_lock_irqsave(&dev->lock, iflags);
1461 ep->desc = desc;
1462 ep->halted = 0;
1463 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1464 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
1465 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1466 spin_unlock_irqrestore(&dev->lock, iflags);
1467 return 0;
1468 }
1469
1470 /**
1471 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1472 * from gadget driver
1473 * @usbep Reference to the USB endpoint structure
1474 *
1475 * Return codes:
1476 * 0: Success
1477 * -EINVAL:
1478 */
1479 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1480 {
1481 struct pch_udc_ep *ep;
1482 struct pch_udc_dev *dev;
1483 unsigned long iflags;
1484
1485 if (!usbep)
1486 return -EINVAL;
1487
1488 ep = container_of(usbep, struct pch_udc_ep, ep);
1489 dev = ep->dev;
1490 if ((usbep->name == ep0_string) || !ep->desc)
1491 return -EINVAL;
1492
1493 spin_lock_irqsave(&ep->dev->lock, iflags);
1494 empty_req_queue(ep);
1495 ep->halted = 1;
1496 pch_udc_ep_disable(ep);
1497 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1498 ep->desc = NULL;
1499 INIT_LIST_HEAD(&ep->queue);
1500 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1501 return 0;
1502 }
1503
1504 /**
1505 * pch_udc_alloc_request() - This function allocates request structure.
1506 * It is called by gadget driver
1507 * @usbep: Reference to the USB endpoint structure
1508 * @gfp: Flag to be used while allocating memory
1509 *
1510 * Return codes:
1511 * NULL: Failure
1512 * Allocated address: Success
1513 */
1514 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1515 gfp_t gfp)
1516 {
1517 struct pch_udc_request *req;
1518 struct pch_udc_ep *ep;
1519 struct pch_udc_data_dma_desc *dma_desc;
1520 struct pch_udc_dev *dev;
1521
1522 if (!usbep)
1523 return NULL;
1524 ep = container_of(usbep, struct pch_udc_ep, ep);
1525 dev = ep->dev;
1526 req = kzalloc(sizeof *req, gfp);
1527 if (!req)
1528 return NULL;
1529 req->req.dma = DMA_ADDR_INVALID;
1530 req->dma = DMA_ADDR_INVALID;
1531 INIT_LIST_HEAD(&req->queue);
1532 if (!ep->dev->dma_addr)
1533 return &req->req;
1534 /* ep0 in requests are allocated from data pool here */
1535 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1536 &req->td_data_phys);
1537 if (NULL == dma_desc) {
1538 kfree(req);
1539 return NULL;
1540 }
1541 /* prevent from using desc. - set HOST BUSY */
1542 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1543 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1544 req->td_data = dma_desc;
1545 req->td_data_last = dma_desc;
1546 req->chain_len = 1;
1547 return &req->req;
1548 }
1549
1550 /**
1551 * pch_udc_free_request() - This function frees request structure.
1552 * It is called by gadget driver
1553 * @usbep: Reference to the USB endpoint structure
1554 * @usbreq: Reference to the USB request
1555 */
1556 static void pch_udc_free_request(struct usb_ep *usbep,
1557 struct usb_request *usbreq)
1558 {
1559 struct pch_udc_ep *ep;
1560 struct pch_udc_request *req;
1561 struct pch_udc_dev *dev;
1562
1563 if (!usbep || !usbreq)
1564 return;
1565 ep = container_of(usbep, struct pch_udc_ep, ep);
1566 req = container_of(usbreq, struct pch_udc_request, req);
1567 dev = ep->dev;
1568 if (!list_empty(&req->queue))
1569 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1570 __func__, usbep->name, req);
1571 if (req->td_data != NULL) {
1572 if (req->chain_len > 1)
1573 pch_udc_free_dma_chain(ep->dev, req);
1574 pci_pool_free(ep->dev->data_requests, req->td_data,
1575 req->td_data_phys);
1576 }
1577 kfree(req);
1578 }
1579
1580 /**
1581 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1582 * by gadget driver
1583 * @usbep: Reference to the USB endpoint structure
1584 * @usbreq: Reference to the USB request
1585 * @gfp: Flag to be used while mapping the data buffer
1586 *
1587 * Return codes:
1588 * 0: Success
1589 * linux error number: Failure
1590 */
1591 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1592 gfp_t gfp)
1593 {
1594 int retval = 0;
1595 struct pch_udc_ep *ep;
1596 struct pch_udc_dev *dev;
1597 struct pch_udc_request *req;
1598 unsigned long iflags;
1599
1600 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1601 return -EINVAL;
1602 ep = container_of(usbep, struct pch_udc_ep, ep);
1603 dev = ep->dev;
1604 if (!ep->desc && ep->num)
1605 return -EINVAL;
1606 req = container_of(usbreq, struct pch_udc_request, req);
1607 if (!list_empty(&req->queue))
1608 return -EINVAL;
1609 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1610 return -ESHUTDOWN;
1611 spin_lock_irqsave(&ep->dev->lock, iflags);
1612 /* map the buffer for dma */
1613 if (usbreq->length &&
1614 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1615 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1616 if (ep->in)
1617 usbreq->dma = dma_map_single(&dev->pdev->dev,
1618 usbreq->buf,
1619 usbreq->length,
1620 DMA_TO_DEVICE);
1621 else
1622 usbreq->dma = dma_map_single(&dev->pdev->dev,
1623 usbreq->buf,
1624 usbreq->length,
1625 DMA_FROM_DEVICE);
1626 } else {
1627 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1628 if (!req->buf)
1629 return -ENOMEM;
1630 if (ep->in) {
1631 memcpy(req->buf, usbreq->buf, usbreq->length);
1632 req->dma = dma_map_single(&dev->pdev->dev,
1633 req->buf,
1634 usbreq->length,
1635 DMA_TO_DEVICE);
1636 } else
1637 req->dma = dma_map_single(&dev->pdev->dev,
1638 req->buf,
1639 usbreq->length,
1640 DMA_FROM_DEVICE);
1641 }
1642 req->dma_mapped = 1;
1643 }
1644 if (usbreq->length > 0) {
1645 retval = prepare_dma(ep, req, GFP_ATOMIC);
1646 if (retval)
1647 goto probe_end;
1648 }
1649 usbreq->actual = 0;
1650 usbreq->status = -EINPROGRESS;
1651 req->dma_done = 0;
1652 if (list_empty(&ep->queue) && !ep->halted) {
1653 /* no pending transfer, so start this req */
1654 if (!usbreq->length) {
1655 process_zlp(ep, req);
1656 retval = 0;
1657 goto probe_end;
1658 }
1659 if (!ep->in) {
1660 pch_udc_start_rxrequest(ep, req);
1661 } else {
1662 /*
1663 * For IN trfr the descriptors will be programmed and
1664 * P bit will be set when
1665 * we get an IN token
1666 */
1667 pch_udc_wait_ep_stall(ep);
1668 pch_udc_ep_clear_nak(ep);
1669 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1670 }
1671 }
1672 /* Now add this request to the ep's pending requests */
1673 if (req != NULL)
1674 list_add_tail(&req->queue, &ep->queue);
1675
1676 probe_end:
1677 spin_unlock_irqrestore(&dev->lock, iflags);
1678 return retval;
1679 }
1680
1681 /**
1682 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1683 * It is called by gadget driver
1684 * @usbep: Reference to the USB endpoint structure
1685 * @usbreq: Reference to the USB request
1686 *
1687 * Return codes:
1688 * 0: Success
1689 * linux error number: Failure
1690 */
1691 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1692 struct usb_request *usbreq)
1693 {
1694 struct pch_udc_ep *ep;
1695 struct pch_udc_request *req;
1696 struct pch_udc_dev *dev;
1697 unsigned long flags;
1698 int ret = -EINVAL;
1699
1700 ep = container_of(usbep, struct pch_udc_ep, ep);
1701 dev = ep->dev;
1702 if (!usbep || !usbreq || (!ep->desc && ep->num))
1703 return ret;
1704 req = container_of(usbreq, struct pch_udc_request, req);
1705 spin_lock_irqsave(&ep->dev->lock, flags);
1706 /* make sure it's still queued on this endpoint */
1707 list_for_each_entry(req, &ep->queue, queue) {
1708 if (&req->req == usbreq) {
1709 pch_udc_ep_set_nak(ep);
1710 if (!list_empty(&req->queue))
1711 complete_req(ep, req, -ECONNRESET);
1712 ret = 0;
1713 break;
1714 }
1715 }
1716 spin_unlock_irqrestore(&ep->dev->lock, flags);
1717 return ret;
1718 }
1719
1720 /**
1721 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1722 * feature
1723 * @usbep: Reference to the USB endpoint structure
1724 * @halt: Specifies whether to set or clear the feature
1725 *
1726 * Return codes:
1727 * 0: Success
1728 * linux error number: Failure
1729 */
1730 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1731 {
1732 struct pch_udc_ep *ep;
1733 struct pch_udc_dev *dev;
1734 unsigned long iflags;
1735 int ret;
1736
1737 if (!usbep)
1738 return -EINVAL;
1739 ep = container_of(usbep, struct pch_udc_ep, ep);
1740 dev = ep->dev;
1741 if (!ep->desc && !ep->num)
1742 return -EINVAL;
1743 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1744 return -ESHUTDOWN;
1745 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1746 if (list_empty(&ep->queue)) {
1747 if (halt) {
1748 if (ep->num == PCH_UDC_EP0)
1749 ep->dev->stall = 1;
1750 pch_udc_ep_set_stall(ep);
1751 pch_udc_enable_ep_interrupts(ep->dev,
1752 PCH_UDC_EPINT(ep->in,
1753 ep->num));
1754 } else {
1755 pch_udc_ep_clear_stall(ep);
1756 }
1757 ret = 0;
1758 } else {
1759 ret = -EAGAIN;
1760 }
1761 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1762 return ret;
1763 }
1764
1765 /**
1766 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1767 * halt feature
1768 * @usbep: Reference to the USB endpoint structure
1769 * @halt: Specifies whether to set or clear the feature
1770 *
1771 * Return codes:
1772 * 0: Success
1773 * linux error number: Failure
1774 */
1775 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1776 {
1777 struct pch_udc_ep *ep;
1778 struct pch_udc_dev *dev;
1779 unsigned long iflags;
1780 int ret;
1781
1782 if (!usbep)
1783 return -EINVAL;
1784 ep = container_of(usbep, struct pch_udc_ep, ep);
1785 dev = ep->dev;
1786 if (!ep->desc && !ep->num)
1787 return -EINVAL;
1788 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1789 return -ESHUTDOWN;
1790 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1791 if (!list_empty(&ep->queue)) {
1792 ret = -EAGAIN;
1793 } else {
1794 if (ep->num == PCH_UDC_EP0)
1795 ep->dev->stall = 1;
1796 pch_udc_ep_set_stall(ep);
1797 pch_udc_enable_ep_interrupts(ep->dev,
1798 PCH_UDC_EPINT(ep->in, ep->num));
1799 ep->dev->prot_stall = 1;
1800 ret = 0;
1801 }
1802 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1803 return ret;
1804 }
1805
1806 /**
1807 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1808 * @usbep: Reference to the USB endpoint structure
1809 */
1810 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1811 {
1812 struct pch_udc_ep *ep;
1813
1814 if (!usbep)
1815 return;
1816
1817 ep = container_of(usbep, struct pch_udc_ep, ep);
1818 if (ep->desc || !ep->num)
1819 pch_udc_ep_fifo_flush(ep, ep->in);
1820 }
1821
1822 static const struct usb_ep_ops pch_udc_ep_ops = {
1823 .enable = pch_udc_pcd_ep_enable,
1824 .disable = pch_udc_pcd_ep_disable,
1825 .alloc_request = pch_udc_alloc_request,
1826 .free_request = pch_udc_free_request,
1827 .queue = pch_udc_pcd_queue,
1828 .dequeue = pch_udc_pcd_dequeue,
1829 .set_halt = pch_udc_pcd_set_halt,
1830 .set_wedge = pch_udc_pcd_set_wedge,
1831 .fifo_status = NULL,
1832 .fifo_flush = pch_udc_pcd_fifo_flush,
1833 };
1834
1835 /**
1836 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1837 * @td_stp: Reference to the SETP buffer structure
1838 */
1839 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
1840 {
1841 static u32 pky_marker;
1842
1843 if (!td_stp)
1844 return;
1845 td_stp->reserved = ++pky_marker;
1846 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
1847 td_stp->status = PCH_UDC_BS_HST_RDY;
1848 }
1849
1850 /**
1851 * pch_udc_start_next_txrequest() - This function starts
1852 * the next transmission requirement
1853 * @ep: Reference to the endpoint structure
1854 */
1855 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
1856 {
1857 struct pch_udc_request *req;
1858 struct pch_udc_data_dma_desc *td_data;
1859
1860 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
1861 return;
1862
1863 if (list_empty(&ep->queue))
1864 return;
1865
1866 /* next request */
1867 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1868 if (req->dma_going)
1869 return;
1870 if (!req->td_data)
1871 return;
1872 pch_udc_wait_ep_stall(ep);
1873 req->dma_going = 1;
1874 pch_udc_ep_set_ddptr(ep, 0);
1875 td_data = req->td_data;
1876 while (1) {
1877 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1878 PCH_UDC_BS_HST_RDY;
1879 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1880 break;
1881 td_data = phys_to_virt(td_data->next);
1882 }
1883 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1884 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
1885 pch_udc_ep_set_pd(ep);
1886 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1887 pch_udc_ep_clear_nak(ep);
1888 }
1889
1890 /**
1891 * pch_udc_complete_transfer() - This function completes a transfer
1892 * @ep: Reference to the endpoint structure
1893 */
1894 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
1895 {
1896 struct pch_udc_request *req;
1897 struct pch_udc_dev *dev = ep->dev;
1898
1899 if (list_empty(&ep->queue))
1900 return;
1901 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1902 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
1903 PCH_UDC_BS_DMA_DONE)
1904 return;
1905 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
1906 PCH_UDC_RTS_SUCC) {
1907 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
1908 "epstatus=0x%08x\n",
1909 (req->td_data_last->status & PCH_UDC_RXTX_STS),
1910 (int)(ep->epsts));
1911 return;
1912 }
1913
1914 req->req.actual = req->req.length;
1915 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1916 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
1917 complete_req(ep, req, 0);
1918 req->dma_going = 0;
1919 if (!list_empty(&ep->queue)) {
1920 pch_udc_wait_ep_stall(ep);
1921 pch_udc_ep_clear_nak(ep);
1922 pch_udc_enable_ep_interrupts(ep->dev,
1923 PCH_UDC_EPINT(ep->in, ep->num));
1924 } else {
1925 pch_udc_disable_ep_interrupts(ep->dev,
1926 PCH_UDC_EPINT(ep->in, ep->num));
1927 }
1928 }
1929
1930 /**
1931 * pch_udc_complete_receiver() - This function completes a receiver
1932 * @ep: Reference to the endpoint structure
1933 */
1934 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
1935 {
1936 struct pch_udc_request *req;
1937 struct pch_udc_dev *dev = ep->dev;
1938 unsigned int count;
1939 struct pch_udc_data_dma_desc *td;
1940 dma_addr_t addr;
1941
1942 if (list_empty(&ep->queue))
1943 return;
1944 /* next request */
1945 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1946 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1947 pch_udc_ep_set_ddptr(ep, 0);
1948 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
1949 PCH_UDC_BS_DMA_DONE)
1950 td = req->td_data_last;
1951 else
1952 td = req->td_data;
1953
1954 while (1) {
1955 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
1956 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
1957 "epstatus=0x%08x\n",
1958 (req->td_data->status & PCH_UDC_RXTX_STS),
1959 (int)(ep->epsts));
1960 return;
1961 }
1962 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
1963 if (td->status | PCH_UDC_DMA_LAST) {
1964 count = td->status & PCH_UDC_RXTX_BYTES;
1965 break;
1966 }
1967 if (td == req->td_data_last) {
1968 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
1969 return;
1970 }
1971 addr = (dma_addr_t)td->next;
1972 td = phys_to_virt(addr);
1973 }
1974 /* on 64k packets the RXBYTES field is zero */
1975 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
1976 count = UDC_DMA_MAXPACKET;
1977 req->td_data->status |= PCH_UDC_DMA_LAST;
1978 td->status |= PCH_UDC_BS_HST_BSY;
1979
1980 req->dma_going = 0;
1981 req->req.actual = count;
1982 complete_req(ep, req, 0);
1983 /* If there is a new/failed requests try that now */
1984 if (!list_empty(&ep->queue)) {
1985 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1986 pch_udc_start_rxrequest(ep, req);
1987 }
1988 }
1989
1990 /**
1991 * pch_udc_svc_data_in() - This function process endpoint interrupts
1992 * for IN endpoints
1993 * @dev: Reference to the device structure
1994 * @ep_num: Endpoint that generated the interrupt
1995 */
1996 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
1997 {
1998 u32 epsts;
1999 struct pch_udc_ep *ep;
2000
2001 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2002 epsts = ep->epsts;
2003 ep->epsts = 0;
2004
2005 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2006 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2007 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2008 return;
2009 if ((epsts & UDC_EPSTS_BNA))
2010 return;
2011 if (epsts & UDC_EPSTS_HE)
2012 return;
2013 if (epsts & UDC_EPSTS_RSS) {
2014 pch_udc_ep_set_stall(ep);
2015 pch_udc_enable_ep_interrupts(ep->dev,
2016 PCH_UDC_EPINT(ep->in, ep->num));
2017 }
2018 if (epsts & UDC_EPSTS_RCS) {
2019 if (!dev->prot_stall) {
2020 pch_udc_ep_clear_stall(ep);
2021 } else {
2022 pch_udc_ep_set_stall(ep);
2023 pch_udc_enable_ep_interrupts(ep->dev,
2024 PCH_UDC_EPINT(ep->in, ep->num));
2025 }
2026 }
2027 if (epsts & UDC_EPSTS_TDC)
2028 pch_udc_complete_transfer(ep);
2029 /* On IN interrupt, provide data if we have any */
2030 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2031 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2032 pch_udc_start_next_txrequest(ep);
2033 }
2034
2035 /**
2036 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2037 * @dev: Reference to the device structure
2038 * @ep_num: Endpoint that generated the interrupt
2039 */
2040 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2041 {
2042 u32 epsts;
2043 struct pch_udc_ep *ep;
2044 struct pch_udc_request *req = NULL;
2045
2046 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2047 epsts = ep->epsts;
2048 ep->epsts = 0;
2049
2050 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2051 /* next request */
2052 req = list_entry(ep->queue.next, struct pch_udc_request,
2053 queue);
2054 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2055 PCH_UDC_BS_DMA_DONE) {
2056 if (!req->dma_going)
2057 pch_udc_start_rxrequest(ep, req);
2058 return;
2059 }
2060 }
2061 if (epsts & UDC_EPSTS_HE)
2062 return;
2063 if (epsts & UDC_EPSTS_RSS) {
2064 pch_udc_ep_set_stall(ep);
2065 pch_udc_enable_ep_interrupts(ep->dev,
2066 PCH_UDC_EPINT(ep->in, ep->num));
2067 }
2068 if (epsts & UDC_EPSTS_RCS) {
2069 if (!dev->prot_stall) {
2070 pch_udc_ep_clear_stall(ep);
2071 } else {
2072 pch_udc_ep_set_stall(ep);
2073 pch_udc_enable_ep_interrupts(ep->dev,
2074 PCH_UDC_EPINT(ep->in, ep->num));
2075 }
2076 }
2077 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2078 UDC_EPSTS_OUT_DATA) {
2079 if (ep->dev->prot_stall == 1) {
2080 pch_udc_ep_set_stall(ep);
2081 pch_udc_enable_ep_interrupts(ep->dev,
2082 PCH_UDC_EPINT(ep->in, ep->num));
2083 } else {
2084 pch_udc_complete_receiver(ep);
2085 }
2086 }
2087 if (list_empty(&ep->queue))
2088 pch_udc_set_dma(dev, DMA_DIR_RX);
2089 }
2090
2091 /**
2092 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2093 * @dev: Reference to the device structure
2094 */
2095 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2096 {
2097 u32 epsts;
2098 struct pch_udc_ep *ep;
2099 struct pch_udc_ep *ep_out;
2100
2101 ep = &dev->ep[UDC_EP0IN_IDX];
2102 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2103 epsts = ep->epsts;
2104 ep->epsts = 0;
2105
2106 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2107 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2108 UDC_EPSTS_XFERDONE)))
2109 return;
2110 if ((epsts & UDC_EPSTS_BNA))
2111 return;
2112 if (epsts & UDC_EPSTS_HE)
2113 return;
2114 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2115 pch_udc_complete_transfer(ep);
2116 pch_udc_clear_dma(dev, DMA_DIR_RX);
2117 ep_out->td_data->status = (ep_out->td_data->status &
2118 ~PCH_UDC_BUFF_STS) |
2119 PCH_UDC_BS_HST_RDY;
2120 pch_udc_ep_clear_nak(ep_out);
2121 pch_udc_set_dma(dev, DMA_DIR_RX);
2122 pch_udc_ep_set_rrdy(ep_out);
2123 }
2124 /* On IN interrupt, provide data if we have any */
2125 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2126 !(epsts & UDC_EPSTS_TXEMPTY))
2127 pch_udc_start_next_txrequest(ep);
2128 }
2129
2130 /**
2131 * pch_udc_svc_control_out() - Routine that handle Control
2132 * OUT endpoint interrupts
2133 * @dev: Reference to the device structure
2134 */
2135 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2136 {
2137 u32 stat;
2138 int setup_supported;
2139 struct pch_udc_ep *ep;
2140
2141 ep = &dev->ep[UDC_EP0OUT_IDX];
2142 stat = ep->epsts;
2143 ep->epsts = 0;
2144
2145 /* If setup data */
2146 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2147 UDC_EPSTS_OUT_SETUP) {
2148 dev->stall = 0;
2149 dev->ep[UDC_EP0IN_IDX].halted = 0;
2150 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2151 dev->setup_data = ep->td_stp->request;
2152 pch_udc_init_setup_buff(ep->td_stp);
2153 pch_udc_clear_dma(dev, DMA_DIR_RX);
2154 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2155 dev->ep[UDC_EP0IN_IDX].in);
2156 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2157 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2158 else /* OUT */
2159 dev->gadget.ep0 = &ep->ep;
2160 spin_unlock(&dev->lock);
2161 /* If Mass storage Reset */
2162 if ((dev->setup_data.bRequestType == 0x21) &&
2163 (dev->setup_data.bRequest == 0xFF))
2164 dev->prot_stall = 0;
2165 /* call gadget with setup data received */
2166 setup_supported = dev->driver->setup(&dev->gadget,
2167 &dev->setup_data);
2168 spin_lock(&dev->lock);
2169
2170 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2171 ep->td_data->status = (ep->td_data->status &
2172 ~PCH_UDC_BUFF_STS) |
2173 PCH_UDC_BS_HST_RDY;
2174 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2175 }
2176 /* ep0 in returns data on IN phase */
2177 if (setup_supported >= 0 && setup_supported <
2178 UDC_EP0IN_MAX_PKT_SIZE) {
2179 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2180 /* Gadget would have queued a request when
2181 * we called the setup */
2182 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2183 pch_udc_set_dma(dev, DMA_DIR_RX);
2184 pch_udc_ep_clear_nak(ep);
2185 }
2186 } else if (setup_supported < 0) {
2187 /* if unsupported request, then stall */
2188 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2189 pch_udc_enable_ep_interrupts(ep->dev,
2190 PCH_UDC_EPINT(ep->in, ep->num));
2191 dev->stall = 0;
2192 pch_udc_set_dma(dev, DMA_DIR_RX);
2193 } else {
2194 dev->waiting_zlp_ack = 1;
2195 }
2196 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2197 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2198 pch_udc_clear_dma(dev, DMA_DIR_RX);
2199 pch_udc_ep_set_ddptr(ep, 0);
2200 if (!list_empty(&ep->queue)) {
2201 ep->epsts = stat;
2202 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2203 }
2204 pch_udc_set_dma(dev, DMA_DIR_RX);
2205 }
2206 pch_udc_ep_set_rrdy(ep);
2207 }
2208
2209
2210 /**
2211 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2212 * and clears NAK status
2213 * @dev: Reference to the device structure
2214 * @ep_num: End point number
2215 */
2216 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2217 {
2218 struct pch_udc_ep *ep;
2219 struct pch_udc_request *req;
2220
2221 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2222 if (!list_empty(&ep->queue)) {
2223 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2224 pch_udc_enable_ep_interrupts(ep->dev,
2225 PCH_UDC_EPINT(ep->in, ep->num));
2226 pch_udc_ep_clear_nak(ep);
2227 }
2228 }
2229
2230 /**
2231 * pch_udc_read_all_epstatus() - This function read all endpoint status
2232 * @dev: Reference to the device structure
2233 * @ep_intr: Status of endpoint interrupt
2234 */
2235 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2236 {
2237 int i;
2238 struct pch_udc_ep *ep;
2239
2240 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2241 /* IN */
2242 if (ep_intr & (0x1 << i)) {
2243 ep = &dev->ep[UDC_EPIN_IDX(i)];
2244 ep->epsts = pch_udc_read_ep_status(ep);
2245 pch_udc_clear_ep_status(ep, ep->epsts);
2246 }
2247 /* OUT */
2248 if (ep_intr & (0x10000 << i)) {
2249 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2250 ep->epsts = pch_udc_read_ep_status(ep);
2251 pch_udc_clear_ep_status(ep, ep->epsts);
2252 }
2253 }
2254 }
2255
2256 /**
2257 * pch_udc_activate_control_ep() - This function enables the control endpoints
2258 * for traffic after a reset
2259 * @dev: Reference to the device structure
2260 */
2261 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2262 {
2263 struct pch_udc_ep *ep;
2264 u32 val;
2265
2266 /* Setup the IN endpoint */
2267 ep = &dev->ep[UDC_EP0IN_IDX];
2268 pch_udc_clear_ep_control(ep);
2269 pch_udc_ep_fifo_flush(ep, ep->in);
2270 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2271 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2272 /* Initialize the IN EP Descriptor */
2273 ep->td_data = NULL;
2274 ep->td_stp = NULL;
2275 ep->td_data_phys = 0;
2276 ep->td_stp_phys = 0;
2277
2278 /* Setup the OUT endpoint */
2279 ep = &dev->ep[UDC_EP0OUT_IDX];
2280 pch_udc_clear_ep_control(ep);
2281 pch_udc_ep_fifo_flush(ep, ep->in);
2282 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2283 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2284 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2285 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2286
2287 /* Initialize the SETUP buffer */
2288 pch_udc_init_setup_buff(ep->td_stp);
2289 /* Write the pointer address of dma descriptor */
2290 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2291 /* Write the pointer address of Setup descriptor */
2292 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2293
2294 /* Initialize the dma descriptor */
2295 ep->td_data->status = PCH_UDC_DMA_LAST;
2296 ep->td_data->dataptr = dev->dma_addr;
2297 ep->td_data->next = ep->td_data_phys;
2298
2299 pch_udc_ep_clear_nak(ep);
2300 }
2301
2302
2303 /**
2304 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2305 * @dev: Reference to driver structure
2306 */
2307 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2308 {
2309 struct pch_udc_ep *ep;
2310 int i;
2311
2312 pch_udc_clear_dma(dev, DMA_DIR_TX);
2313 pch_udc_clear_dma(dev, DMA_DIR_RX);
2314 /* Mask all endpoint interrupts */
2315 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2316 /* clear all endpoint interrupts */
2317 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2318
2319 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2320 ep = &dev->ep[i];
2321 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2322 pch_udc_clear_ep_control(ep);
2323 pch_udc_ep_set_ddptr(ep, 0);
2324 pch_udc_write_csr(ep->dev, 0x00, i);
2325 }
2326 dev->stall = 0;
2327 dev->prot_stall = 0;
2328 dev->waiting_zlp_ack = 0;
2329 dev->set_cfg_not_acked = 0;
2330
2331 /* disable ep to empty req queue. Skip the control EP's */
2332 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2333 ep = &dev->ep[i];
2334 pch_udc_ep_set_nak(ep);
2335 pch_udc_ep_fifo_flush(ep, ep->in);
2336 /* Complete request queue */
2337 empty_req_queue(ep);
2338 }
2339 if (dev->driver && dev->driver->disconnect)
2340 dev->driver->disconnect(&dev->gadget);
2341 }
2342
2343 /**
2344 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2345 * done interrupt
2346 * @dev: Reference to driver structure
2347 */
2348 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2349 {
2350 u32 dev_stat, dev_speed;
2351 u32 speed = USB_SPEED_FULL;
2352
2353 dev_stat = pch_udc_read_device_status(dev);
2354 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2355 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2356 switch (dev_speed) {
2357 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2358 speed = USB_SPEED_HIGH;
2359 break;
2360 case UDC_DEVSTS_ENUM_SPEED_FULL:
2361 speed = USB_SPEED_FULL;
2362 break;
2363 case UDC_DEVSTS_ENUM_SPEED_LOW:
2364 speed = USB_SPEED_LOW;
2365 break;
2366 default:
2367 BUG();
2368 }
2369 dev->gadget.speed = speed;
2370 pch_udc_activate_control_ep(dev);
2371 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2372 pch_udc_set_dma(dev, DMA_DIR_TX);
2373 pch_udc_set_dma(dev, DMA_DIR_RX);
2374 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2375 }
2376
2377 /**
2378 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2379 * interrupt
2380 * @dev: Reference to driver structure
2381 */
2382 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2383 {
2384 u32 reg, dev_stat = 0;
2385 int i, ret;
2386
2387 dev_stat = pch_udc_read_device_status(dev);
2388 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2389 UDC_DEVSTS_INTF_SHIFT;
2390 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2391 UDC_DEVSTS_ALT_SHIFT;
2392 dev->set_cfg_not_acked = 1;
2393 /* Construct the usb request for gadget driver and inform it */
2394 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2395 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2396 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2397 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2398 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2399 /* programm the Endpoint Cfg registers */
2400 /* Only one end point cfg register */
2401 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2402 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2403 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2404 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2405 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2406 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2407 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2408 /* clear stall bits */
2409 pch_udc_ep_clear_stall(&(dev->ep[i]));
2410 dev->ep[i].halted = 0;
2411 }
2412 dev->stall = 0;
2413 spin_unlock(&dev->lock);
2414 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2415 spin_lock(&dev->lock);
2416 }
2417
2418 /**
2419 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2420 * interrupt
2421 * @dev: Reference to driver structure
2422 */
2423 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2424 {
2425 int i, ret;
2426 u32 reg, dev_stat = 0;
2427
2428 dev_stat = pch_udc_read_device_status(dev);
2429 dev->set_cfg_not_acked = 1;
2430 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2431 UDC_DEVSTS_CFG_SHIFT;
2432 /* make usb request for gadget driver */
2433 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2434 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2435 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2436 /* program the NE registers */
2437 /* Only one end point cfg register */
2438 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2439 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2440 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2441 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2442 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2443 /* clear stall bits */
2444 pch_udc_ep_clear_stall(&(dev->ep[i]));
2445 dev->ep[i].halted = 0;
2446 }
2447 dev->stall = 0;
2448
2449 /* call gadget zero with setup data received */
2450 spin_unlock(&dev->lock);
2451 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2452 spin_lock(&dev->lock);
2453 }
2454
2455 /**
2456 * pch_udc_dev_isr() - This function services device interrupts
2457 * by invoking appropriate routines.
2458 * @dev: Reference to the device structure
2459 * @dev_intr: The Device interrupt status.
2460 */
2461 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2462 {
2463 /* USB Reset Interrupt */
2464 if (dev_intr & UDC_DEVINT_UR)
2465 pch_udc_svc_ur_interrupt(dev);
2466 /* Enumeration Done Interrupt */
2467 if (dev_intr & UDC_DEVINT_ENUM)
2468 pch_udc_svc_enum_interrupt(dev);
2469 /* Set Interface Interrupt */
2470 if (dev_intr & UDC_DEVINT_SI)
2471 pch_udc_svc_intf_interrupt(dev);
2472 /* Set Config Interrupt */
2473 if (dev_intr & UDC_DEVINT_SC)
2474 pch_udc_svc_cfg_interrupt(dev);
2475 /* USB Suspend interrupt */
2476 if (dev_intr & UDC_DEVINT_US)
2477 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2478 /* Clear the SOF interrupt, if enabled */
2479 if (dev_intr & UDC_DEVINT_SOF)
2480 dev_dbg(&dev->pdev->dev, "SOF\n");
2481 /* ES interrupt, IDLE > 3ms on the USB */
2482 if (dev_intr & UDC_DEVINT_ES)
2483 dev_dbg(&dev->pdev->dev, "ES\n");
2484 /* RWKP interrupt */
2485 if (dev_intr & UDC_DEVINT_RWKP)
2486 dev_dbg(&dev->pdev->dev, "RWKP\n");
2487 }
2488
2489 /**
2490 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2491 * @irq: Interrupt request number
2492 * @dev: Reference to the device structure
2493 */
2494 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2495 {
2496 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2497 u32 dev_intr, ep_intr;
2498 int i;
2499
2500 dev_intr = pch_udc_read_device_interrupts(dev);
2501 ep_intr = pch_udc_read_ep_interrupts(dev);
2502
2503 if (dev_intr)
2504 /* Clear device interrupts */
2505 pch_udc_write_device_interrupts(dev, dev_intr);
2506 if (ep_intr)
2507 /* Clear ep interrupts */
2508 pch_udc_write_ep_interrupts(dev, ep_intr);
2509 if (!dev_intr && !ep_intr)
2510 return IRQ_NONE;
2511 spin_lock(&dev->lock);
2512 if (dev_intr)
2513 pch_udc_dev_isr(dev, dev_intr);
2514 if (ep_intr) {
2515 pch_udc_read_all_epstatus(dev, ep_intr);
2516 /* Process Control In interrupts, if present */
2517 if (ep_intr & UDC_EPINT_IN_EP0) {
2518 pch_udc_svc_control_in(dev);
2519 pch_udc_postsvc_epinters(dev, 0);
2520 }
2521 /* Process Control Out interrupts, if present */
2522 if (ep_intr & UDC_EPINT_OUT_EP0)
2523 pch_udc_svc_control_out(dev);
2524 /* Process data in end point interrupts */
2525 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2526 if (ep_intr & (1 << i)) {
2527 pch_udc_svc_data_in(dev, i);
2528 pch_udc_postsvc_epinters(dev, i);
2529 }
2530 }
2531 /* Process data out end point interrupts */
2532 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2533 PCH_UDC_USED_EP_NUM); i++)
2534 if (ep_intr & (1 << i))
2535 pch_udc_svc_data_out(dev, i -
2536 UDC_EPINT_OUT_SHIFT);
2537 }
2538 spin_unlock(&dev->lock);
2539 return IRQ_HANDLED;
2540 }
2541
2542 /**
2543 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2544 * @dev: Reference to the device structure
2545 */
2546 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2547 {
2548 /* enable ep0 interrupts */
2549 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2550 UDC_EPINT_OUT_EP0);
2551 /* enable device interrupts */
2552 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2553 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2554 UDC_DEVINT_SI | UDC_DEVINT_SC);
2555 }
2556
2557 /**
2558 * gadget_release() - Free the gadget driver private data
2559 * @pdev reference to struct pci_dev
2560 */
2561 static void gadget_release(struct device *pdev)
2562 {
2563 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2564
2565 kfree(dev);
2566 }
2567
2568 /**
2569 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2570 * @dev: Reference to the driver structure
2571 */
2572 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2573 {
2574 const char *const ep_string[] = {
2575 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2576 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2577 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2578 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2579 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2580 "ep15in", "ep15out",
2581 };
2582 int i;
2583
2584 dev->gadget.speed = USB_SPEED_UNKNOWN;
2585 INIT_LIST_HEAD(&dev->gadget.ep_list);
2586
2587 /* Initialize the endpoints structures */
2588 memset(dev->ep, 0, sizeof dev->ep);
2589 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2590 struct pch_udc_ep *ep = &dev->ep[i];
2591 ep->dev = dev;
2592 ep->halted = 1;
2593 ep->num = i / 2;
2594 ep->in = ~i & 1;
2595 ep->ep.name = ep_string[i];
2596 ep->ep.ops = &pch_udc_ep_ops;
2597 if (ep->in)
2598 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2599 else
2600 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2601 UDC_EP_REG_SHIFT;
2602 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2603 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2604 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2605 INIT_LIST_HEAD(&ep->queue);
2606 }
2607 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2608 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2609
2610 /* remove ep0 in and out from the list. They have own pointer */
2611 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2612 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2613
2614 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2615 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2616 }
2617
2618 /**
2619 * pch_udc_pcd_init() - This API initializes the driver structure
2620 * @dev: Reference to the driver structure
2621 *
2622 * Return codes:
2623 * 0: Success
2624 */
2625 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2626 {
2627 pch_udc_init(dev);
2628 pch_udc_pcd_reinit(dev);
2629 return 0;
2630 }
2631
2632 /**
2633 * init_dma_pools() - create dma pools during initialization
2634 * @pdev: reference to struct pci_dev
2635 */
2636 static int init_dma_pools(struct pch_udc_dev *dev)
2637 {
2638 struct pch_udc_stp_dma_desc *td_stp;
2639 struct pch_udc_data_dma_desc *td_data;
2640
2641 /* DMA setup */
2642 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2643 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2644 if (!dev->data_requests) {
2645 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2646 __func__);
2647 return -ENOMEM;
2648 }
2649
2650 /* dma desc for setup data */
2651 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2652 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2653 if (!dev->stp_requests) {
2654 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2655 __func__);
2656 return -ENOMEM;
2657 }
2658 /* setup */
2659 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2660 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2661 if (!td_stp) {
2662 dev_err(&dev->pdev->dev,
2663 "%s: can't allocate setup dma descriptor\n", __func__);
2664 return -ENOMEM;
2665 }
2666 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2667
2668 /* data: 0 packets !? */
2669 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2670 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2671 if (!td_data) {
2672 dev_err(&dev->pdev->dev,
2673 "%s: can't allocate data dma descriptor\n", __func__);
2674 return -ENOMEM;
2675 }
2676 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2677 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2678 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2679 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2680 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2681
2682 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2683 if (!dev->ep0out_buf)
2684 return -ENOMEM;
2685 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2686 UDC_EP0OUT_BUFF_SIZE * 4,
2687 DMA_FROM_DEVICE);
2688 return 0;
2689 }
2690
2691 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
2692 int (*bind)(struct usb_gadget *))
2693 {
2694 struct pch_udc_dev *dev = pch_udc;
2695 int retval;
2696
2697 if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind ||
2698 !driver->setup || !driver->unbind || !driver->disconnect) {
2699 dev_err(&dev->pdev->dev,
2700 "%s: invalid driver parameter\n", __func__);
2701 return -EINVAL;
2702 }
2703
2704 if (!dev)
2705 return -ENODEV;
2706
2707 if (dev->driver) {
2708 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2709 return -EBUSY;
2710 }
2711 driver->driver.bus = NULL;
2712 dev->driver = driver;
2713 dev->gadget.dev.driver = &driver->driver;
2714
2715 /* Invoke the bind routine of the gadget driver */
2716 retval = bind(&dev->gadget);
2717
2718 if (retval) {
2719 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2720 __func__, driver->driver.name, retval);
2721 dev->driver = NULL;
2722 dev->gadget.dev.driver = NULL;
2723 return retval;
2724 }
2725 /* get ready for ep0 traffic */
2726 pch_udc_setup_ep0(dev);
2727
2728 /* clear SD */
2729 pch_udc_clear_disconnect(dev);
2730
2731 dev->connected = 1;
2732 return 0;
2733 }
2734 EXPORT_SYMBOL(usb_gadget_probe_driver);
2735
2736 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2737 {
2738 struct pch_udc_dev *dev = pch_udc;
2739
2740 if (!dev)
2741 return -ENODEV;
2742
2743 if (!driver || (driver != dev->driver)) {
2744 dev_err(&dev->pdev->dev,
2745 "%s: invalid driver parameter\n", __func__);
2746 return -EINVAL;
2747 }
2748
2749 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2750
2751 /* Assures that there are no pending requests with this driver */
2752 driver->disconnect(&dev->gadget);
2753 driver->unbind(&dev->gadget);
2754 dev->gadget.dev.driver = NULL;
2755 dev->driver = NULL;
2756 dev->connected = 0;
2757
2758 /* set SD */
2759 pch_udc_set_disconnect(dev);
2760 return 0;
2761 }
2762 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2763
2764 static void pch_udc_shutdown(struct pci_dev *pdev)
2765 {
2766 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2767
2768 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2769 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2770
2771 /* disable the pullup so the host will think we're gone */
2772 pch_udc_set_disconnect(dev);
2773 }
2774
2775 static void pch_udc_remove(struct pci_dev *pdev)
2776 {
2777 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2778
2779 /* gadget driver must not be registered */
2780 if (dev->driver)
2781 dev_err(&pdev->dev,
2782 "%s: gadget driver still bound!!!\n", __func__);
2783 /* dma pool cleanup */
2784 if (dev->data_requests)
2785 pci_pool_destroy(dev->data_requests);
2786
2787 if (dev->stp_requests) {
2788 /* cleanup DMA desc's for ep0in */
2789 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
2790 pci_pool_free(dev->stp_requests,
2791 dev->ep[UDC_EP0OUT_IDX].td_stp,
2792 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2793 }
2794 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
2795 pci_pool_free(dev->stp_requests,
2796 dev->ep[UDC_EP0OUT_IDX].td_data,
2797 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2798 }
2799 pci_pool_destroy(dev->stp_requests);
2800 }
2801
2802 if (dev->dma_addr)
2803 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
2804 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
2805 kfree(dev->ep0out_buf);
2806
2807 pch_udc_exit(dev);
2808
2809 if (dev->irq_registered)
2810 free_irq(pdev->irq, dev);
2811 if (dev->base_addr)
2812 iounmap(dev->base_addr);
2813 if (dev->mem_region)
2814 release_mem_region(dev->phys_addr,
2815 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
2816 if (dev->active)
2817 pci_disable_device(pdev);
2818 if (dev->registered)
2819 device_unregister(&dev->gadget.dev);
2820 kfree(dev);
2821 pci_set_drvdata(pdev, NULL);
2822 }
2823
2824 #ifdef CONFIG_PM
2825 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
2826 {
2827 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2828
2829 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2830 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2831
2832 pci_disable_device(pdev);
2833 pci_enable_wake(pdev, PCI_D3hot, 0);
2834
2835 if (pci_save_state(pdev)) {
2836 dev_err(&pdev->dev,
2837 "%s: could not save PCI config state\n", __func__);
2838 return -ENOMEM;
2839 }
2840 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2841 return 0;
2842 }
2843
2844 static int pch_udc_resume(struct pci_dev *pdev)
2845 {
2846 int ret;
2847
2848 pci_set_power_state(pdev, PCI_D0);
2849 pci_restore_state(pdev);
2850 ret = pci_enable_device(pdev);
2851 if (ret) {
2852 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
2853 return ret;
2854 }
2855 pci_enable_wake(pdev, PCI_D3hot, 0);
2856 return 0;
2857 }
2858 #else
2859 #define pch_udc_suspend NULL
2860 #define pch_udc_resume NULL
2861 #endif /* CONFIG_PM */
2862
2863 static int pch_udc_probe(struct pci_dev *pdev,
2864 const struct pci_device_id *id)
2865 {
2866 unsigned long resource;
2867 unsigned long len;
2868 int retval;
2869 struct pch_udc_dev *dev;
2870
2871 /* one udc only */
2872 if (pch_udc) {
2873 pr_err("%s: already probed\n", __func__);
2874 return -EBUSY;
2875 }
2876 /* init */
2877 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2878 if (!dev) {
2879 pr_err("%s: no memory for device structure\n", __func__);
2880 return -ENOMEM;
2881 }
2882 /* pci setup */
2883 if (pci_enable_device(pdev) < 0) {
2884 kfree(dev);
2885 pr_err("%s: pci_enable_device failed\n", __func__);
2886 return -ENODEV;
2887 }
2888 dev->active = 1;
2889 pci_set_drvdata(pdev, dev);
2890
2891 /* PCI resource allocation */
2892 resource = pci_resource_start(pdev, 1);
2893 len = pci_resource_len(pdev, 1);
2894
2895 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
2896 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
2897 retval = -EBUSY;
2898 goto finished;
2899 }
2900 dev->phys_addr = resource;
2901 dev->mem_region = 1;
2902
2903 dev->base_addr = ioremap_nocache(resource, len);
2904 if (!dev->base_addr) {
2905 pr_err("%s: device memory cannot be mapped\n", __func__);
2906 retval = -ENOMEM;
2907 goto finished;
2908 }
2909 if (!pdev->irq) {
2910 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
2911 retval = -ENODEV;
2912 goto finished;
2913 }
2914 pch_udc = dev;
2915 /* initialize the hardware */
2916 if (pch_udc_pcd_init(dev))
2917 goto finished;
2918 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
2919 dev)) {
2920 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
2921 pdev->irq);
2922 retval = -ENODEV;
2923 goto finished;
2924 }
2925 dev->irq = pdev->irq;
2926 dev->irq_registered = 1;
2927
2928 pci_set_master(pdev);
2929 pci_try_set_mwi(pdev);
2930
2931 /* device struct setup */
2932 spin_lock_init(&dev->lock);
2933 dev->pdev = pdev;
2934 dev->gadget.ops = &pch_udc_ops;
2935
2936 retval = init_dma_pools(dev);
2937 if (retval)
2938 goto finished;
2939
2940 dev_set_name(&dev->gadget.dev, "gadget");
2941 dev->gadget.dev.parent = &pdev->dev;
2942 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2943 dev->gadget.dev.release = gadget_release;
2944 dev->gadget.name = KBUILD_MODNAME;
2945 dev->gadget.is_dualspeed = 1;
2946
2947 retval = device_register(&dev->gadget.dev);
2948 if (retval)
2949 goto finished;
2950 dev->registered = 1;
2951
2952 /* Put the device in disconnected state till a driver is bound */
2953 pch_udc_set_disconnect(dev);
2954 return 0;
2955
2956 finished:
2957 pch_udc_remove(pdev);
2958 return retval;
2959 }
2960
2961 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
2962 {
2963 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
2964 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2965 .class_mask = 0xffffffff,
2966 },
2967 {
2968 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
2969 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
2970 .class_mask = 0xffffffff,
2971 },
2972 { 0 },
2973 };
2974
2975 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
2976
2977
2978 static struct pci_driver pch_udc_driver = {
2979 .name = KBUILD_MODNAME,
2980 .id_table = pch_udc_pcidev_id,
2981 .probe = pch_udc_probe,
2982 .remove = pch_udc_remove,
2983 .suspend = pch_udc_suspend,
2984 .resume = pch_udc_resume,
2985 .shutdown = pch_udc_shutdown,
2986 };
2987
2988 static int __init pch_udc_pci_init(void)
2989 {
2990 return pci_register_driver(&pch_udc_driver);
2991 }
2992 module_init(pch_udc_pci_init);
2993
2994 static void __exit pch_udc_pci_exit(void)
2995 {
2996 pci_unregister_driver(&pch_udc_driver);
2997 }
2998 module_exit(pch_udc_pci_exit);
2999
3000 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3001 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
3002 MODULE_LICENSE("GPL");
Mirror of the linux-mips.org kernel tree