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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / video / omap2 / dss / venc.c
blob8e35a5bae429c8a858e0c6acf5ac3bca92c2ca79
1 /*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "VENC"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36
37 #include <plat/display.h>
38 #include <plat/cpu.h>
39
40 #include "dss.h"
41
42 /* Venc registers */
43 #define VENC_REV_ID 0x00
44 #define VENC_STATUS 0x04
45 #define VENC_F_CONTROL 0x08
46 #define VENC_VIDOUT_CTRL 0x10
47 #define VENC_SYNC_CTRL 0x14
48 #define VENC_LLEN 0x1C
49 #define VENC_FLENS 0x20
50 #define VENC_HFLTR_CTRL 0x24
51 #define VENC_CC_CARR_WSS_CARR 0x28
52 #define VENC_C_PHASE 0x2C
53 #define VENC_GAIN_U 0x30
54 #define VENC_GAIN_V 0x34
55 #define VENC_GAIN_Y 0x38
56 #define VENC_BLACK_LEVEL 0x3C
57 #define VENC_BLANK_LEVEL 0x40
58 #define VENC_X_COLOR 0x44
59 #define VENC_M_CONTROL 0x48
60 #define VENC_BSTAMP_WSS_DATA 0x4C
61 #define VENC_S_CARR 0x50
62 #define VENC_LINE21 0x54
63 #define VENC_LN_SEL 0x58
64 #define VENC_L21__WC_CTL 0x5C
65 #define VENC_HTRIGGER_VTRIGGER 0x60
66 #define VENC_SAVID__EAVID 0x64
67 #define VENC_FLEN__FAL 0x68
68 #define VENC_LAL__PHASE_RESET 0x6C
69 #define VENC_HS_INT_START_STOP_X 0x70
70 #define VENC_HS_EXT_START_STOP_X 0x74
71 #define VENC_VS_INT_START_X 0x78
72 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
73 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
74 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
75 #define VENC_VS_EXT_STOP_Y 0x88
76 #define VENC_AVID_START_STOP_X 0x90
77 #define VENC_AVID_START_STOP_Y 0x94
78 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
79 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
80 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
81 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
82 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
83 #define VENC_GEN_CTRL 0xB8
84 #define VENC_OUTPUT_CONTROL 0xC4
85 #define VENC_OUTPUT_TEST 0xC8
86 #define VENC_DAC_B__DAC_C 0xC8
87
88 struct venc_config {
89 u32 f_control;
90 u32 vidout_ctrl;
91 u32 sync_ctrl;
92 u32 llen;
93 u32 flens;
94 u32 hfltr_ctrl;
95 u32 cc_carr_wss_carr;
96 u32 c_phase;
97 u32 gain_u;
98 u32 gain_v;
99 u32 gain_y;
100 u32 black_level;
101 u32 blank_level;
102 u32 x_color;
103 u32 m_control;
104 u32 bstamp_wss_data;
105 u32 s_carr;
106 u32 line21;
107 u32 ln_sel;
108 u32 l21__wc_ctl;
109 u32 htrigger_vtrigger;
110 u32 savid__eavid;
111 u32 flen__fal;
112 u32 lal__phase_reset;
113 u32 hs_int_start_stop_x;
114 u32 hs_ext_start_stop_x;
115 u32 vs_int_start_x;
116 u32 vs_int_stop_x__vs_int_start_y;
117 u32 vs_int_stop_y__vs_ext_start_x;
118 u32 vs_ext_stop_x__vs_ext_start_y;
119 u32 vs_ext_stop_y;
120 u32 avid_start_stop_x;
121 u32 avid_start_stop_y;
122 u32 fid_int_start_x__fid_int_start_y;
123 u32 fid_int_offset_y__fid_ext_start_x;
124 u32 fid_ext_start_y__fid_ext_offset_y;
125 u32 tvdetgp_int_start_stop_x;
126 u32 tvdetgp_int_start_stop_y;
127 u32 gen_ctrl;
128 };
129
130 /* from TRM */
131 static const struct venc_config venc_config_pal_trm = {
132 .f_control = 0,
133 .vidout_ctrl = 1,
134 .sync_ctrl = 0x40,
135 .llen = 0x35F, /* 863 */
136 .flens = 0x270, /* 624 */
137 .hfltr_ctrl = 0,
138 .cc_carr_wss_carr = 0x2F7225ED,
139 .c_phase = 0,
140 .gain_u = 0x111,
141 .gain_v = 0x181,
142 .gain_y = 0x140,
143 .black_level = 0x3B,
144 .blank_level = 0x3B,
145 .x_color = 0x7,
146 .m_control = 0x2,
147 .bstamp_wss_data = 0x3F,
148 .s_carr = 0x2A098ACB,
149 .line21 = 0,
150 .ln_sel = 0x01290015,
151 .l21__wc_ctl = 0x0000F603,
152 .htrigger_vtrigger = 0,
153
154 .savid__eavid = 0x06A70108,
155 .flen__fal = 0x00180270,
156 .lal__phase_reset = 0x00040135,
157 .hs_int_start_stop_x = 0x00880358,
158 .hs_ext_start_stop_x = 0x000F035F,
159 .vs_int_start_x = 0x01A70000,
160 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
161 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
162 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
163 .vs_ext_stop_y = 0x00000025,
164 .avid_start_stop_x = 0x03530083,
165 .avid_start_stop_y = 0x026C002E,
166 .fid_int_start_x__fid_int_start_y = 0x0001008A,
167 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
168 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
169
170 .tvdetgp_int_start_stop_x = 0x00140001,
171 .tvdetgp_int_start_stop_y = 0x00010001,
172 .gen_ctrl = 0x00FF0000,
173 };
174
175 /* from TRM */
176 static const struct venc_config venc_config_ntsc_trm = {
177 .f_control = 0,
178 .vidout_ctrl = 1,
179 .sync_ctrl = 0x8040,
180 .llen = 0x359,
181 .flens = 0x20C,
182 .hfltr_ctrl = 0,
183 .cc_carr_wss_carr = 0x043F2631,
184 .c_phase = 0,
185 .gain_u = 0x102,
186 .gain_v = 0x16C,
187 .gain_y = 0x12F,
188 .black_level = 0x43,
189 .blank_level = 0x38,
190 .x_color = 0x7,
191 .m_control = 0x1,
192 .bstamp_wss_data = 0x38,
193 .s_carr = 0x21F07C1F,
194 .line21 = 0,
195 .ln_sel = 0x01310011,
196 .l21__wc_ctl = 0x0000F003,
197 .htrigger_vtrigger = 0,
198
199 .savid__eavid = 0x069300F4,
200 .flen__fal = 0x0016020C,
201 .lal__phase_reset = 0x00060107,
202 .hs_int_start_stop_x = 0x008E0350,
203 .hs_ext_start_stop_x = 0x000F0359,
204 .vs_int_start_x = 0x01A00000,
205 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
206 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
207 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
208 .vs_ext_stop_y = 0x00000006,
209 .avid_start_stop_x = 0x03480078,
210 .avid_start_stop_y = 0x02060024,
211 .fid_int_start_x__fid_int_start_y = 0x0001008A,
212 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
213 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
214
215 .tvdetgp_int_start_stop_x = 0x00140001,
216 .tvdetgp_int_start_stop_y = 0x00010001,
217 .gen_ctrl = 0x00F90000,
218 };
219
220 static const struct venc_config venc_config_pal_bdghi = {
221 .f_control = 0,
222 .vidout_ctrl = 0,
223 .sync_ctrl = 0,
224 .hfltr_ctrl = 0,
225 .x_color = 0,
226 .line21 = 0,
227 .ln_sel = 21,
228 .htrigger_vtrigger = 0,
229 .tvdetgp_int_start_stop_x = 0x00140001,
230 .tvdetgp_int_start_stop_y = 0x00010001,
231 .gen_ctrl = 0x00FB0000,
232
233 .llen = 864-1,
234 .flens = 625-1,
235 .cc_carr_wss_carr = 0x2F7625ED,
236 .c_phase = 0xDF,
237 .gain_u = 0x111,
238 .gain_v = 0x181,
239 .gain_y = 0x140,
240 .black_level = 0x3e,
241 .blank_level = 0x3e,
242 .m_control = 0<<2 | 1<<1,
243 .bstamp_wss_data = 0x42,
244 .s_carr = 0x2a098acb,
245 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
246 .savid__eavid = 0x06A70108,
247 .flen__fal = 23<<16 | 624<<0,
248 .lal__phase_reset = 2<<17 | 310<<0,
249 .hs_int_start_stop_x = 0x00920358,
250 .hs_ext_start_stop_x = 0x000F035F,
251 .vs_int_start_x = 0x1a7<<16,
252 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
253 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
254 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
255 .vs_ext_stop_y = 0x05,
256 .avid_start_stop_x = 0x03530082,
257 .avid_start_stop_y = 0x0270002E,
258 .fid_int_start_x__fid_int_start_y = 0x0005008A,
259 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
260 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
261 };
262
263 const struct omap_video_timings omap_dss_pal_timings = {
264 .x_res = 720,
265 .y_res = 574,
266 .pixel_clock = 13500,
267 .hsw = 64,
268 .hfp = 12,
269 .hbp = 68,
270 .vsw = 5,
271 .vfp = 5,
272 .vbp = 41,
273 };
274 EXPORT_SYMBOL(omap_dss_pal_timings);
275
276 const struct omap_video_timings omap_dss_ntsc_timings = {
277 .x_res = 720,
278 .y_res = 482,
279 .pixel_clock = 13500,
280 .hsw = 64,
281 .hfp = 16,
282 .hbp = 58,
283 .vsw = 6,
284 .vfp = 6,
285 .vbp = 31,
286 };
287 EXPORT_SYMBOL(omap_dss_ntsc_timings);
288
289 static struct {
290 struct platform_device *pdev;
291 void __iomem *base;
292 struct mutex venc_lock;
293 u32 wss_data;
294 struct regulator *vdda_dac_reg;
295 } venc;
296
297 static inline void venc_write_reg(int idx, u32 val)
298 {
299 __raw_writel(val, venc.base + idx);
300 }
301
302 static inline u32 venc_read_reg(int idx)
303 {
304 u32 l = __raw_readl(venc.base + idx);
305 return l;
306 }
307
308 static void venc_write_config(const struct venc_config *config)
309 {
310 DSSDBG("write venc conf\n");
311
312 venc_write_reg(VENC_LLEN, config->llen);
313 venc_write_reg(VENC_FLENS, config->flens);
314 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
315 venc_write_reg(VENC_C_PHASE, config->c_phase);
316 venc_write_reg(VENC_GAIN_U, config->gain_u);
317 venc_write_reg(VENC_GAIN_V, config->gain_v);
318 venc_write_reg(VENC_GAIN_Y, config->gain_y);
319 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
320 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
321 venc_write_reg(VENC_M_CONTROL, config->m_control);
322 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
323 venc.wss_data);
324 venc_write_reg(VENC_S_CARR, config->s_carr);
325 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
326 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
327 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
328 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
329 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
330 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
331 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
332 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
333 config->vs_int_stop_x__vs_int_start_y);
334 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
335 config->vs_int_stop_y__vs_ext_start_x);
336 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
337 config->vs_ext_stop_x__vs_ext_start_y);
338 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
339 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
340 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
341 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
342 config->fid_int_start_x__fid_int_start_y);
343 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
344 config->fid_int_offset_y__fid_ext_start_x);
345 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
346 config->fid_ext_start_y__fid_ext_offset_y);
347
348 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
349 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
350 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
351 venc_write_reg(VENC_X_COLOR, config->x_color);
352 venc_write_reg(VENC_LINE21, config->line21);
353 venc_write_reg(VENC_LN_SEL, config->ln_sel);
354 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
355 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
356 config->tvdetgp_int_start_stop_x);
357 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
358 config->tvdetgp_int_start_stop_y);
359 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
360 venc_write_reg(VENC_F_CONTROL, config->f_control);
361 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
362 }
363
364 static void venc_reset(void)
365 {
366 int t = 1000;
367
368 venc_write_reg(VENC_F_CONTROL, 1<<8);
369 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
370 if (--t == 0) {
371 DSSERR("Failed to reset venc\n");
372 return;
373 }
374 }
375
376 /* the magical sleep that makes things work */
377 msleep(20);
378 }
379
380 static void venc_enable_clocks(int enable)
381 {
382 if (enable)
383 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
384 DSS_CLK_VIDFCK);
385 else
386 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
387 DSS_CLK_VIDFCK);
388 }
389
390 static const struct venc_config *venc_timings_to_config(
391 struct omap_video_timings *timings)
392 {
393 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
394 return &venc_config_pal_trm;
395
396 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
397 return &venc_config_ntsc_trm;
398
399 BUG();
400 }
401
402 static void venc_power_on(struct omap_dss_device *dssdev)
403 {
404 u32 l;
405
406 venc_enable_clocks(1);
407
408 venc_reset();
409 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
410
411 dss_set_venc_output(dssdev->phy.venc.type);
412 dss_set_dac_pwrdn_bgz(1);
413
414 l = 0;
415
416 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
417 l |= 1 << 1;
418 else /* S-Video */
419 l |= (1 << 0) | (1 << 2);
420
421 if (dssdev->phy.venc.invert_polarity == false)
422 l |= 1 << 3;
423
424 venc_write_reg(VENC_OUTPUT_CONTROL, l);
425
426 dispc_set_digit_size(dssdev->panel.timings.x_res,
427 dssdev->panel.timings.y_res/2);
428
429 regulator_enable(venc.vdda_dac_reg);
430
431 if (dssdev->platform_enable)
432 dssdev->platform_enable(dssdev);
433
434 dssdev->manager->enable(dssdev->manager);
435 }
436
437 static void venc_power_off(struct omap_dss_device *dssdev)
438 {
439 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
440 dss_set_dac_pwrdn_bgz(0);
441
442 dssdev->manager->disable(dssdev->manager);
443
444 if (dssdev->platform_disable)
445 dssdev->platform_disable(dssdev);
446
447 regulator_disable(venc.vdda_dac_reg);
448
449 venc_enable_clocks(0);
450 }
451
452
453
454
455
456 /* driver */
457 static int venc_panel_probe(struct omap_dss_device *dssdev)
458 {
459 dssdev->panel.timings = omap_dss_pal_timings;
460
461 return 0;
462 }
463
464 static void venc_panel_remove(struct omap_dss_device *dssdev)
465 {
466 }
467
468 static int venc_panel_enable(struct omap_dss_device *dssdev)
469 {
470 int r = 0;
471
472 DSSDBG("venc_enable_display\n");
473
474 mutex_lock(&venc.venc_lock);
475
476 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
477 r = -EINVAL;
478 goto err1;
479 }
480
481 venc_power_on(dssdev);
482
483 venc.wss_data = 0;
484
485 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
486
487 /* wait couple of vsyncs until enabling the LCD */
488 msleep(50);
489
490 err1:
491 mutex_unlock(&venc.venc_lock);
492
493 return r;
494 }
495
496 static void venc_panel_disable(struct omap_dss_device *dssdev)
497 {
498 DSSDBG("venc_disable_display\n");
499
500 mutex_lock(&venc.venc_lock);
501
502 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
503 goto end;
504
505 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
506 /* suspended is the same as disabled with venc */
507 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
508 goto end;
509 }
510
511 venc_power_off(dssdev);
512
513 /* wait at least 5 vsyncs after disabling the LCD */
514 msleep(100);
515
516 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
517 end:
518 mutex_unlock(&venc.venc_lock);
519 }
520
521 static int venc_panel_suspend(struct omap_dss_device *dssdev)
522 {
523 venc_panel_disable(dssdev);
524 return 0;
525 }
526
527 static int venc_panel_resume(struct omap_dss_device *dssdev)
528 {
529 return venc_panel_enable(dssdev);
530 }
531
532 static enum omap_dss_update_mode venc_get_update_mode(
533 struct omap_dss_device *dssdev)
534 {
535 return OMAP_DSS_UPDATE_AUTO;
536 }
537
538 static int venc_set_update_mode(struct omap_dss_device *dssdev,
539 enum omap_dss_update_mode mode)
540 {
541 if (mode != OMAP_DSS_UPDATE_AUTO)
542 return -EINVAL;
543 return 0;
544 }
545
546 static void venc_get_timings(struct omap_dss_device *dssdev,
547 struct omap_video_timings *timings)
548 {
549 *timings = dssdev->panel.timings;
550 }
551
552 static void venc_set_timings(struct omap_dss_device *dssdev,
553 struct omap_video_timings *timings)
554 {
555 DSSDBG("venc_set_timings\n");
556
557 /* Reset WSS data when the TV standard changes. */
558 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
559 venc.wss_data = 0;
560
561 dssdev->panel.timings = *timings;
562 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
563 /* turn the venc off and on to get new timings to use */
564 venc_panel_disable(dssdev);
565 venc_panel_enable(dssdev);
566 }
567 }
568
569 static int venc_check_timings(struct omap_dss_device *dssdev,
570 struct omap_video_timings *timings)
571 {
572 DSSDBG("venc_check_timings\n");
573
574 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
575 return 0;
576
577 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
578 return 0;
579
580 return -EINVAL;
581 }
582
583 static u32 venc_get_wss(struct omap_dss_device *dssdev)
584 {
585 /* Invert due to VENC_L21_WC_CTL:INV=1 */
586 return (venc.wss_data >> 8) ^ 0xfffff;
587 }
588
589 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
590 {
591 const struct venc_config *config;
592
593 DSSDBG("venc_set_wss\n");
594
595 mutex_lock(&venc.venc_lock);
596
597 config = venc_timings_to_config(&dssdev->panel.timings);
598
599 /* Invert due to VENC_L21_WC_CTL:INV=1 */
600 venc.wss_data = (wss ^ 0xfffff) << 8;
601
602 venc_enable_clocks(1);
603
604 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
605 venc.wss_data);
606
607 venc_enable_clocks(0);
608
609 mutex_unlock(&venc.venc_lock);
610
611 return 0;
612 }
613
614 static struct omap_dss_driver venc_driver = {
615 .probe = venc_panel_probe,
616 .remove = venc_panel_remove,
617
618 .enable = venc_panel_enable,
619 .disable = venc_panel_disable,
620 .suspend = venc_panel_suspend,
621 .resume = venc_panel_resume,
622
623 .get_resolution = omapdss_default_get_resolution,
624 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
625
626 .set_update_mode = venc_set_update_mode,
627 .get_update_mode = venc_get_update_mode,
628
629 .get_timings = venc_get_timings,
630 .set_timings = venc_set_timings,
631 .check_timings = venc_check_timings,
632
633 .get_wss = venc_get_wss,
634 .set_wss = venc_set_wss,
635
636 .driver = {
637 .name = "venc",
638 .owner = THIS_MODULE,
639 },
640 };
641 /* driver end */
642
643 int venc_init_display(struct omap_dss_device *dssdev)
644 {
645 DSSDBG("init_display\n");
646
647 if (venc.vdda_dac_reg == NULL) {
648 struct regulator *vdda_dac;
649
650 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
651
652 if (IS_ERR(vdda_dac)) {
653 DSSERR("can't get VDDA_DAC regulator\n");
654 return PTR_ERR(vdda_dac);
655 }
656
657 venc.vdda_dac_reg = vdda_dac;
658 }
659
660 return 0;
661 }
662
663 void venc_dump_regs(struct seq_file *s)
664 {
665 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
666
667 venc_enable_clocks(1);
668
669 DUMPREG(VENC_F_CONTROL);
670 DUMPREG(VENC_VIDOUT_CTRL);
671 DUMPREG(VENC_SYNC_CTRL);
672 DUMPREG(VENC_LLEN);
673 DUMPREG(VENC_FLENS);
674 DUMPREG(VENC_HFLTR_CTRL);
675 DUMPREG(VENC_CC_CARR_WSS_CARR);
676 DUMPREG(VENC_C_PHASE);
677 DUMPREG(VENC_GAIN_U);
678 DUMPREG(VENC_GAIN_V);
679 DUMPREG(VENC_GAIN_Y);
680 DUMPREG(VENC_BLACK_LEVEL);
681 DUMPREG(VENC_BLANK_LEVEL);
682 DUMPREG(VENC_X_COLOR);
683 DUMPREG(VENC_M_CONTROL);
684 DUMPREG(VENC_BSTAMP_WSS_DATA);
685 DUMPREG(VENC_S_CARR);
686 DUMPREG(VENC_LINE21);
687 DUMPREG(VENC_LN_SEL);
688 DUMPREG(VENC_L21__WC_CTL);
689 DUMPREG(VENC_HTRIGGER_VTRIGGER);
690 DUMPREG(VENC_SAVID__EAVID);
691 DUMPREG(VENC_FLEN__FAL);
692 DUMPREG(VENC_LAL__PHASE_RESET);
693 DUMPREG(VENC_HS_INT_START_STOP_X);
694 DUMPREG(VENC_HS_EXT_START_STOP_X);
695 DUMPREG(VENC_VS_INT_START_X);
696 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
697 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
698 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
699 DUMPREG(VENC_VS_EXT_STOP_Y);
700 DUMPREG(VENC_AVID_START_STOP_X);
701 DUMPREG(VENC_AVID_START_STOP_Y);
702 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
703 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
704 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
705 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
706 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
707 DUMPREG(VENC_GEN_CTRL);
708 DUMPREG(VENC_OUTPUT_CONTROL);
709 DUMPREG(VENC_OUTPUT_TEST);
710
711 venc_enable_clocks(0);
712
713 #undef DUMPREG
714 }
715
716 /* VENC HW IP initialisation */
717 static int omap_venchw_probe(struct platform_device *pdev)
718 {
719 u8 rev_id;
720 struct resource *venc_mem;
721
722 venc.pdev = pdev;
723
724 mutex_init(&venc.venc_lock);
725
726 venc.wss_data = 0;
727
728 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
729 if (!venc_mem) {
730 DSSERR("can't get IORESOURCE_MEM VENC\n");
731 return -EINVAL;
732 }
733 venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
734 if (!venc.base) {
735 DSSERR("can't ioremap VENC\n");
736 return -ENOMEM;
737 }
738
739 venc_enable_clocks(1);
740
741 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
742 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
743
744 venc_enable_clocks(0);
745
746 return omap_dss_register_driver(&venc_driver);
747 }
748
749 static int omap_venchw_remove(struct platform_device *pdev)
750 {
751 if (venc.vdda_dac_reg != NULL) {
752 regulator_put(venc.vdda_dac_reg);
753 venc.vdda_dac_reg = NULL;
754 }
755 omap_dss_unregister_driver(&venc_driver);
756
757 iounmap(venc.base);
758 return 0;
759 }
760
761 static struct platform_driver omap_venchw_driver = {
762 .probe = omap_venchw_probe,
763 .remove = omap_venchw_remove,
764 .driver = {
765 .name = "omapdss_venc",
766 .owner = THIS_MODULE,
767 },
768 };
769
770 int venc_init_platform_driver(void)
771 {
772 if (cpu_is_omap44xx())
773 return 0;
774
775 return platform_driver_register(&omap_venchw_driver);
776 }
777
778 void venc_uninit_platform_driver(void)
779 {
780 if (cpu_is_omap44xx())
781 return;
782
783 return platform_driver_unregister(&omap_venchw_driver);
784 }
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