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IPVS: fix netns if reading ip_vs_* procfs entries
[linux-2.6/linux-mips.git] / drivers / video / s3fb.c
blobc4482f2e5799130f946cb8daf80c63a295a83ee1
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/mm.h>
19 #include <linux/tty.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/svga.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
26 #include <video/vga.h>
27
28 #ifdef CONFIG_MTRR
29 #include <asm/mtrr.h>
30 #endif
31
32 struct s3fb_info {
33 int chip, rev, mclk_freq;
34 int mtrr_reg;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39 };
40
41
42 /* ------------------------------------------------------------------------- */
43
44 static const struct svga_fb_format s3fb_formats[] = {
45 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
46 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
47 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
48 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
49 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
50 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
51 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
52 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
53 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
55 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
59 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 SVGA_FORMAT_END
62 };
63
64
65 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
66 35000, 240000, 14318};
67 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
68 230000, 460000, 14318};
69
70 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
71
72 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
74 "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
76 "S3 Virge/GX2", "S3 Virge/GX2+", "",
77 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
78 "S3 Trio3D"};
79
80 #define CHIP_UNKNOWN 0x00
81 #define CHIP_732_TRIO32 0x01
82 #define CHIP_764_TRIO64 0x02
83 #define CHIP_765_TRIO64VP 0x03
84 #define CHIP_767_TRIO64UVP 0x04
85 #define CHIP_775_TRIO64V2_DX 0x05
86 #define CHIP_785_TRIO64V2_GX 0x06
87 #define CHIP_551_PLATO_PX 0x07
88 #define CHIP_M65_AURORA64VP 0x08
89 #define CHIP_325_VIRGE 0x09
90 #define CHIP_988_VIRGE_VX 0x0A
91 #define CHIP_375_VIRGE_DX 0x0B
92 #define CHIP_385_VIRGE_GX 0x0C
93 #define CHIP_357_VIRGE_GX2 0x0D
94 #define CHIP_359_VIRGE_GX2P 0x0E
95 #define CHIP_360_TRIO3D_1X 0x10
96 #define CHIP_362_TRIO3D_2X 0x11
97 #define CHIP_368_TRIO3D_2X 0x12
98 #define CHIP_365_TRIO3D 0x13
99
100 #define CHIP_XXX_TRIO 0x80
101 #define CHIP_XXX_TRIO64V2_DXGX 0x81
102 #define CHIP_XXX_VIRGE_DXGX 0x82
103 #define CHIP_36X_TRIO3D_1X_2X 0x83
104
105 #define CHIP_UNDECIDED_FLAG 0x80
106 #define CHIP_MASK 0xFF
107
108 /* CRT timing register sets */
109
110 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
111 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
112 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
113 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
114 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
115 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
116
117 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
118 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
119 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
120 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
121 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
122 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
123
124 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
125 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
126 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
127
128 static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
129
130 static const struct svga_timing_regs s3_timing_regs = {
131 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
132 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
133 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
134 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
135 };
136
137
138 /* ------------------------------------------------------------------------- */
139
140 /* Module parameters */
141
142
143 static char *mode_option __devinitdata = "640x480-8@60";
144
145 #ifdef CONFIG_MTRR
146 static int mtrr __devinitdata = 1;
147 #endif
148
149 static int fasttext = 1;
150
151
152 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
153 MODULE_LICENSE("GPL");
154 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
155
156 module_param(mode_option, charp, 0444);
157 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
158 module_param_named(mode, mode_option, charp, 0444);
159 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
160
161 #ifdef CONFIG_MTRR
162 module_param(mtrr, int, 0444);
163 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
164 #endif
165
166 module_param(fasttext, int, 0644);
167 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
168
169
170 /* ------------------------------------------------------------------------- */
171
172 /* Set font in S3 fast text mode */
173
174 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
175 {
176 const u8 *font = map->data;
177 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
178 int i, c;
179
180 if ((map->width != 8) || (map->height != 16) ||
181 (map->depth != 1) || (map->length != 256)) {
182 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
183 info->node, map->width, map->height, map->depth, map->length);
184 return;
185 }
186
187 fb += 2;
188 for (i = 0; i < map->height; i++) {
189 for (c = 0; c < map->length; c++) {
190 fb_writeb(font[c * map->height + i], fb + c * 4);
191 }
192 fb += 1024;
193 }
194 }
195
196 static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
197 {
198 struct s3fb_info *par = info->par;
199
200 svga_tilecursor(par->state.vgabase, info, cursor);
201 }
202
203 static struct fb_tile_ops s3fb_tile_ops = {
204 .fb_settile = svga_settile,
205 .fb_tilecopy = svga_tilecopy,
206 .fb_tilefill = svga_tilefill,
207 .fb_tileblit = svga_tileblit,
208 .fb_tilecursor = s3fb_tilecursor,
209 .fb_get_tilemax = svga_get_tilemax,
210 };
211
212 static struct fb_tile_ops s3fb_fast_tile_ops = {
213 .fb_settile = s3fb_settile_fast,
214 .fb_tilecopy = svga_tilecopy,
215 .fb_tilefill = svga_tilefill,
216 .fb_tileblit = svga_tileblit,
217 .fb_tilecursor = s3fb_tilecursor,
218 .fb_get_tilemax = svga_get_tilemax,
219 };
220
221
222 /* ------------------------------------------------------------------------- */
223
224 /* image data is MSB-first, fb structure is MSB-first too */
225 static inline u32 expand_color(u32 c)
226 {
227 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
228 }
229
230 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
231 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
232 {
233 u32 fg = expand_color(image->fg_color);
234 u32 bg = expand_color(image->bg_color);
235 const u8 *src1, *src;
236 u8 __iomem *dst1;
237 u32 __iomem *dst;
238 u32 val;
239 int x, y;
240
241 src1 = image->data;
242 dst1 = info->screen_base + (image->dy * info->fix.line_length)
243 + ((image->dx / 8) * 4);
244
245 for (y = 0; y < image->height; y++) {
246 src = src1;
247 dst = (u32 __iomem *) dst1;
248 for (x = 0; x < image->width; x += 8) {
249 val = *(src++) * 0x01010101;
250 val = (val & fg) | (~val & bg);
251 fb_writel(val, dst++);
252 }
253 src1 += image->width / 8;
254 dst1 += info->fix.line_length;
255 }
256
257 }
258
259 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
260 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
261 {
262 u32 fg = expand_color(rect->color);
263 u8 __iomem *dst1;
264 u32 __iomem *dst;
265 int x, y;
266
267 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
268 + ((rect->dx / 8) * 4);
269
270 for (y = 0; y < rect->height; y++) {
271 dst = (u32 __iomem *) dst1;
272 for (x = 0; x < rect->width; x += 8) {
273 fb_writel(fg, dst++);
274 }
275 dst1 += info->fix.line_length;
276 }
277 }
278
279
280 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
281 static inline u32 expand_pixel(u32 c)
282 {
283 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
284 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
285 }
286
287 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
288 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
289 {
290 u32 fg = image->fg_color * 0x11111111;
291 u32 bg = image->bg_color * 0x11111111;
292 const u8 *src1, *src;
293 u8 __iomem *dst1;
294 u32 __iomem *dst;
295 u32 val;
296 int x, y;
297
298 src1 = image->data;
299 dst1 = info->screen_base + (image->dy * info->fix.line_length)
300 + ((image->dx / 8) * 4);
301
302 for (y = 0; y < image->height; y++) {
303 src = src1;
304 dst = (u32 __iomem *) dst1;
305 for (x = 0; x < image->width; x += 8) {
306 val = expand_pixel(*(src++));
307 val = (val & fg) | (~val & bg);
308 fb_writel(val, dst++);
309 }
310 src1 += image->width / 8;
311 dst1 += info->fix.line_length;
312 }
313 }
314
315 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
316 {
317 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
318 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
319 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
320 s3fb_iplan_imageblit(info, image);
321 else
322 s3fb_cfb4_imageblit(info, image);
323 } else
324 cfb_imageblit(info, image);
325 }
326
327 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
328 {
329 if ((info->var.bits_per_pixel == 4)
330 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
331 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
332 s3fb_iplan_fillrect(info, rect);
333 else
334 cfb_fillrect(info, rect);
335 }
336
337
338
339 /* ------------------------------------------------------------------------- */
340
341
342 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
343 {
344 struct s3fb_info *par = info->par;
345 u16 m, n, r;
346 u8 regval;
347 int rv;
348
349 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
350 1000000000 / pixclock, &m, &n, &r, info->node);
351 if (rv < 0) {
352 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
353 return;
354 }
355
356 /* Set VGA misc register */
357 regval = vga_r(par->state.vgabase, VGA_MIS_R);
358 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
359
360 /* Set S3 clock registers */
361 if (par->chip == CHIP_357_VIRGE_GX2 ||
362 par->chip == CHIP_359_VIRGE_GX2P ||
363 par->chip == CHIP_360_TRIO3D_1X ||
364 par->chip == CHIP_362_TRIO3D_2X ||
365 par->chip == CHIP_368_TRIO3D_2X) {
366 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
367 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
368 } else
369 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
370 vga_wseq(par->state.vgabase, 0x13, m - 2);
371
372 udelay(1000);
373
374 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
375 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
376 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
377 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
378 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
379 }
380
381
382 /* Open framebuffer */
383
384 static int s3fb_open(struct fb_info *info, int user)
385 {
386 struct s3fb_info *par = info->par;
387
388 mutex_lock(&(par->open_lock));
389 if (par->ref_count == 0) {
390 void __iomem *vgabase = par->state.vgabase;
391
392 memset(&(par->state), 0, sizeof(struct vgastate));
393 par->state.vgabase = vgabase;
394 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
395 par->state.num_crtc = 0x70;
396 par->state.num_seq = 0x20;
397 save_vga(&(par->state));
398 }
399
400 par->ref_count++;
401 mutex_unlock(&(par->open_lock));
402
403 return 0;
404 }
405
406 /* Close framebuffer */
407
408 static int s3fb_release(struct fb_info *info, int user)
409 {
410 struct s3fb_info *par = info->par;
411
412 mutex_lock(&(par->open_lock));
413 if (par->ref_count == 0) {
414 mutex_unlock(&(par->open_lock));
415 return -EINVAL;
416 }
417
418 if (par->ref_count == 1)
419 restore_vga(&(par->state));
420
421 par->ref_count--;
422 mutex_unlock(&(par->open_lock));
423
424 return 0;
425 }
426
427 /* Validate passed in var */
428
429 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
430 {
431 struct s3fb_info *par = info->par;
432 int rv, mem, step;
433 u16 m, n, r;
434
435 /* Find appropriate format */
436 rv = svga_match_format (s3fb_formats, var, NULL);
437
438 /* 32bpp mode is not supported on VIRGE VX,
439 24bpp is not supported on others */
440 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
441 rv = -EINVAL;
442
443 if (rv < 0) {
444 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
445 return rv;
446 }
447
448 /* Do not allow to have real resoulution larger than virtual */
449 if (var->xres > var->xres_virtual)
450 var->xres_virtual = var->xres;
451
452 if (var->yres > var->yres_virtual)
453 var->yres_virtual = var->yres;
454
455 /* Round up xres_virtual to have proper alignment of lines */
456 step = s3fb_formats[rv].xresstep - 1;
457 var->xres_virtual = (var->xres_virtual+step) & ~step;
458
459 /* Check whether have enough memory */
460 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
461 if (mem > info->screen_size) {
462 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
463 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
464 return -EINVAL;
465 }
466
467 rv = svga_check_timings (&s3_timing_regs, var, info->node);
468 if (rv < 0) {
469 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
470 return rv;
471 }
472
473 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
474 info->node);
475 if (rv < 0) {
476 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
477 info->node);
478 return rv;
479 }
480
481 return 0;
482 }
483
484 /* Set video mode from par */
485
486 static int s3fb_set_par(struct fb_info *info)
487 {
488 struct s3fb_info *par = info->par;
489 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
490 u32 bpp = info->var.bits_per_pixel;
491 u32 htotal, hsstart;
492
493 if (bpp != 0) {
494 info->fix.ypanstep = 1;
495 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
496
497 info->flags &= ~FBINFO_MISC_TILEBLITTING;
498 info->tileops = NULL;
499
500 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
501 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
502 info->pixmap.blit_y = ~(u32)0;
503
504 offset_value = (info->var.xres_virtual * bpp) / 64;
505 screen_size = info->var.yres_virtual * info->fix.line_length;
506 } else {
507 info->fix.ypanstep = 16;
508 info->fix.line_length = 0;
509
510 info->flags |= FBINFO_MISC_TILEBLITTING;
511 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
512
513 /* supports 8x16 tiles only */
514 info->pixmap.blit_x = 1 << (8 - 1);
515 info->pixmap.blit_y = 1 << (16 - 1);
516
517 offset_value = info->var.xres_virtual / 16;
518 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
519 }
520
521 info->var.xoffset = 0;
522 info->var.yoffset = 0;
523 info->var.activate = FB_ACTIVATE_NOW;
524
525 /* Unlock registers */
526 vga_wcrt(par->state.vgabase, 0x38, 0x48);
527 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
528 vga_wseq(par->state.vgabase, 0x08, 0x06);
529 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
530
531 /* Blank screen and turn off sync */
532 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
533 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
534
535 /* Set default values */
536 svga_set_default_gfx_regs(par->state.vgabase);
537 svga_set_default_atc_regs(par->state.vgabase);
538 svga_set_default_seq_regs(par->state.vgabase);
539 svga_set_default_crt_regs(par->state.vgabase);
540 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
541 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
542
543 /* S3 specific initialization */
544 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
545 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
546
547 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
548 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
549 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
550 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
551
552 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
553
554 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
555
556 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
557 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
558
559
560 /* Set the offset register */
561 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
562 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
563
564 if (par->chip != CHIP_357_VIRGE_GX2 &&
565 par->chip != CHIP_359_VIRGE_GX2P &&
566 par->chip != CHIP_360_TRIO3D_1X &&
567 par->chip != CHIP_362_TRIO3D_2X &&
568 par->chip != CHIP_368_TRIO3D_2X) {
569 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
570 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
571 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
572 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
573 }
574
575 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
576 svga_wattr(par->state.vgabase, 0x33, 0x00);
577
578 if (info->var.vmode & FB_VMODE_DOUBLE)
579 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
580 else
581 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
582
583 if (info->var.vmode & FB_VMODE_INTERLACED)
584 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
585 else
586 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
587
588 /* Disable hardware graphics cursor */
589 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
590 /* Disable Streams engine */
591 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
592
593 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
594
595 /* S3 virge DX hack */
596 if (par->chip == CHIP_375_VIRGE_DX) {
597 vga_wcrt(par->state.vgabase, 0x86, 0x80);
598 vga_wcrt(par->state.vgabase, 0x90, 0x00);
599 }
600
601 /* S3 virge VX hack */
602 if (par->chip == CHIP_988_VIRGE_VX) {
603 vga_wcrt(par->state.vgabase, 0x50, 0x00);
604 vga_wcrt(par->state.vgabase, 0x67, 0x50);
605
606 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
607 vga_wcrt(par->state.vgabase, 0x66, 0x90);
608 }
609
610 if (par->chip == CHIP_357_VIRGE_GX2 ||
611 par->chip == CHIP_359_VIRGE_GX2P ||
612 par->chip == CHIP_360_TRIO3D_1X ||
613 par->chip == CHIP_362_TRIO3D_2X ||
614 par->chip == CHIP_368_TRIO3D_2X ||
615 par->chip == CHIP_365_TRIO3D ||
616 par->chip == CHIP_375_VIRGE_DX ||
617 par->chip == CHIP_385_VIRGE_GX) {
618 dbytes = info->var.xres * ((bpp+7)/8);
619 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
620 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
621
622 vga_wcrt(par->state.vgabase, 0x66, 0x81);
623 }
624
625 if (par->chip == CHIP_357_VIRGE_GX2 ||
626 par->chip == CHIP_359_VIRGE_GX2P ||
627 par->chip == CHIP_360_TRIO3D_1X ||
628 par->chip == CHIP_362_TRIO3D_2X ||
629 par->chip == CHIP_368_TRIO3D_2X)
630 vga_wcrt(par->state.vgabase, 0x34, 0x00);
631 else /* enable Data Transfer Position Control (DTPC) */
632 vga_wcrt(par->state.vgabase, 0x34, 0x10);
633
634 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
635 multiplex = 0;
636 hmul = 1;
637
638 /* Set mode-specific register values */
639 switch (mode) {
640 case 0:
641 pr_debug("fb%d: text mode\n", info->node);
642 svga_set_textmode_vga_regs(par->state.vgabase);
643
644 /* Set additional registers like in 8-bit mode */
645 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
646 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
647
648 /* Disable enhanced mode */
649 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
650
651 if (fasttext) {
652 pr_debug("fb%d: high speed text mode set\n", info->node);
653 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
654 }
655 break;
656 case 1:
657 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
658 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
659
660 /* Set additional registers like in 8-bit mode */
661 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
662 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
663
664 /* disable enhanced mode */
665 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
666 break;
667 case 2:
668 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
669
670 /* Set additional registers like in 8-bit mode */
671 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
672 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
673
674 /* disable enhanced mode */
675 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
676 break;
677 case 3:
678 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
679 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
680 if (info->var.pixclock > 20000 ||
681 par->chip == CHIP_357_VIRGE_GX2 ||
682 par->chip == CHIP_359_VIRGE_GX2P ||
683 par->chip == CHIP_360_TRIO3D_1X ||
684 par->chip == CHIP_362_TRIO3D_2X ||
685 par->chip == CHIP_368_TRIO3D_2X)
686 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
687 else {
688 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
689 multiplex = 1;
690 }
691 break;
692 case 4:
693 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
694 if (par->chip == CHIP_988_VIRGE_VX) {
695 if (info->var.pixclock > 20000)
696 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
697 else
698 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
699 } else if (par->chip == CHIP_365_TRIO3D) {
700 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
701 if (info->var.pixclock > 8695) {
702 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
703 hmul = 2;
704 } else {
705 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
706 multiplex = 1;
707 }
708 } else {
709 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
710 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
711 if (par->chip != CHIP_357_VIRGE_GX2 &&
712 par->chip != CHIP_359_VIRGE_GX2P &&
713 par->chip != CHIP_360_TRIO3D_1X &&
714 par->chip != CHIP_362_TRIO3D_2X &&
715 par->chip != CHIP_368_TRIO3D_2X)
716 hmul = 2;
717 }
718 break;
719 case 5:
720 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
721 if (par->chip == CHIP_988_VIRGE_VX) {
722 if (info->var.pixclock > 20000)
723 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
724 else
725 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
726 } else if (par->chip == CHIP_365_TRIO3D) {
727 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
728 if (info->var.pixclock > 8695) {
729 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
730 hmul = 2;
731 } else {
732 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
733 multiplex = 1;
734 }
735 } else {
736 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
737 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
738 if (par->chip != CHIP_357_VIRGE_GX2 &&
739 par->chip != CHIP_359_VIRGE_GX2P &&
740 par->chip != CHIP_360_TRIO3D_1X &&
741 par->chip != CHIP_362_TRIO3D_2X &&
742 par->chip != CHIP_368_TRIO3D_2X)
743 hmul = 2;
744 }
745 break;
746 case 6:
747 /* VIRGE VX case */
748 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
749 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
750 break;
751 case 7:
752 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
753 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
754 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
755 break;
756 default:
757 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
758 return -EINVAL;
759 }
760
761 if (par->chip != CHIP_988_VIRGE_VX) {
762 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
763 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
764 }
765
766 s3_set_pixclock(info, info->var.pixclock);
767 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
768 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
769 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
770 hmul, info->node);
771
772 /* Set interlaced mode start/end register */
773 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
774 htotal = ((htotal * hmul) / 8) - 5;
775 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
776
777 /* Set Data Transfer Position */
778 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
779 value = clamp((htotal + hsstart + 1) / 2, hsstart + 4, htotal + 1);
780 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
781
782 memset_io(info->screen_base, 0x00, screen_size);
783 /* Device and screen back on */
784 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
785 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
786
787 return 0;
788 }
789
790 /* Set a colour register */
791
792 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
793 u_int transp, struct fb_info *fb)
794 {
795 switch (fb->var.bits_per_pixel) {
796 case 0:
797 case 4:
798 if (regno >= 16)
799 return -EINVAL;
800
801 if ((fb->var.bits_per_pixel == 4) &&
802 (fb->var.nonstd == 0)) {
803 outb(0xF0, VGA_PEL_MSK);
804 outb(regno*16, VGA_PEL_IW);
805 } else {
806 outb(0x0F, VGA_PEL_MSK);
807 outb(regno, VGA_PEL_IW);
808 }
809 outb(red >> 10, VGA_PEL_D);
810 outb(green >> 10, VGA_PEL_D);
811 outb(blue >> 10, VGA_PEL_D);
812 break;
813 case 8:
814 if (regno >= 256)
815 return -EINVAL;
816
817 outb(0xFF, VGA_PEL_MSK);
818 outb(regno, VGA_PEL_IW);
819 outb(red >> 10, VGA_PEL_D);
820 outb(green >> 10, VGA_PEL_D);
821 outb(blue >> 10, VGA_PEL_D);
822 break;
823 case 16:
824 if (regno >= 16)
825 return 0;
826
827 if (fb->var.green.length == 5)
828 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
829 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
830 else if (fb->var.green.length == 6)
831 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
832 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
833 else return -EINVAL;
834 break;
835 case 24:
836 case 32:
837 if (regno >= 16)
838 return 0;
839
840 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
841 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
842 break;
843 default:
844 return -EINVAL;
845 }
846
847 return 0;
848 }
849
850
851 /* Set the display blanking state */
852
853 static int s3fb_blank(int blank_mode, struct fb_info *info)
854 {
855 struct s3fb_info *par = info->par;
856
857 switch (blank_mode) {
858 case FB_BLANK_UNBLANK:
859 pr_debug("fb%d: unblank\n", info->node);
860 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
861 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
862 break;
863 case FB_BLANK_NORMAL:
864 pr_debug("fb%d: blank\n", info->node);
865 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
866 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
867 break;
868 case FB_BLANK_HSYNC_SUSPEND:
869 pr_debug("fb%d: hsync\n", info->node);
870 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
871 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
872 break;
873 case FB_BLANK_VSYNC_SUSPEND:
874 pr_debug("fb%d: vsync\n", info->node);
875 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
876 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
877 break;
878 case FB_BLANK_POWERDOWN:
879 pr_debug("fb%d: sync down\n", info->node);
880 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
881 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
882 break;
883 }
884
885 return 0;
886 }
887
888
889 /* Pan the display */
890
891 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
892 {
893 struct s3fb_info *par = info->par;
894 unsigned int offset;
895
896 /* Calculate the offset */
897 if (var->bits_per_pixel == 0) {
898 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
899 offset = offset >> 2;
900 } else {
901 offset = (var->yoffset * info->fix.line_length) +
902 (var->xoffset * var->bits_per_pixel / 8);
903 offset = offset >> 2;
904 }
905
906 /* Set the offset */
907 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
908
909 return 0;
910 }
911
912 /* ------------------------------------------------------------------------- */
913
914 /* Frame buffer operations */
915
916 static struct fb_ops s3fb_ops = {
917 .owner = THIS_MODULE,
918 .fb_open = s3fb_open,
919 .fb_release = s3fb_release,
920 .fb_check_var = s3fb_check_var,
921 .fb_set_par = s3fb_set_par,
922 .fb_setcolreg = s3fb_setcolreg,
923 .fb_blank = s3fb_blank,
924 .fb_pan_display = s3fb_pan_display,
925 .fb_fillrect = s3fb_fillrect,
926 .fb_copyarea = cfb_copyarea,
927 .fb_imageblit = s3fb_imageblit,
928 .fb_get_caps = svga_get_caps,
929 };
930
931 /* ------------------------------------------------------------------------- */
932
933 static int __devinit s3_identification(struct s3fb_info *par)
934 {
935 int chip = par->chip;
936
937 if (chip == CHIP_XXX_TRIO) {
938 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
939 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
940 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
941
942 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
943 if (cr2e == 0x10)
944 return CHIP_732_TRIO32;
945 if (cr2e == 0x11) {
946 if (! (cr2f & 0x40))
947 return CHIP_764_TRIO64;
948 else
949 return CHIP_765_TRIO64VP;
950 }
951 }
952 }
953
954 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
955 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
956
957 if (! (cr6f & 0x01))
958 return CHIP_775_TRIO64V2_DX;
959 else
960 return CHIP_785_TRIO64V2_GX;
961 }
962
963 if (chip == CHIP_XXX_VIRGE_DXGX) {
964 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
965
966 if (! (cr6f & 0x01))
967 return CHIP_375_VIRGE_DX;
968 else
969 return CHIP_385_VIRGE_GX;
970 }
971
972 if (chip == CHIP_36X_TRIO3D_1X_2X) {
973 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
974 case 0x00:
975 return CHIP_360_TRIO3D_1X;
976 case 0x01:
977 return CHIP_362_TRIO3D_2X;
978 case 0x02:
979 return CHIP_368_TRIO3D_2X;
980 }
981 }
982
983 return CHIP_UNKNOWN;
984 }
985
986
987 /* PCI probe */
988
989 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
990 {
991 struct pci_bus_region bus_reg;
992 struct resource vga_res;
993 struct fb_info *info;
994 struct s3fb_info *par;
995 int rc;
996 u8 regval, cr38, cr39;
997
998 /* Ignore secondary VGA device because there is no VGA arbitration */
999 if (! svga_primary_device(dev)) {
1000 dev_info(&(dev->dev), "ignoring secondary device\n");
1001 return -ENODEV;
1002 }
1003
1004 /* Allocate and fill driver data structure */
1005 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
1006 if (!info) {
1007 dev_err(&(dev->dev), "cannot allocate memory\n");
1008 return -ENOMEM;
1009 }
1010
1011 par = info->par;
1012 mutex_init(&par->open_lock);
1013
1014 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
1015 info->fbops = &s3fb_ops;
1016
1017 /* Prepare PCI device */
1018 rc = pci_enable_device(dev);
1019 if (rc < 0) {
1020 dev_err(info->device, "cannot enable PCI device\n");
1021 goto err_enable_device;
1022 }
1023
1024 rc = pci_request_regions(dev, "s3fb");
1025 if (rc < 0) {
1026 dev_err(info->device, "cannot reserve framebuffer region\n");
1027 goto err_request_regions;
1028 }
1029
1030
1031 info->fix.smem_start = pci_resource_start(dev, 0);
1032 info->fix.smem_len = pci_resource_len(dev, 0);
1033
1034 /* Map physical IO memory address into kernel space */
1035 info->screen_base = pci_iomap(dev, 0, 0);
1036 if (! info->screen_base) {
1037 rc = -ENOMEM;
1038 dev_err(info->device, "iomap for framebuffer failed\n");
1039 goto err_iomap;
1040 }
1041
1042 bus_reg.start = 0;
1043 bus_reg.end = 64 * 1024;
1044
1045 vga_res.flags = IORESOURCE_IO;
1046
1047 pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
1048
1049 par->state.vgabase = (void __iomem *) vga_res.start;
1050
1051 /* Unlock regs */
1052 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1053 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1054 vga_wseq(par->state.vgabase, 0x08, 0x06);
1055 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1056 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1057
1058 /* Identify chip type */
1059 par->chip = id->driver_data & CHIP_MASK;
1060 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1061 if (par->chip & CHIP_UNDECIDED_FLAG)
1062 par->chip = s3_identification(par);
1063
1064 /* Find how many physical memory there is on card */
1065 /* 0x36 register is accessible even if other registers are locked */
1066 regval = vga_rcrt(par->state.vgabase, 0x36);
1067 if (par->chip == CHIP_360_TRIO3D_1X ||
1068 par->chip == CHIP_362_TRIO3D_2X ||
1069 par->chip == CHIP_368_TRIO3D_2X ||
1070 par->chip == CHIP_365_TRIO3D) {
1071 switch ((regval & 0xE0) >> 5) {
1072 case 0: /* 8MB -- only 4MB usable for display */
1073 case 1: /* 4MB with 32-bit bus */
1074 case 2: /* 4MB */
1075 info->screen_size = 4 << 20;
1076 break;
1077 case 4: /* 2MB on 365 Trio3D */
1078 case 6: /* 2MB */
1079 info->screen_size = 2 << 20;
1080 break;
1081 }
1082 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1083 par->chip == CHIP_359_VIRGE_GX2P) {
1084 switch ((regval & 0xC0) >> 6) {
1085 case 1: /* 4MB */
1086 info->screen_size = 4 << 20;
1087 break;
1088 case 3: /* 2MB */
1089 info->screen_size = 2 << 20;
1090 break;
1091 }
1092 } else
1093 info->screen_size = s3_memsizes[regval >> 5] << 10;
1094 info->fix.smem_len = info->screen_size;
1095
1096 /* Find MCLK frequency */
1097 regval = vga_rseq(par->state.vgabase, 0x10);
1098 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1099 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1100
1101 /* Restore locks */
1102 vga_wcrt(par->state.vgabase, 0x38, cr38);
1103 vga_wcrt(par->state.vgabase, 0x39, cr39);
1104
1105 strcpy(info->fix.id, s3_names [par->chip]);
1106 info->fix.mmio_start = 0;
1107 info->fix.mmio_len = 0;
1108 info->fix.type = FB_TYPE_PACKED_PIXELS;
1109 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1110 info->fix.ypanstep = 0;
1111 info->fix.accel = FB_ACCEL_NONE;
1112 info->pseudo_palette = (void*) (par->pseudo_palette);
1113
1114 /* Prepare startup mode */
1115 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1116 if (! ((rc == 1) || (rc == 2))) {
1117 rc = -EINVAL;
1118 dev_err(info->device, "mode %s not found\n", mode_option);
1119 goto err_find_mode;
1120 }
1121
1122 /* maximize virtual vertical size for fast scrolling */
1123 info->var.yres_virtual = info->fix.smem_len * 8 /
1124 (info->var.bits_per_pixel * info->var.xres_virtual);
1125 if (info->var.yres_virtual < info->var.yres) {
1126 dev_err(info->device, "virtual vertical size smaller than real\n");
1127 goto err_find_mode;
1128 }
1129
1130 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1131 if (rc < 0) {
1132 dev_err(info->device, "cannot allocate colormap\n");
1133 goto err_alloc_cmap;
1134 }
1135
1136 rc = register_framebuffer(info);
1137 if (rc < 0) {
1138 dev_err(info->device, "cannot register framebuffer\n");
1139 goto err_reg_fb;
1140 }
1141
1142 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
1143 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1144
1145 if (par->chip == CHIP_UNKNOWN)
1146 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1147 info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e),
1148 vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30));
1149
1150 /* Record a reference to the driver data */
1151 pci_set_drvdata(dev, info);
1152
1153 #ifdef CONFIG_MTRR
1154 if (mtrr) {
1155 par->mtrr_reg = -1;
1156 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1157 }
1158 #endif
1159
1160 return 0;
1161
1162 /* Error handling */
1163 err_reg_fb:
1164 fb_dealloc_cmap(&info->cmap);
1165 err_alloc_cmap:
1166 err_find_mode:
1167 pci_iounmap(dev, info->screen_base);
1168 err_iomap:
1169 pci_release_regions(dev);
1170 err_request_regions:
1171 /* pci_disable_device(dev); */
1172 err_enable_device:
1173 framebuffer_release(info);
1174 return rc;
1175 }
1176
1177
1178 /* PCI remove */
1179
1180 static void __devexit s3_pci_remove(struct pci_dev *dev)
1181 {
1182 struct fb_info *info = pci_get_drvdata(dev);
1183
1184 if (info) {
1185
1186 #ifdef CONFIG_MTRR
1187 struct s3fb_info *par = info->par;
1188
1189 if (par->mtrr_reg >= 0) {
1190 mtrr_del(par->mtrr_reg, 0, 0);
1191 par->mtrr_reg = -1;
1192 }
1193 #endif
1194
1195 unregister_framebuffer(info);
1196 fb_dealloc_cmap(&info->cmap);
1197
1198 pci_iounmap(dev, info->screen_base);
1199 pci_release_regions(dev);
1200 /* pci_disable_device(dev); */
1201
1202 pci_set_drvdata(dev, NULL);
1203 framebuffer_release(info);
1204 }
1205 }
1206
1207 /* PCI suspend */
1208
1209 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1210 {
1211 struct fb_info *info = pci_get_drvdata(dev);
1212 struct s3fb_info *par = info->par;
1213
1214 dev_info(info->device, "suspend\n");
1215
1216 console_lock();
1217 mutex_lock(&(par->open_lock));
1218
1219 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1220 mutex_unlock(&(par->open_lock));
1221 console_unlock();
1222 return 0;
1223 }
1224
1225 fb_set_suspend(info, 1);
1226
1227 pci_save_state(dev);
1228 pci_disable_device(dev);
1229 pci_set_power_state(dev, pci_choose_state(dev, state));
1230
1231 mutex_unlock(&(par->open_lock));
1232 console_unlock();
1233
1234 return 0;
1235 }
1236
1237
1238 /* PCI resume */
1239
1240 static int s3_pci_resume(struct pci_dev* dev)
1241 {
1242 struct fb_info *info = pci_get_drvdata(dev);
1243 struct s3fb_info *par = info->par;
1244 int err;
1245
1246 dev_info(info->device, "resume\n");
1247
1248 console_lock();
1249 mutex_lock(&(par->open_lock));
1250
1251 if (par->ref_count == 0) {
1252 mutex_unlock(&(par->open_lock));
1253 console_unlock();
1254 return 0;
1255 }
1256
1257 pci_set_power_state(dev, PCI_D0);
1258 pci_restore_state(dev);
1259 err = pci_enable_device(dev);
1260 if (err) {
1261 mutex_unlock(&(par->open_lock));
1262 console_unlock();
1263 dev_err(info->device, "error %d enabling device for resume\n", err);
1264 return err;
1265 }
1266 pci_set_master(dev);
1267
1268 s3fb_set_par(info);
1269 fb_set_suspend(info, 0);
1270
1271 mutex_unlock(&(par->open_lock));
1272 console_unlock();
1273
1274 return 0;
1275 }
1276
1277
1278 /* List of boards that we are trying to support */
1279
1280 static struct pci_device_id s3_devices[] __devinitdata = {
1281 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1282 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1283 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1284 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1285 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1286 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1287
1288 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1289 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1290 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1291 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1292 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
1293 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1294 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1295 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1296
1297 {0, 0, 0, 0, 0, 0, 0}
1298 };
1299
1300
1301 MODULE_DEVICE_TABLE(pci, s3_devices);
1302
1303 static struct pci_driver s3fb_pci_driver = {
1304 .name = "s3fb",
1305 .id_table = s3_devices,
1306 .probe = s3_pci_probe,
1307 .remove = __devexit_p(s3_pci_remove),
1308 .suspend = s3_pci_suspend,
1309 .resume = s3_pci_resume,
1310 };
1311
1312 /* Parse user speficied options */
1313
1314 #ifndef MODULE
1315 static int __init s3fb_setup(char *options)
1316 {
1317 char *opt;
1318
1319 if (!options || !*options)
1320 return 0;
1321
1322 while ((opt = strsep(&options, ",")) != NULL) {
1323
1324 if (!*opt)
1325 continue;
1326 #ifdef CONFIG_MTRR
1327 else if (!strncmp(opt, "mtrr:", 5))
1328 mtrr = simple_strtoul(opt + 5, NULL, 0);
1329 #endif
1330 else if (!strncmp(opt, "fasttext:", 9))
1331 fasttext = simple_strtoul(opt + 9, NULL, 0);
1332 else
1333 mode_option = opt;
1334 }
1335
1336 return 0;
1337 }
1338 #endif
1339
1340 /* Cleanup */
1341
1342 static void __exit s3fb_cleanup(void)
1343 {
1344 pr_debug("s3fb: cleaning up\n");
1345 pci_unregister_driver(&s3fb_pci_driver);
1346 }
1347
1348 /* Driver Initialisation */
1349
1350 static int __init s3fb_init(void)
1351 {
1352
1353 #ifndef MODULE
1354 char *option = NULL;
1355
1356 if (fb_get_options("s3fb", &option))
1357 return -ENODEV;
1358 s3fb_setup(option);
1359 #endif
1360
1361 pr_debug("s3fb: initializing\n");
1362 return pci_register_driver(&s3fb_pci_driver);
1363 }
1364
1365 /* ------------------------------------------------------------------------- */
1366
1367 /* Modularization */
1368
1369 module_init(s3fb_init);
1370 module_exit(s3fb_cleanup);
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