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staging/octeon: Software should check the checksum of no tcp/udp packets
[linux-2.6/linux-mips.git] / drivers / spi / spi-imx.c
blobfa594d604acae4501986125e5ca25f6e2b8e3c22
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/types.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_gpio.h>
40
41 #include <mach/spi.h>
42
43 #define DRIVER_NAME "spi_imx"
44
45 #define MXC_CSPIRXDATA 0x00
46 #define MXC_CSPITXDATA 0x04
47 #define MXC_CSPICTRL 0x08
48 #define MXC_CSPIINT 0x0c
49 #define MXC_RESET 0x1c
50
51 /* generic defines to abstract from the different register layouts */
52 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
55 struct spi_imx_config {
56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
59 u8 cs;
60 };
61
62 enum spi_imx_devtype {
63 IMX1_CSPI,
64 IMX21_CSPI,
65 IMX27_CSPI,
66 IMX31_CSPI,
67 IMX35_CSPI, /* CSPI on all i.mx except above */
68 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
69 };
70
71 struct spi_imx_data;
72
73 struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
78 void (*reset)(struct spi_imx_data *);
79 enum spi_imx_devtype devtype;
80 };
81
82 struct spi_imx_data {
83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
86 void *base;
87 int irq;
88 struct clk *clk;
89 unsigned long spi_clk;
90
91 unsigned int count;
92 void (*tx)(struct spi_imx_data *);
93 void (*rx)(struct spi_imx_data *);
94 void *rx_buf;
95 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */
97
98 struct spi_imx_devtype_data *devtype_data;
99 int chipselect[0];
100 };
101
102 static inline int is_imx27_cspi(struct spi_imx_data *d)
103 {
104 return d->devtype_data->devtype == IMX27_CSPI;
105 }
106
107 static inline int is_imx35_cspi(struct spi_imx_data *d)
108 {
109 return d->devtype_data->devtype == IMX35_CSPI;
110 }
111
112 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
113 {
114 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
115 }
116
117 #define MXC_SPI_BUF_RX(type) \
118 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
119 { \
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
121 \
122 if (spi_imx->rx_buf) { \
123 *(type *)spi_imx->rx_buf = val; \
124 spi_imx->rx_buf += sizeof(type); \
125 } \
126 }
127
128 #define MXC_SPI_BUF_TX(type) \
129 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
130 { \
131 type val = 0; \
132 \
133 if (spi_imx->tx_buf) { \
134 val = *(type *)spi_imx->tx_buf; \
135 spi_imx->tx_buf += sizeof(type); \
136 } \
137 \
138 spi_imx->count -= sizeof(type); \
139 \
140 writel(val, spi_imx->base + MXC_CSPITXDATA); \
141 }
142
143 MXC_SPI_BUF_RX(u8)
144 MXC_SPI_BUF_TX(u8)
145 MXC_SPI_BUF_RX(u16)
146 MXC_SPI_BUF_TX(u16)
147 MXC_SPI_BUF_RX(u32)
148 MXC_SPI_BUF_TX(u32)
149
150 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
151 * (which is currently not the case in this driver)
152 */
153 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
154 256, 384, 512, 768, 1024};
155
156 /* MX21, MX27 */
157 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
158 unsigned int fspi, unsigned int max)
159 {
160 int i;
161
162 for (i = 2; i < max; i++)
163 if (fspi * mxc_clkdivs[i] >= fin)
164 return i;
165
166 return max;
167 }
168
169 /* MX1, MX31, MX35, MX51 CSPI */
170 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
171 unsigned int fspi)
172 {
173 int i, div = 4;
174
175 for (i = 0; i < 7; i++) {
176 if (fspi * div >= fin)
177 return i;
178 div <<= 1;
179 }
180
181 return 7;
182 }
183
184 #define MX51_ECSPI_CTRL 0x08
185 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
186 #define MX51_ECSPI_CTRL_XCH (1 << 2)
187 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
188 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
189 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
190 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
191 #define MX51_ECSPI_CTRL_BL_OFFSET 20
192
193 #define MX51_ECSPI_CONFIG 0x0c
194 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
195 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
196 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
197 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
198
199 #define MX51_ECSPI_INT 0x10
200 #define MX51_ECSPI_INT_TEEN (1 << 0)
201 #define MX51_ECSPI_INT_RREN (1 << 3)
202
203 #define MX51_ECSPI_STAT 0x18
204 #define MX51_ECSPI_STAT_RR (1 << 3)
205
206 /* MX51 eCSPI */
207 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
208 {
209 /*
210 * there are two 4-bit dividers, the pre-divider divides by
211 * $pre, the post-divider by 2^$post
212 */
213 unsigned int pre, post;
214
215 if (unlikely(fspi > fin))
216 return 0;
217
218 post = fls(fin) - fls(fspi);
219 if (fin > fspi << post)
220 post++;
221
222 /* now we have: (fin <= fspi << post) with post being minimal */
223
224 post = max(4U, post) - 4;
225 if (unlikely(post > 0xf)) {
226 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
227 __func__, fspi, fin);
228 return 0xff;
229 }
230
231 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
232
233 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
234 __func__, fin, fspi, post, pre);
235 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
236 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
237 }
238
239 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
240 {
241 unsigned val = 0;
242
243 if (enable & MXC_INT_TE)
244 val |= MX51_ECSPI_INT_TEEN;
245
246 if (enable & MXC_INT_RR)
247 val |= MX51_ECSPI_INT_RREN;
248
249 writel(val, spi_imx->base + MX51_ECSPI_INT);
250 }
251
252 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
253 {
254 u32 reg;
255
256 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
257 reg |= MX51_ECSPI_CTRL_XCH;
258 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
259 }
260
261 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
262 struct spi_imx_config *config)
263 {
264 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
265
266 /*
267 * The hardware seems to have a race condition when changing modes. The
268 * current assumption is that the selection of the channel arrives
269 * earlier in the hardware than the mode bits when they are written at
270 * the same time.
271 * So set master mode for all channels as we do not support slave mode.
272 */
273 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
274
275 /* set clock speed */
276 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
277
278 /* set chip select to use */
279 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
280
281 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
282
283 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
284
285 if (config->mode & SPI_CPHA)
286 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
287
288 if (config->mode & SPI_CPOL)
289 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
290
291 if (config->mode & SPI_CS_HIGH)
292 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
293
294 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
295 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
296
297 return 0;
298 }
299
300 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
301 {
302 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
303 }
304
305 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
306 {
307 /* drain receive buffer */
308 while (mx51_ecspi_rx_available(spi_imx))
309 readl(spi_imx->base + MXC_CSPIRXDATA);
310 }
311
312 #define MX31_INTREG_TEEN (1 << 0)
313 #define MX31_INTREG_RREN (1 << 3)
314
315 #define MX31_CSPICTRL_ENABLE (1 << 0)
316 #define MX31_CSPICTRL_MASTER (1 << 1)
317 #define MX31_CSPICTRL_XCH (1 << 2)
318 #define MX31_CSPICTRL_POL (1 << 4)
319 #define MX31_CSPICTRL_PHA (1 << 5)
320 #define MX31_CSPICTRL_SSCTL (1 << 6)
321 #define MX31_CSPICTRL_SSPOL (1 << 7)
322 #define MX31_CSPICTRL_BC_SHIFT 8
323 #define MX35_CSPICTRL_BL_SHIFT 20
324 #define MX31_CSPICTRL_CS_SHIFT 24
325 #define MX35_CSPICTRL_CS_SHIFT 12
326 #define MX31_CSPICTRL_DR_SHIFT 16
327
328 #define MX31_CSPISTATUS 0x14
329 #define MX31_STATUS_RR (1 << 3)
330
331 /* These functions also work for the i.MX35, but be aware that
332 * the i.MX35 has a slightly different register layout for bits
333 * we do not use here.
334 */
335 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
336 {
337 unsigned int val = 0;
338
339 if (enable & MXC_INT_TE)
340 val |= MX31_INTREG_TEEN;
341 if (enable & MXC_INT_RR)
342 val |= MX31_INTREG_RREN;
343
344 writel(val, spi_imx->base + MXC_CSPIINT);
345 }
346
347 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
348 {
349 unsigned int reg;
350
351 reg = readl(spi_imx->base + MXC_CSPICTRL);
352 reg |= MX31_CSPICTRL_XCH;
353 writel(reg, spi_imx->base + MXC_CSPICTRL);
354 }
355
356 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
357 struct spi_imx_config *config)
358 {
359 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
360 int cs = spi_imx->chipselect[config->cs];
361
362 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
363 MX31_CSPICTRL_DR_SHIFT;
364
365 if (is_imx35_cspi(spi_imx)) {
366 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
367 reg |= MX31_CSPICTRL_SSCTL;
368 } else {
369 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
370 }
371
372 if (config->mode & SPI_CPHA)
373 reg |= MX31_CSPICTRL_PHA;
374 if (config->mode & SPI_CPOL)
375 reg |= MX31_CSPICTRL_POL;
376 if (config->mode & SPI_CS_HIGH)
377 reg |= MX31_CSPICTRL_SSPOL;
378 if (cs < 0)
379 reg |= (cs + 32) <<
380 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
381 MX31_CSPICTRL_CS_SHIFT);
382
383 writel(reg, spi_imx->base + MXC_CSPICTRL);
384
385 return 0;
386 }
387
388 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
389 {
390 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
391 }
392
393 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
394 {
395 /* drain receive buffer */
396 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
397 readl(spi_imx->base + MXC_CSPIRXDATA);
398 }
399
400 #define MX21_INTREG_RR (1 << 4)
401 #define MX21_INTREG_TEEN (1 << 9)
402 #define MX21_INTREG_RREN (1 << 13)
403
404 #define MX21_CSPICTRL_POL (1 << 5)
405 #define MX21_CSPICTRL_PHA (1 << 6)
406 #define MX21_CSPICTRL_SSPOL (1 << 8)
407 #define MX21_CSPICTRL_XCH (1 << 9)
408 #define MX21_CSPICTRL_ENABLE (1 << 10)
409 #define MX21_CSPICTRL_MASTER (1 << 11)
410 #define MX21_CSPICTRL_DR_SHIFT 14
411 #define MX21_CSPICTRL_CS_SHIFT 19
412
413 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
414 {
415 unsigned int val = 0;
416
417 if (enable & MXC_INT_TE)
418 val |= MX21_INTREG_TEEN;
419 if (enable & MXC_INT_RR)
420 val |= MX21_INTREG_RREN;
421
422 writel(val, spi_imx->base + MXC_CSPIINT);
423 }
424
425 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
426 {
427 unsigned int reg;
428
429 reg = readl(spi_imx->base + MXC_CSPICTRL);
430 reg |= MX21_CSPICTRL_XCH;
431 writel(reg, spi_imx->base + MXC_CSPICTRL);
432 }
433
434 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
435 struct spi_imx_config *config)
436 {
437 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
438 int cs = spi_imx->chipselect[config->cs];
439 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
440
441 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
442 MX21_CSPICTRL_DR_SHIFT;
443 reg |= config->bpw - 1;
444
445 if (config->mode & SPI_CPHA)
446 reg |= MX21_CSPICTRL_PHA;
447 if (config->mode & SPI_CPOL)
448 reg |= MX21_CSPICTRL_POL;
449 if (config->mode & SPI_CS_HIGH)
450 reg |= MX21_CSPICTRL_SSPOL;
451 if (cs < 0)
452 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
453
454 writel(reg, spi_imx->base + MXC_CSPICTRL);
455
456 return 0;
457 }
458
459 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
460 {
461 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
462 }
463
464 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
465 {
466 writel(1, spi_imx->base + MXC_RESET);
467 }
468
469 #define MX1_INTREG_RR (1 << 3)
470 #define MX1_INTREG_TEEN (1 << 8)
471 #define MX1_INTREG_RREN (1 << 11)
472
473 #define MX1_CSPICTRL_POL (1 << 4)
474 #define MX1_CSPICTRL_PHA (1 << 5)
475 #define MX1_CSPICTRL_XCH (1 << 8)
476 #define MX1_CSPICTRL_ENABLE (1 << 9)
477 #define MX1_CSPICTRL_MASTER (1 << 10)
478 #define MX1_CSPICTRL_DR_SHIFT 13
479
480 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
481 {
482 unsigned int val = 0;
483
484 if (enable & MXC_INT_TE)
485 val |= MX1_INTREG_TEEN;
486 if (enable & MXC_INT_RR)
487 val |= MX1_INTREG_RREN;
488
489 writel(val, spi_imx->base + MXC_CSPIINT);
490 }
491
492 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
493 {
494 unsigned int reg;
495
496 reg = readl(spi_imx->base + MXC_CSPICTRL);
497 reg |= MX1_CSPICTRL_XCH;
498 writel(reg, spi_imx->base + MXC_CSPICTRL);
499 }
500
501 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
502 struct spi_imx_config *config)
503 {
504 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
505
506 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
507 MX1_CSPICTRL_DR_SHIFT;
508 reg |= config->bpw - 1;
509
510 if (config->mode & SPI_CPHA)
511 reg |= MX1_CSPICTRL_PHA;
512 if (config->mode & SPI_CPOL)
513 reg |= MX1_CSPICTRL_POL;
514
515 writel(reg, spi_imx->base + MXC_CSPICTRL);
516
517 return 0;
518 }
519
520 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
521 {
522 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
523 }
524
525 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
526 {
527 writel(1, spi_imx->base + MXC_RESET);
528 }
529
530 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
531 .intctrl = mx1_intctrl,
532 .config = mx1_config,
533 .trigger = mx1_trigger,
534 .rx_available = mx1_rx_available,
535 .reset = mx1_reset,
536 .devtype = IMX1_CSPI,
537 };
538
539 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
540 .intctrl = mx21_intctrl,
541 .config = mx21_config,
542 .trigger = mx21_trigger,
543 .rx_available = mx21_rx_available,
544 .reset = mx21_reset,
545 .devtype = IMX21_CSPI,
546 };
547
548 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
549 /* i.mx27 cspi shares the functions with i.mx21 one */
550 .intctrl = mx21_intctrl,
551 .config = mx21_config,
552 .trigger = mx21_trigger,
553 .rx_available = mx21_rx_available,
554 .reset = mx21_reset,
555 .devtype = IMX27_CSPI,
556 };
557
558 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
559 .intctrl = mx31_intctrl,
560 .config = mx31_config,
561 .trigger = mx31_trigger,
562 .rx_available = mx31_rx_available,
563 .reset = mx31_reset,
564 .devtype = IMX31_CSPI,
565 };
566
567 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
568 /* i.mx35 and later cspi shares the functions with i.mx31 one */
569 .intctrl = mx31_intctrl,
570 .config = mx31_config,
571 .trigger = mx31_trigger,
572 .rx_available = mx31_rx_available,
573 .reset = mx31_reset,
574 .devtype = IMX35_CSPI,
575 };
576
577 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
578 .intctrl = mx51_ecspi_intctrl,
579 .config = mx51_ecspi_config,
580 .trigger = mx51_ecspi_trigger,
581 .rx_available = mx51_ecspi_rx_available,
582 .reset = mx51_ecspi_reset,
583 .devtype = IMX51_ECSPI,
584 };
585
586 static struct platform_device_id spi_imx_devtype[] = {
587 {
588 .name = "imx1-cspi",
589 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
590 }, {
591 .name = "imx21-cspi",
592 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
593 }, {
594 .name = "imx27-cspi",
595 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
596 }, {
597 .name = "imx31-cspi",
598 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
599 }, {
600 .name = "imx35-cspi",
601 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
602 }, {
603 .name = "imx51-ecspi",
604 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
605 }, {
606 /* sentinel */
607 }
608 };
609
610 static const struct of_device_id spi_imx_dt_ids[] = {
611 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
612 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
613 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
614 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
615 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
616 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
617 { /* sentinel */ }
618 };
619
620 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
621 {
622 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
623 int gpio = spi_imx->chipselect[spi->chip_select];
624 int active = is_active != BITBANG_CS_INACTIVE;
625 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
626
627 if (gpio < 0)
628 return;
629
630 gpio_set_value(gpio, dev_is_lowactive ^ active);
631 }
632
633 static void spi_imx_push(struct spi_imx_data *spi_imx)
634 {
635 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
636 if (!spi_imx->count)
637 break;
638 spi_imx->tx(spi_imx);
639 spi_imx->txfifo++;
640 }
641
642 spi_imx->devtype_data->trigger(spi_imx);
643 }
644
645 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
646 {
647 struct spi_imx_data *spi_imx = dev_id;
648
649 while (spi_imx->devtype_data->rx_available(spi_imx)) {
650 spi_imx->rx(spi_imx);
651 spi_imx->txfifo--;
652 }
653
654 if (spi_imx->count) {
655 spi_imx_push(spi_imx);
656 return IRQ_HANDLED;
657 }
658
659 if (spi_imx->txfifo) {
660 /* No data left to push, but still waiting for rx data,
661 * enable receive data available interrupt.
662 */
663 spi_imx->devtype_data->intctrl(
664 spi_imx, MXC_INT_RR);
665 return IRQ_HANDLED;
666 }
667
668 spi_imx->devtype_data->intctrl(spi_imx, 0);
669 complete(&spi_imx->xfer_done);
670
671 return IRQ_HANDLED;
672 }
673
674 static int spi_imx_setupxfer(struct spi_device *spi,
675 struct spi_transfer *t)
676 {
677 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
678 struct spi_imx_config config;
679
680 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
681 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
682 config.mode = spi->mode;
683 config.cs = spi->chip_select;
684
685 if (!config.speed_hz)
686 config.speed_hz = spi->max_speed_hz;
687 if (!config.bpw)
688 config.bpw = spi->bits_per_word;
689 if (!config.speed_hz)
690 config.speed_hz = spi->max_speed_hz;
691
692 /* Initialize the functions for transfer */
693 if (config.bpw <= 8) {
694 spi_imx->rx = spi_imx_buf_rx_u8;
695 spi_imx->tx = spi_imx_buf_tx_u8;
696 } else if (config.bpw <= 16) {
697 spi_imx->rx = spi_imx_buf_rx_u16;
698 spi_imx->tx = spi_imx_buf_tx_u16;
699 } else if (config.bpw <= 32) {
700 spi_imx->rx = spi_imx_buf_rx_u32;
701 spi_imx->tx = spi_imx_buf_tx_u32;
702 } else
703 BUG();
704
705 spi_imx->devtype_data->config(spi_imx, &config);
706
707 return 0;
708 }
709
710 static int spi_imx_transfer(struct spi_device *spi,
711 struct spi_transfer *transfer)
712 {
713 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
714
715 spi_imx->tx_buf = transfer->tx_buf;
716 spi_imx->rx_buf = transfer->rx_buf;
717 spi_imx->count = transfer->len;
718 spi_imx->txfifo = 0;
719
720 init_completion(&spi_imx->xfer_done);
721
722 spi_imx_push(spi_imx);
723
724 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
725
726 wait_for_completion(&spi_imx->xfer_done);
727
728 return transfer->len;
729 }
730
731 static int spi_imx_setup(struct spi_device *spi)
732 {
733 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
734 int gpio = spi_imx->chipselect[spi->chip_select];
735
736 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
737 spi->mode, spi->bits_per_word, spi->max_speed_hz);
738
739 if (gpio >= 0)
740 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
741
742 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
743
744 return 0;
745 }
746
747 static void spi_imx_cleanup(struct spi_device *spi)
748 {
749 }
750
751 static int __devinit spi_imx_probe(struct platform_device *pdev)
752 {
753 struct device_node *np = pdev->dev.of_node;
754 const struct of_device_id *of_id =
755 of_match_device(spi_imx_dt_ids, &pdev->dev);
756 struct spi_imx_master *mxc_platform_info =
757 dev_get_platdata(&pdev->dev);
758 struct spi_master *master;
759 struct spi_imx_data *spi_imx;
760 struct resource *res;
761 int i, ret, num_cs;
762
763 if (!np && !mxc_platform_info) {
764 dev_err(&pdev->dev, "can't get the platform data\n");
765 return -EINVAL;
766 }
767
768 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
769 if (ret < 0)
770 num_cs = mxc_platform_info->num_chipselect;
771
772 master = spi_alloc_master(&pdev->dev,
773 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
774 if (!master)
775 return -ENOMEM;
776
777 platform_set_drvdata(pdev, master);
778
779 master->bus_num = pdev->id;
780 master->num_chipselect = num_cs;
781
782 spi_imx = spi_master_get_devdata(master);
783 spi_imx->bitbang.master = spi_master_get(master);
784
785 for (i = 0; i < master->num_chipselect; i++) {
786 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
787 if (cs_gpio < 0)
788 cs_gpio = mxc_platform_info->chipselect[i];
789
790 spi_imx->chipselect[i] = cs_gpio;
791 if (cs_gpio < 0)
792 continue;
793
794 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
795 if (ret) {
796 while (i > 0) {
797 i--;
798 if (spi_imx->chipselect[i] >= 0)
799 gpio_free(spi_imx->chipselect[i]);
800 }
801 dev_err(&pdev->dev, "can't get cs gpios\n");
802 goto out_master_put;
803 }
804 }
805
806 spi_imx->bitbang.chipselect = spi_imx_chipselect;
807 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
808 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
809 spi_imx->bitbang.master->setup = spi_imx_setup;
810 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
811 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
812
813 init_completion(&spi_imx->xfer_done);
814
815 spi_imx->devtype_data = of_id ? of_id->data :
816 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
817
818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 if (!res) {
820 dev_err(&pdev->dev, "can't get platform resource\n");
821 ret = -ENOMEM;
822 goto out_gpio_free;
823 }
824
825 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
826 dev_err(&pdev->dev, "request_mem_region failed\n");
827 ret = -EBUSY;
828 goto out_gpio_free;
829 }
830
831 spi_imx->base = ioremap(res->start, resource_size(res));
832 if (!spi_imx->base) {
833 ret = -EINVAL;
834 goto out_release_mem;
835 }
836
837 spi_imx->irq = platform_get_irq(pdev, 0);
838 if (spi_imx->irq < 0) {
839 ret = -EINVAL;
840 goto out_iounmap;
841 }
842
843 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
844 if (ret) {
845 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
846 goto out_iounmap;
847 }
848
849 spi_imx->clk = clk_get(&pdev->dev, NULL);
850 if (IS_ERR(spi_imx->clk)) {
851 dev_err(&pdev->dev, "unable to get clock\n");
852 ret = PTR_ERR(spi_imx->clk);
853 goto out_free_irq;
854 }
855
856 clk_enable(spi_imx->clk);
857 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
858
859 spi_imx->devtype_data->reset(spi_imx);
860
861 spi_imx->devtype_data->intctrl(spi_imx, 0);
862
863 master->dev.of_node = pdev->dev.of_node;
864 ret = spi_bitbang_start(&spi_imx->bitbang);
865 if (ret) {
866 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
867 goto out_clk_put;
868 }
869
870 dev_info(&pdev->dev, "probed\n");
871
872 return ret;
873
874 out_clk_put:
875 clk_disable(spi_imx->clk);
876 clk_put(spi_imx->clk);
877 out_free_irq:
878 free_irq(spi_imx->irq, spi_imx);
879 out_iounmap:
880 iounmap(spi_imx->base);
881 out_release_mem:
882 release_mem_region(res->start, resource_size(res));
883 out_gpio_free:
884 for (i = 0; i < master->num_chipselect; i++)
885 if (spi_imx->chipselect[i] >= 0)
886 gpio_free(spi_imx->chipselect[i]);
887 out_master_put:
888 spi_master_put(master);
889 kfree(master);
890 platform_set_drvdata(pdev, NULL);
891 return ret;
892 }
893
894 static int __devexit spi_imx_remove(struct platform_device *pdev)
895 {
896 struct spi_master *master = platform_get_drvdata(pdev);
897 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
899 int i;
900
901 spi_bitbang_stop(&spi_imx->bitbang);
902
903 writel(0, spi_imx->base + MXC_CSPICTRL);
904 clk_disable(spi_imx->clk);
905 clk_put(spi_imx->clk);
906 free_irq(spi_imx->irq, spi_imx);
907 iounmap(spi_imx->base);
908
909 for (i = 0; i < master->num_chipselect; i++)
910 if (spi_imx->chipselect[i] >= 0)
911 gpio_free(spi_imx->chipselect[i]);
912
913 spi_master_put(master);
914
915 release_mem_region(res->start, resource_size(res));
916
917 platform_set_drvdata(pdev, NULL);
918
919 return 0;
920 }
921
922 static struct platform_driver spi_imx_driver = {
923 .driver = {
924 .name = DRIVER_NAME,
925 .owner = THIS_MODULE,
926 .of_match_table = spi_imx_dt_ids,
927 },
928 .id_table = spi_imx_devtype,
929 .probe = spi_imx_probe,
930 .remove = __devexit_p(spi_imx_remove),
931 };
932
933 static int __init spi_imx_init(void)
934 {
935 return platform_driver_register(&spi_imx_driver);
936 }
937
938 static void __exit spi_imx_exit(void)
939 {
940 platform_driver_unregister(&spi_imx_driver);
941 }
942
943 module_init(spi_imx_init);
944 module_exit(spi_imx_exit);
945
946 MODULE_DESCRIPTION("SPI Master Controller driver");
947 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
948 MODULE_LICENSE("GPL");
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