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staging/octeon: Software should check the checksum of no tcp/udp packets
[linux-2.6/linux-mips.git] / drivers / spi / spi-topcliff-pch.c
blob1d23f38318663dfd7682131524d0af179c3ee909
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33
34 /* Register offsets */
35 #define PCH_SPCR 0x00 /* SPI control register */
36 #define PCH_SPBRR 0x04 /* SPI baud rate register */
37 #define PCH_SPSR 0x08 /* SPI status register */
38 #define PCH_SPDWR 0x0C /* SPI write data register */
39 #define PCH_SPDRR 0x10 /* SPI read data register */
40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
41 #define PCH_SRST 0x1C /* SPI reset register */
42 #define PCH_ADDRESS_SIZE 0x20
43
44 #define PCH_SPSR_TFD 0x000007C0
45 #define PCH_SPSR_RFD 0x0000F800
46
47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
49
50 #define PCH_RX_THOLD 7
51 #define PCH_RX_THOLD_MAX 15
52
53 #define PCH_MAX_BAUDRATE 5000000
54 #define PCH_MAX_FIFO_DEPTH 16
55
56 #define STATUS_RUNNING 1
57 #define STATUS_EXITING 2
58 #define PCH_SLEEP_TIME 10
59
60 #define SSN_LOW 0x02U
61 #define SSN_NO_CONTROL 0x00U
62 #define PCH_MAX_CS 0xFF
63 #define PCI_DEVICE_ID_GE_SPI 0x8816
64
65 #define SPCR_SPE_BIT (1 << 0)
66 #define SPCR_MSTR_BIT (1 << 1)
67 #define SPCR_LSBF_BIT (1 << 4)
68 #define SPCR_CPHA_BIT (1 << 5)
69 #define SPCR_CPOL_BIT (1 << 6)
70 #define SPCR_TFIE_BIT (1 << 8)
71 #define SPCR_RFIE_BIT (1 << 9)
72 #define SPCR_FIE_BIT (1 << 10)
73 #define SPCR_ORIE_BIT (1 << 11)
74 #define SPCR_MDFIE_BIT (1 << 12)
75 #define SPCR_FICLR_BIT (1 << 24)
76 #define SPSR_TFI_BIT (1 << 0)
77 #define SPSR_RFI_BIT (1 << 1)
78 #define SPSR_FI_BIT (1 << 2)
79 #define SPSR_ORF_BIT (1 << 3)
80 #define SPBRR_SIZE_BIT (1 << 10)
81
82 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
83 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
84
85 #define SPCR_RFIC_FIELD 20
86 #define SPCR_TFIC_FIELD 16
87
88 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
89 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
90 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
91
92 #define PCH_CLOCK_HZ 50000000
93 #define PCH_MAX_SPBR 1023
94
95 /* Definition for ML7213 by OKI SEMICONDUCTOR */
96 #define PCI_VENDOR_ID_ROHM 0x10DB
97 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
98 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
99
100 /*
101 * Set the number of SPI instance max
102 * Intel EG20T PCH : 1ch
103 * OKI SEMICONDUCTOR ML7213 IOH : 2ch
104 * OKI SEMICONDUCTOR ML7223 IOH : 1ch
105 */
106 #define PCH_SPI_MAX_DEV 2
107
108 #define PCH_BUF_SIZE 4096
109 #define PCH_DMA_TRANS_SIZE 12
110
111 static int use_dma = 1;
112
113 struct pch_spi_dma_ctrl {
114 struct dma_async_tx_descriptor *desc_tx;
115 struct dma_async_tx_descriptor *desc_rx;
116 struct pch_dma_slave param_tx;
117 struct pch_dma_slave param_rx;
118 struct dma_chan *chan_tx;
119 struct dma_chan *chan_rx;
120 struct scatterlist *sg_tx_p;
121 struct scatterlist *sg_rx_p;
122 struct scatterlist sg_tx;
123 struct scatterlist sg_rx;
124 int nent;
125 void *tx_buf_virt;
126 void *rx_buf_virt;
127 dma_addr_t tx_buf_dma;
128 dma_addr_t rx_buf_dma;
129 };
130 /**
131 * struct pch_spi_data - Holds the SPI channel specific details
132 * @io_remap_addr: The remapped PCI base address
133 * @master: Pointer to the SPI master structure
134 * @work: Reference to work queue handler
135 * @wk: Workqueue for carrying out execution of the
136 * requests
137 * @wait: Wait queue for waking up upon receiving an
138 * interrupt.
139 * @transfer_complete: Status of SPI Transfer
140 * @bcurrent_msg_processing: Status flag for message processing
141 * @lock: Lock for protecting this structure
142 * @queue: SPI Message queue
143 * @status: Status of the SPI driver
144 * @bpw_len: Length of data to be transferred in bits per
145 * word
146 * @transfer_active: Flag showing active transfer
147 * @tx_index: Transmit data count; for bookkeeping during
148 * transfer
149 * @rx_index: Receive data count; for bookkeeping during
150 * transfer
151 * @tx_buff: Buffer for data to be transmitted
152 * @rx_index: Buffer for Received data
153 * @n_curnt_chip: The chip number that this SPI driver currently
154 * operates on
155 * @current_chip: Reference to the current chip that this SPI
156 * driver currently operates on
157 * @current_msg: The current message that this SPI driver is
158 * handling
159 * @cur_trans: The current transfer that this SPI driver is
160 * handling
161 * @board_dat: Reference to the SPI device data structure
162 * @plat_dev: platform_device structure
163 * @ch: SPI channel number
164 * @irq_reg_sts: Status of IRQ registration
165 */
166 struct pch_spi_data {
167 void __iomem *io_remap_addr;
168 unsigned long io_base_addr;
169 struct spi_master *master;
170 struct work_struct work;
171 struct workqueue_struct *wk;
172 wait_queue_head_t wait;
173 u8 transfer_complete;
174 u8 bcurrent_msg_processing;
175 spinlock_t lock;
176 struct list_head queue;
177 u8 status;
178 u32 bpw_len;
179 u8 transfer_active;
180 u32 tx_index;
181 u32 rx_index;
182 u16 *pkt_tx_buff;
183 u16 *pkt_rx_buff;
184 u8 n_curnt_chip;
185 struct spi_device *current_chip;
186 struct spi_message *current_msg;
187 struct spi_transfer *cur_trans;
188 struct pch_spi_board_data *board_dat;
189 struct platform_device *plat_dev;
190 int ch;
191 struct pch_spi_dma_ctrl dma;
192 int use_dma;
193 u8 irq_reg_sts;
194 };
195
196 /**
197 * struct pch_spi_board_data - Holds the SPI device specific details
198 * @pdev: Pointer to the PCI device
199 * @suspend_sts: Status of suspend
200 * @num: The number of SPI device instance
201 */
202 struct pch_spi_board_data {
203 struct pci_dev *pdev;
204 u8 suspend_sts;
205 int num;
206 };
207
208 struct pch_pd_dev_save {
209 int num;
210 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
211 struct pch_spi_board_data *board_dat;
212 };
213
214 static struct pci_device_id pch_spi_pcidev_id[] = {
215 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
216 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
217 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
218 { }
219 };
220
221 /**
222 * pch_spi_writereg() - Performs register writes
223 * @master: Pointer to struct spi_master.
224 * @idx: Register offset.
225 * @val: Value to be written to register.
226 */
227 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
228 {
229 struct pch_spi_data *data = spi_master_get_devdata(master);
230 iowrite32(val, (data->io_remap_addr + idx));
231 }
232
233 /**
234 * pch_spi_readreg() - Performs register reads
235 * @master: Pointer to struct spi_master.
236 * @idx: Register offset.
237 */
238 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
239 {
240 struct pch_spi_data *data = spi_master_get_devdata(master);
241 return ioread32(data->io_remap_addr + idx);
242 }
243
244 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
245 u32 set, u32 clr)
246 {
247 u32 tmp = pch_spi_readreg(master, idx);
248 tmp = (tmp & ~clr) | set;
249 pch_spi_writereg(master, idx, tmp);
250 }
251
252 static void pch_spi_set_master_mode(struct spi_master *master)
253 {
254 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
255 }
256
257 /**
258 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
259 * @master: Pointer to struct spi_master.
260 */
261 static void pch_spi_clear_fifo(struct spi_master *master)
262 {
263 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
264 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
265 }
266
267 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
268 void __iomem *io_remap_addr)
269 {
270 u32 n_read, tx_index, rx_index, bpw_len;
271 u16 *pkt_rx_buffer, *pkt_tx_buff;
272 int read_cnt;
273 u32 reg_spcr_val;
274 void __iomem *spsr;
275 void __iomem *spdrr;
276 void __iomem *spdwr;
277
278 spsr = io_remap_addr + PCH_SPSR;
279 iowrite32(reg_spsr_val, spsr);
280
281 if (data->transfer_active) {
282 rx_index = data->rx_index;
283 tx_index = data->tx_index;
284 bpw_len = data->bpw_len;
285 pkt_rx_buffer = data->pkt_rx_buff;
286 pkt_tx_buff = data->pkt_tx_buff;
287
288 spdrr = io_remap_addr + PCH_SPDRR;
289 spdwr = io_remap_addr + PCH_SPDWR;
290
291 n_read = PCH_READABLE(reg_spsr_val);
292
293 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
294 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
295 if (tx_index < bpw_len)
296 iowrite32(pkt_tx_buff[tx_index++], spdwr);
297 }
298
299 /* disable RFI if not needed */
300 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
301 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
302 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
303
304 /* reset rx threshold */
305 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
306 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
307
308 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
309 }
310
311 /* update counts */
312 data->tx_index = tx_index;
313 data->rx_index = rx_index;
314
315 }
316
317 /* if transfer complete interrupt */
318 if (reg_spsr_val & SPSR_FI_BIT) {
319 if (tx_index < bpw_len)
320 dev_err(&data->master->dev,
321 "%s : Transfer is not completed", __func__);
322 /* disable interrupts */
323 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
324
325 /* transfer is completed;inform pch_spi_process_messages */
326 data->transfer_complete = true;
327 data->transfer_active = false;
328 wake_up(&data->wait);
329 }
330 }
331
332 /**
333 * pch_spi_handler() - Interrupt handler
334 * @irq: The interrupt number.
335 * @dev_id: Pointer to struct pch_spi_board_data.
336 */
337 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
338 {
339 u32 reg_spsr_val;
340 void __iomem *spsr;
341 void __iomem *io_remap_addr;
342 irqreturn_t ret = IRQ_NONE;
343 struct pch_spi_data *data = dev_id;
344 struct pch_spi_board_data *board_dat = data->board_dat;
345
346 if (board_dat->suspend_sts) {
347 dev_dbg(&board_dat->pdev->dev,
348 "%s returning due to suspend\n", __func__);
349 return IRQ_NONE;
350 }
351 if (data->use_dma)
352 return IRQ_NONE;
353
354 io_remap_addr = data->io_remap_addr;
355 spsr = io_remap_addr + PCH_SPSR;
356
357 reg_spsr_val = ioread32(spsr);
358
359 if (reg_spsr_val & SPSR_ORF_BIT)
360 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
361
362 /* Check if the interrupt is for SPI device */
363 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
364 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
365 ret = IRQ_HANDLED;
366 }
367
368 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
369 __func__, ret);
370
371 return ret;
372 }
373
374 /**
375 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
376 * @master: Pointer to struct spi_master.
377 * @speed_hz: Baud rate.
378 */
379 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
380 {
381 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
382
383 /* if baud rate is less than we can support limit it */
384 if (n_spbr > PCH_MAX_SPBR)
385 n_spbr = PCH_MAX_SPBR;
386
387 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
388 }
389
390 /**
391 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
392 * @master: Pointer to struct spi_master.
393 * @bits_per_word: Bits per word for SPI transfer.
394 */
395 static void pch_spi_set_bits_per_word(struct spi_master *master,
396 u8 bits_per_word)
397 {
398 if (bits_per_word == 8)
399 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
400 else
401 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
402 }
403
404 /**
405 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
406 * @spi: Pointer to struct spi_device.
407 */
408 static void pch_spi_setup_transfer(struct spi_device *spi)
409 {
410 u32 flags = 0;
411
412 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
413 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
414 spi->max_speed_hz);
415 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
416
417 /* set bits per word */
418 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
419
420 if (!(spi->mode & SPI_LSB_FIRST))
421 flags |= SPCR_LSBF_BIT;
422 if (spi->mode & SPI_CPOL)
423 flags |= SPCR_CPOL_BIT;
424 if (spi->mode & SPI_CPHA)
425 flags |= SPCR_CPHA_BIT;
426 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
427 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
428
429 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
430 pch_spi_clear_fifo(spi->master);
431 }
432
433 /**
434 * pch_spi_reset() - Clears SPI registers
435 * @master: Pointer to struct spi_master.
436 */
437 static void pch_spi_reset(struct spi_master *master)
438 {
439 /* write 1 to reset SPI */
440 pch_spi_writereg(master, PCH_SRST, 0x1);
441
442 /* clear reset */
443 pch_spi_writereg(master, PCH_SRST, 0x0);
444 }
445
446 static int pch_spi_setup(struct spi_device *pspi)
447 {
448 /* check bits per word */
449 if (pspi->bits_per_word == 0) {
450 pspi->bits_per_word = 8;
451 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
452 }
453
454 if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
455 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
456 return -EINVAL;
457 }
458
459 /* Check baud rate setting */
460 /* if baud rate of chip is greater than
461 max we can support,return error */
462 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
463 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
464
465 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
466 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
467
468 return 0;
469 }
470
471 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
472 {
473
474 struct spi_transfer *transfer;
475 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
476 int retval;
477 unsigned long flags;
478
479 /* validate spi message and baud rate */
480 if (unlikely(list_empty(&pmsg->transfers) == 1)) {
481 dev_err(&pspi->dev, "%s list empty\n", __func__);
482 retval = -EINVAL;
483 goto err_out;
484 }
485
486 if (unlikely(pspi->max_speed_hz == 0)) {
487 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
488 __func__, pspi->max_speed_hz);
489 retval = -EINVAL;
490 goto err_out;
491 }
492
493 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
494 "Transfer Speed is set.\n", __func__);
495
496 spin_lock_irqsave(&data->lock, flags);
497 /* validate Tx/Rx buffers and Transfer length */
498 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
499 if (!transfer->tx_buf && !transfer->rx_buf) {
500 dev_err(&pspi->dev,
501 "%s Tx and Rx buffer NULL\n", __func__);
502 retval = -EINVAL;
503 goto err_return_spinlock;
504 }
505
506 if (!transfer->len) {
507 dev_err(&pspi->dev, "%s Transfer length invalid\n",
508 __func__);
509 retval = -EINVAL;
510 goto err_return_spinlock;
511 }
512
513 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
514 " valid\n", __func__);
515
516 /* if baud rate has been specified validate the same */
517 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
518 transfer->speed_hz = PCH_MAX_BAUDRATE;
519
520 /* if bits per word has been specified validate the same */
521 if (transfer->bits_per_word) {
522 if ((transfer->bits_per_word != 8)
523 && (transfer->bits_per_word != 16)) {
524 retval = -EINVAL;
525 dev_err(&pspi->dev,
526 "%s Invalid bits per word\n", __func__);
527 goto err_return_spinlock;
528 }
529 }
530 }
531 spin_unlock_irqrestore(&data->lock, flags);
532
533 /* We won't process any messages if we have been asked to terminate */
534 if (data->status == STATUS_EXITING) {
535 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
536 retval = -ESHUTDOWN;
537 goto err_out;
538 }
539
540 /* If suspended ,return -EINVAL */
541 if (data->board_dat->suspend_sts) {
542 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
543 retval = -EINVAL;
544 goto err_out;
545 }
546
547 /* set status of message */
548 pmsg->actual_length = 0;
549 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
550
551 pmsg->status = -EINPROGRESS;
552 spin_lock_irqsave(&data->lock, flags);
553 /* add message to queue */
554 list_add_tail(&pmsg->queue, &data->queue);
555 spin_unlock_irqrestore(&data->lock, flags);
556
557 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
558
559 /* schedule work queue to run */
560 queue_work(data->wk, &data->work);
561 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
562
563 retval = 0;
564
565 err_out:
566 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
567 return retval;
568 err_return_spinlock:
569 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
570 spin_unlock_irqrestore(&data->lock, flags);
571 return retval;
572 }
573
574 static inline void pch_spi_select_chip(struct pch_spi_data *data,
575 struct spi_device *pspi)
576 {
577 if (data->current_chip != NULL) {
578 if (pspi->chip_select != data->n_curnt_chip) {
579 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
580 data->current_chip = NULL;
581 }
582 }
583
584 data->current_chip = pspi;
585
586 data->n_curnt_chip = data->current_chip->chip_select;
587
588 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
589 pch_spi_setup_transfer(pspi);
590 }
591
592 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
593 {
594 int size;
595 u32 n_writes;
596 int j;
597 struct spi_message *pmsg;
598 const u8 *tx_buf;
599 const u16 *tx_sbuf;
600
601 /* set baud rate if needed */
602 if (data->cur_trans->speed_hz) {
603 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
604 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
605 }
606
607 /* set bits per word if needed */
608 if (data->cur_trans->bits_per_word &&
609 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
610 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
611 pch_spi_set_bits_per_word(data->master,
612 data->cur_trans->bits_per_word);
613 *bpw = data->cur_trans->bits_per_word;
614 } else {
615 *bpw = data->current_msg->spi->bits_per_word;
616 }
617
618 /* reset Tx/Rx index */
619 data->tx_index = 0;
620 data->rx_index = 0;
621
622 data->bpw_len = data->cur_trans->len / (*bpw / 8);
623
624 /* find alloc size */
625 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
626
627 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
628 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
629 if (data->pkt_tx_buff != NULL) {
630 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
631 if (!data->pkt_rx_buff)
632 kfree(data->pkt_tx_buff);
633 }
634
635 if (!data->pkt_rx_buff) {
636 /* flush queue and set status of all transfers to -ENOMEM */
637 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
638 list_for_each_entry(pmsg, data->queue.next, queue) {
639 pmsg->status = -ENOMEM;
640
641 if (pmsg->complete != 0)
642 pmsg->complete(pmsg->context);
643
644 /* delete from queue */
645 list_del_init(&pmsg->queue);
646 }
647 return;
648 }
649
650 /* copy Tx Data */
651 if (data->cur_trans->tx_buf != NULL) {
652 if (*bpw == 8) {
653 tx_buf = data->cur_trans->tx_buf;
654 for (j = 0; j < data->bpw_len; j++)
655 data->pkt_tx_buff[j] = *tx_buf++;
656 } else {
657 tx_sbuf = data->cur_trans->tx_buf;
658 for (j = 0; j < data->bpw_len; j++)
659 data->pkt_tx_buff[j] = *tx_sbuf++;
660 }
661 }
662
663 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
664 n_writes = data->bpw_len;
665 if (n_writes > PCH_MAX_FIFO_DEPTH)
666 n_writes = PCH_MAX_FIFO_DEPTH;
667
668 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
669 "0x2 to SSNXCR\n", __func__);
670 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
671
672 for (j = 0; j < n_writes; j++)
673 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
674
675 /* update tx_index */
676 data->tx_index = j;
677
678 /* reset transfer complete flag */
679 data->transfer_complete = false;
680 data->transfer_active = true;
681 }
682
683 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
684 {
685 struct spi_message *pmsg;
686 dev_dbg(&data->master->dev, "%s called\n", __func__);
687 /* Invoke complete callback
688 * [To the spi core..indicating end of transfer] */
689 data->current_msg->status = 0;
690
691 if (data->current_msg->complete != 0) {
692 dev_dbg(&data->master->dev,
693 "%s:Invoking callback of SPI core\n", __func__);
694 data->current_msg->complete(data->current_msg->context);
695 }
696
697 /* update status in global variable */
698 data->bcurrent_msg_processing = false;
699
700 dev_dbg(&data->master->dev,
701 "%s:data->bcurrent_msg_processing = false\n", __func__);
702
703 data->current_msg = NULL;
704 data->cur_trans = NULL;
705
706 /* check if we have items in list and not suspending
707 * return 1 if list empty */
708 if ((list_empty(&data->queue) == 0) &&
709 (!data->board_dat->suspend_sts) &&
710 (data->status != STATUS_EXITING)) {
711 /* We have some more work to do (either there is more tranint
712 * bpw;sfer requests in the current message or there are
713 *more messages)
714 */
715 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
716 queue_work(data->wk, &data->work);
717 } else if (data->board_dat->suspend_sts ||
718 data->status == STATUS_EXITING) {
719 dev_dbg(&data->master->dev,
720 "%s suspend/remove initiated, flushing queue\n",
721 __func__);
722 list_for_each_entry(pmsg, data->queue.next, queue) {
723 pmsg->status = -EIO;
724
725 if (pmsg->complete)
726 pmsg->complete(pmsg->context);
727
728 /* delete from queue */
729 list_del_init(&pmsg->queue);
730 }
731 }
732 }
733
734 static void pch_spi_set_ir(struct pch_spi_data *data)
735 {
736 /* enable interrupts, set threshold, enable SPI */
737 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
738 /* set receive threshold to PCH_RX_THOLD */
739 pch_spi_setclr_reg(data->master, PCH_SPCR,
740 PCH_RX_THOLD << SPCR_RFIC_FIELD |
741 SPCR_FIE_BIT | SPCR_RFIE_BIT |
742 SPCR_ORIE_BIT | SPCR_SPE_BIT,
743 MASK_RFIC_SPCR_BITS | PCH_ALL);
744 else
745 /* set receive threshold to maximum */
746 pch_spi_setclr_reg(data->master, PCH_SPCR,
747 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
748 SPCR_FIE_BIT | SPCR_ORIE_BIT |
749 SPCR_SPE_BIT,
750 MASK_RFIC_SPCR_BITS | PCH_ALL);
751
752 /* Wait until the transfer completes; go to sleep after
753 initiating the transfer. */
754 dev_dbg(&data->master->dev,
755 "%s:waiting for transfer to get over\n", __func__);
756
757 wait_event_interruptible(data->wait, data->transfer_complete);
758
759 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
760 dev_dbg(&data->master->dev,
761 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
762
763 /* clear all interrupts */
764 pch_spi_writereg(data->master, PCH_SPSR,
765 pch_spi_readreg(data->master, PCH_SPSR));
766 /* Disable interrupts and SPI transfer */
767 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
768 /* clear FIFO */
769 pch_spi_clear_fifo(data->master);
770 }
771
772 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
773 {
774 int j;
775 u8 *rx_buf;
776 u16 *rx_sbuf;
777
778 /* copy Rx Data */
779 if (!data->cur_trans->rx_buf)
780 return;
781
782 if (bpw == 8) {
783 rx_buf = data->cur_trans->rx_buf;
784 for (j = 0; j < data->bpw_len; j++)
785 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
786 } else {
787 rx_sbuf = data->cur_trans->rx_buf;
788 for (j = 0; j < data->bpw_len; j++)
789 *rx_sbuf++ = data->pkt_rx_buff[j];
790 }
791 }
792
793 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
794 {
795 int j;
796 u8 *rx_buf;
797 u16 *rx_sbuf;
798 const u8 *rx_dma_buf;
799 const u16 *rx_dma_sbuf;
800
801 /* copy Rx Data */
802 if (!data->cur_trans->rx_buf)
803 return;
804
805 if (bpw == 8) {
806 rx_buf = data->cur_trans->rx_buf;
807 rx_dma_buf = data->dma.rx_buf_virt;
808 for (j = 0; j < data->bpw_len; j++)
809 *rx_buf++ = *rx_dma_buf++ & 0xFF;
810 } else {
811 rx_sbuf = data->cur_trans->rx_buf;
812 rx_dma_sbuf = data->dma.rx_buf_virt;
813 for (j = 0; j < data->bpw_len; j++)
814 *rx_sbuf++ = *rx_dma_sbuf++;
815 }
816 }
817
818 static void pch_spi_start_transfer(struct pch_spi_data *data)
819 {
820 struct pch_spi_dma_ctrl *dma;
821 unsigned long flags;
822
823 dma = &data->dma;
824
825 spin_lock_irqsave(&data->lock, flags);
826
827 /* disable interrupts, SPI set enable */
828 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
829
830 spin_unlock_irqrestore(&data->lock, flags);
831
832 /* Wait until the transfer completes; go to sleep after
833 initiating the transfer. */
834 dev_dbg(&data->master->dev,
835 "%s:waiting for transfer to get over\n", __func__);
836 wait_event_interruptible(data->wait, data->transfer_complete);
837
838 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
839 DMA_FROM_DEVICE);
840 async_tx_ack(dma->desc_rx);
841 async_tx_ack(dma->desc_tx);
842 kfree(dma->sg_tx_p);
843 kfree(dma->sg_rx_p);
844
845 spin_lock_irqsave(&data->lock, flags);
846 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
847 dev_dbg(&data->master->dev,
848 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
849
850 /* clear fifo threshold, disable interrupts, disable SPI transfer */
851 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
852 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
853 SPCR_SPE_BIT);
854 /* clear all interrupts */
855 pch_spi_writereg(data->master, PCH_SPSR,
856 pch_spi_readreg(data->master, PCH_SPSR));
857 /* clear FIFO */
858 pch_spi_clear_fifo(data->master);
859
860 spin_unlock_irqrestore(&data->lock, flags);
861 }
862
863 static void pch_dma_rx_complete(void *arg)
864 {
865 struct pch_spi_data *data = arg;
866
867 /* transfer is completed;inform pch_spi_process_messages_dma */
868 data->transfer_complete = true;
869 wake_up_interruptible(&data->wait);
870 }
871
872 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
873 {
874 struct pch_dma_slave *param = slave;
875
876 if ((chan->chan_id == param->chan_id) &&
877 (param->dma_dev == chan->device->dev)) {
878 chan->private = param;
879 return true;
880 } else {
881 return false;
882 }
883 }
884
885 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
886 {
887 dma_cap_mask_t mask;
888 struct dma_chan *chan;
889 struct pci_dev *dma_dev;
890 struct pch_dma_slave *param;
891 struct pch_spi_dma_ctrl *dma;
892 unsigned int width;
893
894 if (bpw == 8)
895 width = PCH_DMA_WIDTH_1_BYTE;
896 else
897 width = PCH_DMA_WIDTH_2_BYTES;
898
899 dma = &data->dma;
900 dma_cap_zero(mask);
901 dma_cap_set(DMA_SLAVE, mask);
902
903 /* Get DMA's dev information */
904 dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
905
906 /* Set Tx DMA */
907 param = &dma->param_tx;
908 param->dma_dev = &dma_dev->dev;
909 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
910 param->tx_reg = data->io_base_addr + PCH_SPDWR;
911 param->width = width;
912 chan = dma_request_channel(mask, pch_spi_filter, param);
913 if (!chan) {
914 dev_err(&data->master->dev,
915 "ERROR: dma_request_channel FAILS(Tx)\n");
916 data->use_dma = 0;
917 return;
918 }
919 dma->chan_tx = chan;
920
921 /* Set Rx DMA */
922 param = &dma->param_rx;
923 param->dma_dev = &dma_dev->dev;
924 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
925 param->rx_reg = data->io_base_addr + PCH_SPDRR;
926 param->width = width;
927 chan = dma_request_channel(mask, pch_spi_filter, param);
928 if (!chan) {
929 dev_err(&data->master->dev,
930 "ERROR: dma_request_channel FAILS(Rx)\n");
931 dma_release_channel(dma->chan_tx);
932 dma->chan_tx = NULL;
933 data->use_dma = 0;
934 return;
935 }
936 dma->chan_rx = chan;
937 }
938
939 static void pch_spi_release_dma(struct pch_spi_data *data)
940 {
941 struct pch_spi_dma_ctrl *dma;
942
943 dma = &data->dma;
944 if (dma->chan_tx) {
945 dma_release_channel(dma->chan_tx);
946 dma->chan_tx = NULL;
947 }
948 if (dma->chan_rx) {
949 dma_release_channel(dma->chan_rx);
950 dma->chan_rx = NULL;
951 }
952 return;
953 }
954
955 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
956 {
957 const u8 *tx_buf;
958 const u16 *tx_sbuf;
959 u8 *tx_dma_buf;
960 u16 *tx_dma_sbuf;
961 struct scatterlist *sg;
962 struct dma_async_tx_descriptor *desc_tx;
963 struct dma_async_tx_descriptor *desc_rx;
964 int num;
965 int i;
966 int size;
967 int rem;
968 unsigned long flags;
969 struct pch_spi_dma_ctrl *dma;
970
971 dma = &data->dma;
972
973 /* set baud rate if needed */
974 if (data->cur_trans->speed_hz) {
975 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
976 spin_lock_irqsave(&data->lock, flags);
977 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
978 spin_unlock_irqrestore(&data->lock, flags);
979 }
980
981 /* set bits per word if needed */
982 if (data->cur_trans->bits_per_word &&
983 (data->current_msg->spi->bits_per_word !=
984 data->cur_trans->bits_per_word)) {
985 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
986 spin_lock_irqsave(&data->lock, flags);
987 pch_spi_set_bits_per_word(data->master,
988 data->cur_trans->bits_per_word);
989 spin_unlock_irqrestore(&data->lock, flags);
990 *bpw = data->cur_trans->bits_per_word;
991 } else {
992 *bpw = data->current_msg->spi->bits_per_word;
993 }
994 data->bpw_len = data->cur_trans->len / (*bpw / 8);
995
996 /* copy Tx Data */
997 if (data->cur_trans->tx_buf != NULL) {
998 if (*bpw == 8) {
999 tx_buf = data->cur_trans->tx_buf;
1000 tx_dma_buf = dma->tx_buf_virt;
1001 for (i = 0; i < data->bpw_len; i++)
1002 *tx_dma_buf++ = *tx_buf++;
1003 } else {
1004 tx_sbuf = data->cur_trans->tx_buf;
1005 tx_dma_sbuf = dma->tx_buf_virt;
1006 for (i = 0; i < data->bpw_len; i++)
1007 *tx_dma_sbuf++ = *tx_sbuf++;
1008 }
1009 }
1010 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1011 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1012 size = PCH_DMA_TRANS_SIZE;
1013 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1014 } else {
1015 num = 1;
1016 size = data->bpw_len;
1017 rem = data->bpw_len;
1018 }
1019 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1020 __func__, num, size, rem);
1021 spin_lock_irqsave(&data->lock, flags);
1022
1023 /* set receive fifo threshold and transmit fifo threshold */
1024 pch_spi_setclr_reg(data->master, PCH_SPCR,
1025 ((size - 1) << SPCR_RFIC_FIELD) |
1026 ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1027 SPCR_TFIC_FIELD),
1028 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1029
1030 spin_unlock_irqrestore(&data->lock, flags);
1031
1032 /* RX */
1033 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1034 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1035 /* offset, length setting */
1036 sg = dma->sg_rx_p;
1037 for (i = 0; i < num; i++, sg++) {
1038 if (i == 0) {
1039 sg->offset = 0;
1040 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1041 sg->offset);
1042 sg_dma_len(sg) = rem;
1043 } else {
1044 sg->offset = rem + size * (i - 1);
1045 sg->offset = sg->offset * (*bpw / 8);
1046 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1047 sg->offset);
1048 sg_dma_len(sg) = size;
1049 }
1050 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1051 }
1052 sg = dma->sg_rx_p;
1053 desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1054 num, DMA_FROM_DEVICE,
1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1056 if (!desc_rx) {
1057 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1058 __func__);
1059 return;
1060 }
1061 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1062 desc_rx->callback = pch_dma_rx_complete;
1063 desc_rx->callback_param = data;
1064 dma->nent = num;
1065 dma->desc_rx = desc_rx;
1066
1067 /* TX */
1068 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1069 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1070 /* offset, length setting */
1071 sg = dma->sg_tx_p;
1072 for (i = 0; i < num; i++, sg++) {
1073 if (i == 0) {
1074 sg->offset = 0;
1075 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1076 sg->offset);
1077 sg_dma_len(sg) = rem;
1078 } else {
1079 sg->offset = rem + size * (i - 1);
1080 sg->offset = sg->offset * (*bpw / 8);
1081 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1082 sg->offset);
1083 sg_dma_len(sg) = size;
1084 }
1085 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1086 }
1087 sg = dma->sg_tx_p;
1088 desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1089 sg, num, DMA_TO_DEVICE,
1090 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1091 if (!desc_tx) {
1092 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1093 __func__);
1094 return;
1095 }
1096 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1097 desc_tx->callback = NULL;
1098 desc_tx->callback_param = data;
1099 dma->nent = num;
1100 dma->desc_tx = desc_tx;
1101
1102 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1103 "0x2 to SSNXCR\n", __func__);
1104
1105 spin_lock_irqsave(&data->lock, flags);
1106 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1107 desc_rx->tx_submit(desc_rx);
1108 desc_tx->tx_submit(desc_tx);
1109 spin_unlock_irqrestore(&data->lock, flags);
1110
1111 /* reset transfer complete flag */
1112 data->transfer_complete = false;
1113 }
1114
1115 static void pch_spi_process_messages(struct work_struct *pwork)
1116 {
1117 struct spi_message *pmsg;
1118 struct pch_spi_data *data;
1119 int bpw;
1120
1121 data = container_of(pwork, struct pch_spi_data, work);
1122 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1123
1124 spin_lock(&data->lock);
1125 /* check if suspend has been initiated;if yes flush queue */
1126 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1127 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1128 "flushing queue\n", __func__);
1129 list_for_each_entry(pmsg, data->queue.next, queue) {
1130 pmsg->status = -EIO;
1131
1132 if (pmsg->complete != 0) {
1133 spin_unlock(&data->lock);
1134 pmsg->complete(pmsg->context);
1135 spin_lock(&data->lock);
1136 }
1137
1138 /* delete from queue */
1139 list_del_init(&pmsg->queue);
1140 }
1141
1142 spin_unlock(&data->lock);
1143 return;
1144 }
1145
1146 data->bcurrent_msg_processing = true;
1147 dev_dbg(&data->master->dev,
1148 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1149
1150 /* Get the message from the queue and delete it from there. */
1151 data->current_msg = list_entry(data->queue.next, struct spi_message,
1152 queue);
1153
1154 list_del_init(&data->current_msg->queue);
1155
1156 data->current_msg->status = 0;
1157
1158 pch_spi_select_chip(data, data->current_msg->spi);
1159
1160 spin_unlock(&data->lock);
1161
1162 if (data->use_dma)
1163 pch_spi_request_dma(data,
1164 data->current_msg->spi->bits_per_word);
1165 do {
1166 /* If we are already processing a message get the next
1167 transfer structure from the message otherwise retrieve
1168 the 1st transfer request from the message. */
1169 spin_lock(&data->lock);
1170 if (data->cur_trans == NULL) {
1171 data->cur_trans =
1172 list_entry(data->current_msg->transfers.next,
1173 struct spi_transfer, transfer_list);
1174 dev_dbg(&data->master->dev, "%s "
1175 ":Getting 1st transfer message\n", __func__);
1176 } else {
1177 data->cur_trans =
1178 list_entry(data->cur_trans->transfer_list.next,
1179 struct spi_transfer, transfer_list);
1180 dev_dbg(&data->master->dev, "%s "
1181 ":Getting next transfer message\n", __func__);
1182 }
1183 spin_unlock(&data->lock);
1184
1185 if (data->use_dma) {
1186 pch_spi_handle_dma(data, &bpw);
1187 pch_spi_start_transfer(data);
1188 pch_spi_copy_rx_data_for_dma(data, bpw);
1189 } else {
1190 pch_spi_set_tx(data, &bpw);
1191 pch_spi_set_ir(data);
1192 pch_spi_copy_rx_data(data, bpw);
1193 kfree(data->pkt_rx_buff);
1194 data->pkt_rx_buff = NULL;
1195 kfree(data->pkt_tx_buff);
1196 data->pkt_tx_buff = NULL;
1197 }
1198 /* increment message count */
1199 data->current_msg->actual_length += data->cur_trans->len;
1200
1201 dev_dbg(&data->master->dev,
1202 "%s:data->current_msg->actual_length=%d\n",
1203 __func__, data->current_msg->actual_length);
1204
1205 /* check for delay */
1206 if (data->cur_trans->delay_usecs) {
1207 dev_dbg(&data->master->dev, "%s:"
1208 "delay in usec=%d\n", __func__,
1209 data->cur_trans->delay_usecs);
1210 udelay(data->cur_trans->delay_usecs);
1211 }
1212
1213 spin_lock(&data->lock);
1214
1215 /* No more transfer in this message. */
1216 if ((data->cur_trans->transfer_list.next) ==
1217 &(data->current_msg->transfers)) {
1218 pch_spi_nomore_transfer(data);
1219 }
1220
1221 spin_unlock(&data->lock);
1222
1223 } while (data->cur_trans != NULL);
1224
1225 if (data->use_dma)
1226 pch_spi_release_dma(data);
1227 }
1228
1229 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1230 struct pch_spi_data *data)
1231 {
1232 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1233
1234 /* free workqueue */
1235 if (data->wk != NULL) {
1236 destroy_workqueue(data->wk);
1237 data->wk = NULL;
1238 dev_dbg(&board_dat->pdev->dev,
1239 "%s destroy_workqueue invoked successfully\n",
1240 __func__);
1241 }
1242 }
1243
1244 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1245 struct pch_spi_data *data)
1246 {
1247 int retval = 0;
1248
1249 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1250
1251 /* create workqueue */
1252 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1253 if (!data->wk) {
1254 dev_err(&board_dat->pdev->dev,
1255 "%s create_singlet hread_workqueue failed\n", __func__);
1256 retval = -EBUSY;
1257 goto err_return;
1258 }
1259
1260 /* reset PCH SPI h/w */
1261 pch_spi_reset(data->master);
1262 dev_dbg(&board_dat->pdev->dev,
1263 "%s pch_spi_reset invoked successfully\n", __func__);
1264
1265 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1266
1267 err_return:
1268 if (retval != 0) {
1269 dev_err(&board_dat->pdev->dev,
1270 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1271 pch_spi_free_resources(board_dat, data);
1272 }
1273
1274 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1275
1276 return retval;
1277 }
1278
1279 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1280 struct pch_spi_data *data)
1281 {
1282 struct pch_spi_dma_ctrl *dma;
1283
1284 dma = &data->dma;
1285 if (dma->tx_buf_dma)
1286 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1287 dma->tx_buf_virt, dma->tx_buf_dma);
1288 if (dma->rx_buf_dma)
1289 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1290 dma->rx_buf_virt, dma->rx_buf_dma);
1291 return;
1292 }
1293
1294 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1295 struct pch_spi_data *data)
1296 {
1297 struct pch_spi_dma_ctrl *dma;
1298
1299 dma = &data->dma;
1300 /* Get Consistent memory for Tx DMA */
1301 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1302 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1303 /* Get Consistent memory for Rx DMA */
1304 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1305 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1306 }
1307
1308 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1309 {
1310 int ret;
1311 struct spi_master *master;
1312 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1313 struct pch_spi_data *data;
1314
1315 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1316
1317 master = spi_alloc_master(&board_dat->pdev->dev,
1318 sizeof(struct pch_spi_data));
1319 if (!master) {
1320 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1321 plat_dev->id);
1322 return -ENOMEM;
1323 }
1324
1325 data = spi_master_get_devdata(master);
1326 data->master = master;
1327
1328 platform_set_drvdata(plat_dev, data);
1329
1330 /* baseaddress + address offset) */
1331 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1332 PCH_ADDRESS_SIZE * plat_dev->id;
1333 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1334 PCH_ADDRESS_SIZE * plat_dev->id;
1335 if (!data->io_remap_addr) {
1336 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1337 ret = -ENOMEM;
1338 goto err_pci_iomap;
1339 }
1340
1341 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1342 plat_dev->id, data->io_remap_addr);
1343
1344 /* initialize members of SPI master */
1345 master->bus_num = -1;
1346 master->num_chipselect = PCH_MAX_CS;
1347 master->setup = pch_spi_setup;
1348 master->transfer = pch_spi_transfer;
1349
1350 data->board_dat = board_dat;
1351 data->plat_dev = plat_dev;
1352 data->n_curnt_chip = 255;
1353 data->status = STATUS_RUNNING;
1354 data->ch = plat_dev->id;
1355 data->use_dma = use_dma;
1356
1357 INIT_LIST_HEAD(&data->queue);
1358 spin_lock_init(&data->lock);
1359 INIT_WORK(&data->work, pch_spi_process_messages);
1360 init_waitqueue_head(&data->wait);
1361
1362 ret = pch_spi_get_resources(board_dat, data);
1363 if (ret) {
1364 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1365 goto err_spi_get_resources;
1366 }
1367
1368 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1369 IRQF_SHARED, KBUILD_MODNAME, data);
1370 if (ret) {
1371 dev_err(&plat_dev->dev,
1372 "%s request_irq failed\n", __func__);
1373 goto err_request_irq;
1374 }
1375 data->irq_reg_sts = true;
1376
1377 pch_spi_set_master_mode(master);
1378
1379 ret = spi_register_master(master);
1380 if (ret != 0) {
1381 dev_err(&plat_dev->dev,
1382 "%s spi_register_master FAILED\n", __func__);
1383 goto err_spi_register_master;
1384 }
1385
1386 if (use_dma) {
1387 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1388 pch_alloc_dma_buf(board_dat, data);
1389 }
1390
1391 return 0;
1392
1393 err_spi_register_master:
1394 free_irq(board_dat->pdev->irq, board_dat);
1395 err_request_irq:
1396 pch_spi_free_resources(board_dat, data);
1397 err_spi_get_resources:
1398 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1399 err_pci_iomap:
1400 spi_master_put(master);
1401
1402 return ret;
1403 }
1404
1405 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1406 {
1407 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1408 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1409 int count;
1410 unsigned long flags;
1411
1412 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1413 __func__, plat_dev->id, board_dat->pdev->irq);
1414
1415 if (use_dma)
1416 pch_free_dma_buf(board_dat, data);
1417
1418 /* check for any pending messages; no action is taken if the queue
1419 * is still full; but at least we tried. Unload anyway */
1420 count = 500;
1421 spin_lock_irqsave(&data->lock, flags);
1422 data->status = STATUS_EXITING;
1423 while ((list_empty(&data->queue) == 0) && --count) {
1424 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1425 __func__);
1426 spin_unlock_irqrestore(&data->lock, flags);
1427 msleep(PCH_SLEEP_TIME);
1428 spin_lock_irqsave(&data->lock, flags);
1429 }
1430 spin_unlock_irqrestore(&data->lock, flags);
1431
1432 pch_spi_free_resources(board_dat, data);
1433 /* disable interrupts & free IRQ */
1434 if (data->irq_reg_sts) {
1435 /* disable interrupts */
1436 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1437 data->irq_reg_sts = false;
1438 free_irq(board_dat->pdev->irq, data);
1439 }
1440
1441 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1442 spi_unregister_master(data->master);
1443 spi_master_put(data->master);
1444 platform_set_drvdata(plat_dev, NULL);
1445
1446 return 0;
1447 }
1448 #ifdef CONFIG_PM
1449 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1450 pm_message_t state)
1451 {
1452 u8 count;
1453 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1454 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1455
1456 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1457
1458 if (!board_dat) {
1459 dev_err(&pd_dev->dev,
1460 "%s pci_get_drvdata returned NULL\n", __func__);
1461 return -EFAULT;
1462 }
1463
1464 /* check if the current message is processed:
1465 Only after thats done the transfer will be suspended */
1466 count = 255;
1467 while ((--count) > 0) {
1468 if (!(data->bcurrent_msg_processing))
1469 break;
1470 msleep(PCH_SLEEP_TIME);
1471 }
1472
1473 /* Free IRQ */
1474 if (data->irq_reg_sts) {
1475 /* disable all interrupts */
1476 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1477 pch_spi_reset(data->master);
1478 free_irq(board_dat->pdev->irq, data);
1479
1480 data->irq_reg_sts = false;
1481 dev_dbg(&pd_dev->dev,
1482 "%s free_irq invoked successfully.\n", __func__);
1483 }
1484
1485 return 0;
1486 }
1487
1488 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1489 {
1490 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1491 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1492 int retval;
1493
1494 if (!board_dat) {
1495 dev_err(&pd_dev->dev,
1496 "%s pci_get_drvdata returned NULL\n", __func__);
1497 return -EFAULT;
1498 }
1499
1500 if (!data->irq_reg_sts) {
1501 /* register IRQ */
1502 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1503 IRQF_SHARED, KBUILD_MODNAME, data);
1504 if (retval < 0) {
1505 dev_err(&pd_dev->dev,
1506 "%s request_irq failed\n", __func__);
1507 return retval;
1508 }
1509
1510 /* reset PCH SPI h/w */
1511 pch_spi_reset(data->master);
1512 pch_spi_set_master_mode(data->master);
1513 data->irq_reg_sts = true;
1514 }
1515 return 0;
1516 }
1517 #else
1518 #define pch_spi_pd_suspend NULL
1519 #define pch_spi_pd_resume NULL
1520 #endif
1521
1522 static struct platform_driver pch_spi_pd_driver = {
1523 .driver = {
1524 .name = "pch-spi",
1525 .owner = THIS_MODULE,
1526 },
1527 .probe = pch_spi_pd_probe,
1528 .remove = __devexit_p(pch_spi_pd_remove),
1529 .suspend = pch_spi_pd_suspend,
1530 .resume = pch_spi_pd_resume
1531 };
1532
1533 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1534 const struct pci_device_id *id)
1535 {
1536 struct pch_spi_board_data *board_dat;
1537 struct platform_device *pd_dev = NULL;
1538 int retval;
1539 int i;
1540 struct pch_pd_dev_save *pd_dev_save;
1541
1542 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1543 if (!pd_dev_save) {
1544 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1545 return -ENOMEM;
1546 }
1547
1548 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1549 if (!board_dat) {
1550 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1551 retval = -ENOMEM;
1552 goto err_no_mem;
1553 }
1554
1555 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1556 if (retval) {
1557 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1558 goto pci_request_regions;
1559 }
1560
1561 board_dat->pdev = pdev;
1562 board_dat->num = id->driver_data;
1563 pd_dev_save->num = id->driver_data;
1564 pd_dev_save->board_dat = board_dat;
1565
1566 retval = pci_enable_device(pdev);
1567 if (retval) {
1568 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1569 goto pci_enable_device;
1570 }
1571
1572 for (i = 0; i < board_dat->num; i++) {
1573 pd_dev = platform_device_alloc("pch-spi", i);
1574 if (!pd_dev) {
1575 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1576 goto err_platform_device;
1577 }
1578 pd_dev_save->pd_save[i] = pd_dev;
1579 pd_dev->dev.parent = &pdev->dev;
1580
1581 retval = platform_device_add_data(pd_dev, board_dat,
1582 sizeof(*board_dat));
1583 if (retval) {
1584 dev_err(&pdev->dev,
1585 "platform_device_add_data failed\n");
1586 platform_device_put(pd_dev);
1587 goto err_platform_device;
1588 }
1589
1590 retval = platform_device_add(pd_dev);
1591 if (retval) {
1592 dev_err(&pdev->dev, "platform_device_add failed\n");
1593 platform_device_put(pd_dev);
1594 goto err_platform_device;
1595 }
1596 }
1597
1598 pci_set_drvdata(pdev, pd_dev_save);
1599
1600 return 0;
1601
1602 err_platform_device:
1603 pci_disable_device(pdev);
1604 pci_enable_device:
1605 pci_release_regions(pdev);
1606 pci_request_regions:
1607 kfree(board_dat);
1608 err_no_mem:
1609 kfree(pd_dev_save);
1610
1611 return retval;
1612 }
1613
1614 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1615 {
1616 int i;
1617 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1618
1619 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1620
1621 for (i = 0; i < pd_dev_save->num; i++)
1622 platform_device_unregister(pd_dev_save->pd_save[i]);
1623
1624 pci_disable_device(pdev);
1625 pci_release_regions(pdev);
1626 kfree(pd_dev_save->board_dat);
1627 kfree(pd_dev_save);
1628 }
1629
1630 #ifdef CONFIG_PM
1631 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1632 {
1633 int retval;
1634 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1635
1636 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1637
1638 pd_dev_save->board_dat->suspend_sts = true;
1639
1640 /* save config space */
1641 retval = pci_save_state(pdev);
1642 if (retval == 0) {
1643 pci_enable_wake(pdev, PCI_D3hot, 0);
1644 pci_disable_device(pdev);
1645 pci_set_power_state(pdev, PCI_D3hot);
1646 } else {
1647 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1648 }
1649
1650 return retval;
1651 }
1652
1653 static int pch_spi_resume(struct pci_dev *pdev)
1654 {
1655 int retval;
1656 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1657 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1658
1659 pci_set_power_state(pdev, PCI_D0);
1660 pci_restore_state(pdev);
1661
1662 retval = pci_enable_device(pdev);
1663 if (retval < 0) {
1664 dev_err(&pdev->dev,
1665 "%s pci_enable_device failed\n", __func__);
1666 } else {
1667 pci_enable_wake(pdev, PCI_D3hot, 0);
1668
1669 /* set suspend status to false */
1670 pd_dev_save->board_dat->suspend_sts = false;
1671 }
1672
1673 return retval;
1674 }
1675 #else
1676 #define pch_spi_suspend NULL
1677 #define pch_spi_resume NULL
1678
1679 #endif
1680
1681 static struct pci_driver pch_spi_pcidev = {
1682 .name = "pch_spi",
1683 .id_table = pch_spi_pcidev_id,
1684 .probe = pch_spi_probe,
1685 .remove = pch_spi_remove,
1686 .suspend = pch_spi_suspend,
1687 .resume = pch_spi_resume,
1688 };
1689
1690 static int __init pch_spi_init(void)
1691 {
1692 int ret;
1693 ret = platform_driver_register(&pch_spi_pd_driver);
1694 if (ret)
1695 return ret;
1696
1697 ret = pci_register_driver(&pch_spi_pcidev);
1698 if (ret)
1699 return ret;
1700
1701 return 0;
1702 }
1703 module_init(pch_spi_init);
1704
1705 static void __exit pch_spi_exit(void)
1706 {
1707 pci_unregister_driver(&pch_spi_pcidev);
1708 platform_driver_unregister(&pch_spi_pd_driver);
1709 }
1710 module_exit(pch_spi_exit);
1711
1712 module_param(use_dma, int, 0644);
1713 MODULE_PARM_DESC(use_dma,
1714 "to use DMA for data transfers pass 1 else 0; default 1");
1715
1716 MODULE_LICENSE("GPL");
1717 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");
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