2 * TI DaVinci EVM board support
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c/pcf857x.h>
18 #include <linux/i2c/at24.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/phy.h>
24 #include <linux/clk.h>
25 #include <linux/videodev2.h>
27 #include <media/tvp514x.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
32 #include <mach/dm644x.h>
33 #include <mach/common.h>
35 #include <mach/serial.h>
37 #include <mach/nand.h>
41 #define DM644X_EVM_PHY_MASK (0x2)
42 #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
44 #define DAVINCI_CFC_ATA_BASE 0x01C66000
46 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
49 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
50 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
52 #define LXT971_PHY_ID (0x001378e2)
53 #define LXT971_PHY_MASK (0xfffffff0)
55 static struct mtd_partition davinci_evm_norflash_partitions
[] = {
56 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
61 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
63 /* bootloader params in the next 1 sectors */
66 .offset
= MTDPART_OFS_APPEND
,
73 .offset
= MTDPART_OFS_APPEND
,
80 .offset
= MTDPART_OFS_APPEND
,
81 .size
= MTDPART_SIZ_FULL
,
86 static struct physmap_flash_data davinci_evm_norflash_data
= {
88 .parts
= davinci_evm_norflash_partitions
,
89 .nr_parts
= ARRAY_SIZE(davinci_evm_norflash_partitions
),
92 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
93 * limits addresses to 16M, so using addresses past 16M will wrap */
94 static struct resource davinci_evm_norflash_resource
= {
95 .start
= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE
,
96 .end
= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE
+ SZ_16M
- 1,
97 .flags
= IORESOURCE_MEM
,
100 static struct platform_device davinci_evm_norflash_device
= {
101 .name
= "physmap-flash",
104 .platform_data
= &davinci_evm_norflash_data
,
107 .resource
= &davinci_evm_norflash_resource
,
110 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
111 * It may used instead of the (default) NOR chip to boot, using TI's
112 * tools to install the secondary boot loader (UBL) and U-Boot.
114 struct mtd_partition davinci_evm_nandflash_partition
[] = {
115 /* Bootloader layout depends on whose u-boot is installed, but we
116 * can hide all the details.
117 * - block 0 for u-boot environment ... in mainline u-boot
118 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
119 * - blocks 6...? for u-boot
120 * - blocks 16..23 for u-boot environment ... in TI's u-boot
123 .name
= "bootloader",
125 .size
= SZ_256K
+ SZ_128K
,
126 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
131 .offset
= MTDPART_OFS_APPEND
,
135 /* File system (older GIT kernels started this on the 5MB mark) */
137 .name
= "filesystem",
138 .offset
= MTDPART_OFS_APPEND
,
139 .size
= MTDPART_SIZ_FULL
,
142 /* A few blocks at end hold a flash BBT ... created by TI's CCS
143 * using flashwriter_nand.out, but ignored by TI's versions of
144 * Linux and u-boot. We boot faster by using them.
148 static struct davinci_nand_pdata davinci_evm_nandflash_data
= {
149 .parts
= davinci_evm_nandflash_partition
,
150 .nr_parts
= ARRAY_SIZE(davinci_evm_nandflash_partition
),
151 .ecc_mode
= NAND_ECC_HW
,
152 .options
= NAND_USE_FLASH_BBT
,
155 static struct resource davinci_evm_nandflash_resource
[] = {
157 .start
= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE
,
158 .end
= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE
+ SZ_16M
- 1,
159 .flags
= IORESOURCE_MEM
,
161 .start
= DAVINCI_ASYNC_EMIF_CONTROL_BASE
,
162 .end
= DAVINCI_ASYNC_EMIF_CONTROL_BASE
+ SZ_4K
- 1,
163 .flags
= IORESOURCE_MEM
,
167 static struct platform_device davinci_evm_nandflash_device
= {
168 .name
= "davinci_nand",
171 .platform_data
= &davinci_evm_nandflash_data
,
173 .num_resources
= ARRAY_SIZE(davinci_evm_nandflash_resource
),
174 .resource
= davinci_evm_nandflash_resource
,
177 static u64 davinci_fb_dma_mask
= DMA_BIT_MASK(32);
179 static struct platform_device davinci_fb_device
= {
183 .dma_mask
= &davinci_fb_dma_mask
,
184 .coherent_dma_mask
= DMA_BIT_MASK(32),
189 static struct tvp514x_platform_data tvp5146_pdata
= {
195 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
196 /* Inputs available at the TVP5146 */
197 static struct v4l2_input tvp5146_inputs
[] = {
201 .type
= V4L2_INPUT_TYPE_CAMERA
,
202 .std
= TVP514X_STD_ALL
,
207 .type
= V4L2_INPUT_TYPE_CAMERA
,
208 .std
= TVP514X_STD_ALL
,
213 * this is the route info for connecting each input to decoder
214 * ouput that goes to vpfe. There is a one to one correspondence
215 * with tvp5146_inputs
217 static struct vpfe_route tvp5146_routes
[] = {
219 .input
= INPUT_CVBS_VI2B
,
220 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
223 .input
= INPUT_SVIDEO_VI2C_VI1C
,
224 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
228 static struct vpfe_subdev_info vpfe_sub_devs
[] = {
232 .num_inputs
= ARRAY_SIZE(tvp5146_inputs
),
233 .inputs
= tvp5146_inputs
,
234 .routes
= tvp5146_routes
,
237 .if_type
= VPFE_BT656
,
238 .hdpol
= VPFE_PINPOL_POSITIVE
,
239 .vdpol
= VPFE_PINPOL_POSITIVE
,
242 I2C_BOARD_INFO("tvp5146", 0x5d),
243 .platform_data
= &tvp5146_pdata
,
248 static struct vpfe_config vpfe_cfg
= {
249 .num_subdevs
= ARRAY_SIZE(vpfe_sub_devs
),
251 .sub_devs
= vpfe_sub_devs
,
252 .card_name
= "DM6446 EVM",
253 .ccdc
= "DM6446 CCDC",
256 static struct platform_device rtc_dev
= {
257 .name
= "rtc_davinci_evm",
261 static struct resource ide_resources
[] = {
263 .start
= DAVINCI_CFC_ATA_BASE
,
264 .end
= DAVINCI_CFC_ATA_BASE
+ 0x7ff,
265 .flags
= IORESOURCE_MEM
,
270 .flags
= IORESOURCE_IRQ
,
274 static u64 ide_dma_mask
= DMA_BIT_MASK(32);
276 static struct platform_device ide_dev
= {
277 .name
= "palm_bk3710",
279 .resource
= ide_resources
,
280 .num_resources
= ARRAY_SIZE(ide_resources
),
282 .dma_mask
= &ide_dma_mask
,
283 .coherent_dma_mask
= DMA_BIT_MASK(32),
287 static struct snd_platform_data dm644x_evm_snd_data
;
289 /*----------------------------------------------------------------------*/
295 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
300 static struct gpio_led evm_leds
[] = {
301 { .name
= "DS8", .active_low
= 1,
302 .default_trigger
= "heartbeat", },
303 { .name
= "DS7", .active_low
= 1, },
304 { .name
= "DS6", .active_low
= 1, },
305 { .name
= "DS5", .active_low
= 1, },
306 { .name
= "DS4", .active_low
= 1, },
307 { .name
= "DS3", .active_low
= 1, },
308 { .name
= "DS2", .active_low
= 1,
309 .default_trigger
= "mmc0", },
310 { .name
= "DS1", .active_low
= 1,
311 .default_trigger
= "ide-disk", },
314 static const struct gpio_led_platform_data evm_led_data
= {
315 .num_leds
= ARRAY_SIZE(evm_leds
),
319 static struct platform_device
*evm_led_dev
;
322 evm_led_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
324 struct gpio_led
*leds
= evm_leds
;
332 /* what an extremely annoying way to be forced to handle
333 * device unregistration ...
335 evm_led_dev
= platform_device_alloc("leds-gpio", 0);
336 platform_device_add_data(evm_led_dev
,
337 &evm_led_data
, sizeof evm_led_data
);
339 evm_led_dev
->dev
.parent
= &client
->dev
;
340 status
= platform_device_add(evm_led_dev
);
342 platform_device_put(evm_led_dev
);
349 evm_led_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
352 platform_device_unregister(evm_led_dev
);
358 static struct pcf857x_platform_data pcf_data_u2
= {
359 .gpio_base
= PCF_Uxx_BASE(0),
360 .setup
= evm_led_setup
,
361 .teardown
= evm_led_teardown
,
365 /* U18 - A/V clock generator and user switch */
370 sw_show(struct device
*d
, struct device_attribute
*a
, char *buf
)
372 char *s
= gpio_get_value_cansleep(sw_gpio
) ? "on\n" : "off\n";
378 static DEVICE_ATTR(user_sw
, S_IRUGO
, sw_show
, NULL
);
381 evm_u18_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
385 /* export dip switch option */
387 status
= gpio_request(sw_gpio
, "user_sw");
389 status
= gpio_direction_input(sw_gpio
);
391 status
= device_create_file(&client
->dev
, &dev_attr_user_sw
);
397 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
398 gpio_request(gpio
+ 3, "pll_fs2");
399 gpio_direction_output(gpio
+ 3, 0);
401 gpio_request(gpio
+ 2, "pll_fs1");
402 gpio_direction_output(gpio
+ 2, 0);
404 gpio_request(gpio
+ 1, "pll_sr");
405 gpio_direction_output(gpio
+ 1, 0);
411 evm_u18_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
418 device_remove_file(&client
->dev
, &dev_attr_user_sw
);
424 static struct pcf857x_platform_data pcf_data_u18
= {
425 .gpio_base
= PCF_Uxx_BASE(1),
426 .n_latch
= (1 << 3) | (1 << 2) | (1 << 1),
427 .setup
= evm_u18_setup
,
428 .teardown
= evm_u18_teardown
,
432 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
435 evm_u35_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
437 /* p0 = nDRV_VBUS (initial: don't supply it) */
438 gpio_request(gpio
+ 0, "nDRV_VBUS");
439 gpio_direction_output(gpio
+ 0, 1);
442 gpio_request(gpio
+ 1, "VDDIMX_EN");
443 gpio_direction_output(gpio
+ 1, 1);
446 gpio_request(gpio
+ 2, "VLYNQ_EN");
447 gpio_direction_output(gpio
+ 2, 1);
449 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
450 gpio_request(gpio
+ 3, "nCF_RESET");
451 gpio_direction_output(gpio
+ 3, 0);
455 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
456 gpio_request(gpio
+ 5, "WLAN_RESET");
457 gpio_direction_output(gpio
+ 5, 1);
459 /* p6 = nATA_SEL (initial: select) */
460 gpio_request(gpio
+ 6, "nATA_SEL");
461 gpio_direction_output(gpio
+ 6, 0);
463 /* p7 = nCF_SEL (initial: deselect) */
464 gpio_request(gpio
+ 7, "nCF_SEL");
465 gpio_direction_output(gpio
+ 7, 1);
467 /* irlml6401 switches over 1A, in under 8 msec;
468 * now it can be managed by nDRV_VBUS ...
470 davinci_setup_usb(1000, 8);
476 evm_u35_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
488 static struct pcf857x_platform_data pcf_data_u35
= {
489 .gpio_base
= PCF_Uxx_BASE(2),
490 .setup
= evm_u35_setup
,
491 .teardown
= evm_u35_teardown
,
494 /*----------------------------------------------------------------------*/
496 /* Most of this EEPROM is unused, but U-Boot uses some data:
497 * - 0x7f00, 6 bytes Ethernet Address
498 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
499 * - ... newer boards may have more
502 static struct at24_platform_data eeprom_info
= {
503 .byte_len
= (256*1024) / 8,
505 .flags
= AT24_FLAG_ADDR16
,
506 .setup
= davinci_get_mac_addr
,
507 .context
= (void *)0x7f00,
511 * MSP430 supports RTC, card detection, input from IR remote, and
512 * a bit more. It triggers interrupts on GPIO(7) from pressing
513 * buttons on the IR remote, and for card detect switches.
515 static struct i2c_client
*dm6446evm_msp
;
517 static int dm6446evm_msp_probe(struct i2c_client
*client
,
518 const struct i2c_device_id
*id
)
520 dm6446evm_msp
= client
;
524 static int dm6446evm_msp_remove(struct i2c_client
*client
)
526 dm6446evm_msp
= NULL
;
530 static const struct i2c_device_id dm6446evm_msp_ids
[] = {
531 { "dm6446evm_msp", 0, },
532 { /* end of list */ },
535 static struct i2c_driver dm6446evm_msp_driver
= {
536 .driver
.name
= "dm6446evm_msp",
537 .id_table
= dm6446evm_msp_ids
,
538 .probe
= dm6446evm_msp_probe
,
539 .remove
= dm6446evm_msp_remove
,
542 static int dm6444evm_msp430_get_pins(void)
544 static const char txbuf
[2] = { 2, 4, };
546 struct i2c_msg msg
[2] = {
548 .addr
= dm6446evm_msp
->addr
,
551 .buf
= (void __force
*)txbuf
,
554 .addr
= dm6446evm_msp
->addr
,
565 /* Command 4 == get input state, returns port 2 and port3 data
566 * S Addr W [A] len=2 [A] cmd=4 [A]
567 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
569 status
= i2c_transfer(dm6446evm_msp
->adapter
, msg
, 2);
573 dev_dbg(&dm6446evm_msp
->dev
,
574 "PINS: %02x %02x %02x %02x\n",
575 buf
[0], buf
[1], buf
[2], buf
[3]);
577 return (buf
[3] << 8) | buf
[2];
580 static int dm6444evm_mmc_get_cd(int module
)
582 int status
= dm6444evm_msp430_get_pins();
584 return (status
< 0) ? status
: !(status
& BIT(1));
587 static int dm6444evm_mmc_get_ro(int module
)
589 int status
= dm6444evm_msp430_get_pins();
591 return (status
< 0) ? status
: status
& BIT(6 + 8);
594 static struct davinci_mmc_config dm6446evm_mmc_config
= {
595 .get_cd
= dm6444evm_mmc_get_cd
,
596 .get_ro
= dm6444evm_mmc_get_ro
,
598 .version
= MMC_CTLR_VERSION_1
601 static struct i2c_board_info __initdata i2c_info
[] = {
603 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
606 I2C_BOARD_INFO("pcf8574", 0x38),
607 .platform_data
= &pcf_data_u2
,
610 I2C_BOARD_INFO("pcf8574", 0x39),
611 .platform_data
= &pcf_data_u18
,
614 I2C_BOARD_INFO("pcf8574", 0x3a),
615 .platform_data
= &pcf_data_u35
,
618 I2C_BOARD_INFO("24c256", 0x50),
619 .platform_data
= &eeprom_info
,
622 I2C_BOARD_INFO("tlv320aic33", 0x1b),
626 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
627 * which requires 100 usec of idle bus after i2c writes sent to it.
629 static struct davinci_i2c_platform_data i2c_pdata
= {
630 .bus_freq
= 20 /* kHz */,
631 .bus_delay
= 100 /* usec */,
636 static void __init
evm_init_i2c(void)
638 davinci_init_i2c(&i2c_pdata
);
639 i2c_add_driver(&dm6446evm_msp_driver
);
640 i2c_register_board_info(1, i2c_info
, ARRAY_SIZE(i2c_info
));
643 static struct platform_device
*davinci_evm_devices
[] __initdata
= {
648 static struct davinci_uart_config uart_config __initdata
= {
649 .enabled_uarts
= (1 << 0),
653 davinci_evm_map_io(void)
655 /* setup input configuration for VPFE input devices */
656 dm644x_set_vpfe_config(&vpfe_cfg
);
660 static int davinci_phy_fixup(struct phy_device
*phydev
)
662 unsigned int control
;
663 /* CRITICAL: Fix for increasing PHY signal drive strength for
664 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
665 * signal strength was low causing TX to fail randomly. The
666 * fix is to Set bit 11 (Increased MII drive strength) of PHY
667 * register 26 (Digital Config register) on this phy. */
668 control
= phy_read(phydev
, 26);
669 phy_write(phydev
, 26, (control
| 0x800));
673 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
674 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
680 #if defined(CONFIG_MTD_PHYSMAP) || \
681 defined(CONFIG_MTD_PHYSMAP_MODULE)
687 #if defined(CONFIG_MTD_NAND_DAVINCI) || \
688 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
694 static __init
void davinci_evm_init(void)
696 struct clk
*aemif_clk
;
697 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
699 aemif_clk
= clk_get(NULL
, "aemif");
700 clk_enable(aemif_clk
);
703 if (HAS_NAND
|| HAS_NOR
)
704 pr_warning("WARNING: both IDE and Flash are "
705 "enabled, but they share AEMIF pins.\n"
706 "\tDisable IDE for NAND/NOR support.\n");
707 davinci_cfg_reg(DM644X_HPIEN_DISABLE
);
708 davinci_cfg_reg(DM644X_ATAEN
);
709 davinci_cfg_reg(DM644X_HDIREN
);
710 platform_device_register(&ide_dev
);
711 } else if (HAS_NAND
|| HAS_NOR
) {
712 davinci_cfg_reg(DM644X_HPIEN_DISABLE
);
713 davinci_cfg_reg(DM644X_ATAEN_DISABLE
);
715 /* only one device will be jumpered and detected */
717 platform_device_register(&davinci_evm_nandflash_device
);
718 evm_leds
[7].default_trigger
= "nand-disk";
720 pr_warning("WARNING: both NAND and NOR flash "
721 "are enabled; disable one of them.\n");
723 platform_device_register(&davinci_evm_norflash_device
);
726 platform_add_devices(davinci_evm_devices
,
727 ARRAY_SIZE(davinci_evm_devices
));
730 davinci_setup_mmc(0, &dm6446evm_mmc_config
);
732 davinci_serial_init(&uart_config
);
733 dm644x_init_asp(&dm644x_evm_snd_data
);
735 soc_info
->emac_pdata
->phy_mask
= DM644X_EVM_PHY_MASK
;
736 soc_info
->emac_pdata
->mdio_max_freq
= DM644X_EVM_MDIO_FREQUENCY
;
738 /* Register the fixup for PHY on DaVinci */
739 phy_register_fixup_for_uid(LXT971_PHY_ID
, LXT971_PHY_MASK
,
744 static __init
void davinci_evm_irq_init(void)
749 MACHINE_START(DAVINCI_EVM
, "DaVinci DM644x EVM")
750 /* Maintainer: MontaVista Software <source@mvista.com> */
752 .io_pg_offst
= (__IO_ADDRESS(IO_PHYS
) >> 18) & 0xfffc,
753 .boot_params
= (DAVINCI_DDR_BASE
+ 0x100),
754 .map_io
= davinci_evm_map_io
,
755 .init_irq
= davinci_evm_irq_init
,
756 .timer
= &davinci_timer
,
757 .init_machine
= davinci_evm_init
,