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MIPS: SB1250: Include correct header and fix a warning
[linux-2.6/linux-mips.git] / arch / arm / mach-omap1 / clock_data.c
blobaa8558adbf1c0416d81dd89c6c43dd5eab0424ca
1 /*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
15 #include <linux/io.h>
16
17 #include <asm/mach-types.h> /* for machine_is_* */
18
19 #include <plat/clock.h>
20 #include <plat/cpu.h>
21 #include <plat/clkdev_omap.h>
22 #include <plat/usb.h> /* for OTG_BASE */
23
24 #include "clock.h"
25
26 /*------------------------------------------------------------------------
27 * Omap1 clocks
28 *-------------------------------------------------------------------------*/
29
30 static struct clk ck_ref = {
31 .name = "ck_ref",
32 .ops = &clkops_null,
33 .rate = 12000000,
34 };
35
36 static struct clk ck_dpll1 = {
37 .name = "ck_dpll1",
38 .ops = &clkops_null,
39 .parent = &ck_ref,
40 };
41
42 /*
43 * FIXME: This clock seems to be necessary but no-one has asked for its
44 * activation. [ FIX: SoSSI, SSR ]
45 */
46 static struct arm_idlect1_clk ck_dpll1out = {
47 .clk = {
48 .name = "ck_dpll1out",
49 .ops = &clkops_generic,
50 .parent = &ck_dpll1,
51 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
52 ENABLE_ON_INIT,
53 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
54 .enable_bit = EN_CKOUT_ARM,
55 .recalc = &followparent_recalc,
56 },
57 .idlect_shift = 12,
58 };
59
60 static struct clk sossi_ck = {
61 .name = "ck_sossi",
62 .ops = &clkops_generic,
63 .parent = &ck_dpll1out.clk,
64 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
65 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
66 .enable_bit = 16,
67 .recalc = &omap1_sossi_recalc,
68 .set_rate = &omap1_set_sossi_rate,
69 };
70
71 static struct clk arm_ck = {
72 .name = "arm_ck",
73 .ops = &clkops_null,
74 .parent = &ck_dpll1,
75 .rate_offset = CKCTL_ARMDIV_OFFSET,
76 .recalc = &omap1_ckctl_recalc,
77 .round_rate = omap1_clk_round_rate_ckctl_arm,
78 .set_rate = omap1_clk_set_rate_ckctl_arm,
79 };
80
81 static struct arm_idlect1_clk armper_ck = {
82 .clk = {
83 .name = "armper_ck",
84 .ops = &clkops_generic,
85 .parent = &ck_dpll1,
86 .flags = CLOCK_IDLE_CONTROL,
87 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
88 .enable_bit = EN_PERCK,
89 .rate_offset = CKCTL_PERDIV_OFFSET,
90 .recalc = &omap1_ckctl_recalc,
91 .round_rate = omap1_clk_round_rate_ckctl_arm,
92 .set_rate = omap1_clk_set_rate_ckctl_arm,
93 },
94 .idlect_shift = 2,
95 };
96
97 /*
98 * FIXME: This clock seems to be necessary but no-one has asked for its
99 * activation. [ GPIO code for 1510 ]
100 */
101 static struct clk arm_gpio_ck = {
102 .name = "arm_gpio_ck",
103 .ops = &clkops_generic,
104 .parent = &ck_dpll1,
105 .flags = ENABLE_ON_INIT,
106 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
107 .enable_bit = EN_GPIOCK,
108 .recalc = &followparent_recalc,
109 };
110
111 static struct arm_idlect1_clk armxor_ck = {
112 .clk = {
113 .name = "armxor_ck",
114 .ops = &clkops_generic,
115 .parent = &ck_ref,
116 .flags = CLOCK_IDLE_CONTROL,
117 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
118 .enable_bit = EN_XORPCK,
119 .recalc = &followparent_recalc,
120 },
121 .idlect_shift = 1,
122 };
123
124 static struct arm_idlect1_clk armtim_ck = {
125 .clk = {
126 .name = "armtim_ck",
127 .ops = &clkops_generic,
128 .parent = &ck_ref,
129 .flags = CLOCK_IDLE_CONTROL,
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
131 .enable_bit = EN_TIMCK,
132 .recalc = &followparent_recalc,
133 },
134 .idlect_shift = 9,
135 };
136
137 static struct arm_idlect1_clk armwdt_ck = {
138 .clk = {
139 .name = "armwdt_ck",
140 .ops = &clkops_generic,
141 .parent = &ck_ref,
142 .flags = CLOCK_IDLE_CONTROL,
143 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
144 .enable_bit = EN_WDTCK,
145 .fixed_div = 14,
146 .recalc = &omap_fixed_divisor_recalc,
147 },
148 .idlect_shift = 0,
149 };
150
151 static struct clk arminth_ck16xx = {
152 .name = "arminth_ck",
153 .ops = &clkops_null,
154 .parent = &arm_ck,
155 .recalc = &followparent_recalc,
156 /* Note: On 16xx the frequency can be divided by 2 by programming
157 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
158 *
159 * 1510 version is in TC clocks.
160 */
161 };
162
163 static struct clk dsp_ck = {
164 .name = "dsp_ck",
165 .ops = &clkops_generic,
166 .parent = &ck_dpll1,
167 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
168 .enable_bit = EN_DSPCK,
169 .rate_offset = CKCTL_DSPDIV_OFFSET,
170 .recalc = &omap1_ckctl_recalc,
171 .round_rate = omap1_clk_round_rate_ckctl_arm,
172 .set_rate = omap1_clk_set_rate_ckctl_arm,
173 };
174
175 static struct clk dspmmu_ck = {
176 .name = "dspmmu_ck",
177 .ops = &clkops_null,
178 .parent = &ck_dpll1,
179 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
180 .recalc = &omap1_ckctl_recalc,
181 .round_rate = omap1_clk_round_rate_ckctl_arm,
182 .set_rate = omap1_clk_set_rate_ckctl_arm,
183 };
184
185 static struct clk dspper_ck = {
186 .name = "dspper_ck",
187 .ops = &clkops_dspck,
188 .parent = &ck_dpll1,
189 .enable_reg = DSP_IDLECT2,
190 .enable_bit = EN_PERCK,
191 .rate_offset = CKCTL_PERDIV_OFFSET,
192 .recalc = &omap1_ckctl_recalc_dsp_domain,
193 .round_rate = omap1_clk_round_rate_ckctl_arm,
194 .set_rate = &omap1_clk_set_rate_dsp_domain,
195 };
196
197 static struct clk dspxor_ck = {
198 .name = "dspxor_ck",
199 .ops = &clkops_dspck,
200 .parent = &ck_ref,
201 .enable_reg = DSP_IDLECT2,
202 .enable_bit = EN_XORPCK,
203 .recalc = &followparent_recalc,
204 };
205
206 static struct clk dsptim_ck = {
207 .name = "dsptim_ck",
208 .ops = &clkops_dspck,
209 .parent = &ck_ref,
210 .enable_reg = DSP_IDLECT2,
211 .enable_bit = EN_DSPTIMCK,
212 .recalc = &followparent_recalc,
213 };
214
215 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
216 static struct arm_idlect1_clk tc_ck = {
217 .clk = {
218 .name = "tc_ck",
219 .ops = &clkops_null,
220 .parent = &ck_dpll1,
221 .flags = CLOCK_IDLE_CONTROL,
222 .rate_offset = CKCTL_TCDIV_OFFSET,
223 .recalc = &omap1_ckctl_recalc,
224 .round_rate = omap1_clk_round_rate_ckctl_arm,
225 .set_rate = omap1_clk_set_rate_ckctl_arm,
226 },
227 .idlect_shift = 6,
228 };
229
230 static struct clk arminth_ck1510 = {
231 .name = "arminth_ck",
232 .ops = &clkops_null,
233 .parent = &tc_ck.clk,
234 .recalc = &followparent_recalc,
235 /* Note: On 1510 the frequency follows TC_CK
236 *
237 * 16xx version is in MPU clocks.
238 */
239 };
240
241 static struct clk tipb_ck = {
242 /* No-idle controlled by "tc_ck" */
243 .name = "tipb_ck",
244 .ops = &clkops_null,
245 .parent = &tc_ck.clk,
246 .recalc = &followparent_recalc,
247 };
248
249 static struct clk l3_ocpi_ck = {
250 /* No-idle controlled by "tc_ck" */
251 .name = "l3_ocpi_ck",
252 .ops = &clkops_generic,
253 .parent = &tc_ck.clk,
254 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
255 .enable_bit = EN_OCPI_CK,
256 .recalc = &followparent_recalc,
257 };
258
259 static struct clk tc1_ck = {
260 .name = "tc1_ck",
261 .ops = &clkops_generic,
262 .parent = &tc_ck.clk,
263 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
264 .enable_bit = EN_TC1_CK,
265 .recalc = &followparent_recalc,
266 };
267
268 /*
269 * FIXME: This clock seems to be necessary but no-one has asked for its
270 * activation. [ pm.c (SRAM), CCP, Camera ]
271 */
272 static struct clk tc2_ck = {
273 .name = "tc2_ck",
274 .ops = &clkops_generic,
275 .parent = &tc_ck.clk,
276 .flags = ENABLE_ON_INIT,
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
278 .enable_bit = EN_TC2_CK,
279 .recalc = &followparent_recalc,
280 };
281
282 static struct clk dma_ck = {
283 /* No-idle controlled by "tc_ck" */
284 .name = "dma_ck",
285 .ops = &clkops_null,
286 .parent = &tc_ck.clk,
287 .recalc = &followparent_recalc,
288 };
289
290 static struct clk dma_lcdfree_ck = {
291 .name = "dma_lcdfree_ck",
292 .ops = &clkops_null,
293 .parent = &tc_ck.clk,
294 .recalc = &followparent_recalc,
295 };
296
297 static struct arm_idlect1_clk api_ck = {
298 .clk = {
299 .name = "api_ck",
300 .ops = &clkops_generic,
301 .parent = &tc_ck.clk,
302 .flags = CLOCK_IDLE_CONTROL,
303 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
304 .enable_bit = EN_APICK,
305 .recalc = &followparent_recalc,
306 },
307 .idlect_shift = 8,
308 };
309
310 static struct arm_idlect1_clk lb_ck = {
311 .clk = {
312 .name = "lb_ck",
313 .ops = &clkops_generic,
314 .parent = &tc_ck.clk,
315 .flags = CLOCK_IDLE_CONTROL,
316 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
317 .enable_bit = EN_LBCK,
318 .recalc = &followparent_recalc,
319 },
320 .idlect_shift = 4,
321 };
322
323 static struct clk rhea1_ck = {
324 .name = "rhea1_ck",
325 .ops = &clkops_null,
326 .parent = &tc_ck.clk,
327 .recalc = &followparent_recalc,
328 };
329
330 static struct clk rhea2_ck = {
331 .name = "rhea2_ck",
332 .ops = &clkops_null,
333 .parent = &tc_ck.clk,
334 .recalc = &followparent_recalc,
335 };
336
337 static struct clk lcd_ck_16xx = {
338 .name = "lcd_ck",
339 .ops = &clkops_generic,
340 .parent = &ck_dpll1,
341 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
342 .enable_bit = EN_LCDCK,
343 .rate_offset = CKCTL_LCDDIV_OFFSET,
344 .recalc = &omap1_ckctl_recalc,
345 .round_rate = omap1_clk_round_rate_ckctl_arm,
346 .set_rate = omap1_clk_set_rate_ckctl_arm,
347 };
348
349 static struct arm_idlect1_clk lcd_ck_1510 = {
350 .clk = {
351 .name = "lcd_ck",
352 .ops = &clkops_generic,
353 .parent = &ck_dpll1,
354 .flags = CLOCK_IDLE_CONTROL,
355 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
356 .enable_bit = EN_LCDCK,
357 .rate_offset = CKCTL_LCDDIV_OFFSET,
358 .recalc = &omap1_ckctl_recalc,
359 .round_rate = omap1_clk_round_rate_ckctl_arm,
360 .set_rate = omap1_clk_set_rate_ckctl_arm,
361 },
362 .idlect_shift = 3,
363 };
364
365 static struct clk uart1_1510 = {
366 .name = "uart1_ck",
367 .ops = &clkops_null,
368 /* Direct from ULPD, no real parent */
369 .parent = &armper_ck.clk,
370 .rate = 12000000,
371 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
372 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
373 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
374 .set_rate = &omap1_set_uart_rate,
375 .recalc = &omap1_uart_recalc,
376 };
377
378 static struct uart_clk uart1_16xx = {
379 .clk = {
380 .name = "uart1_ck",
381 .ops = &clkops_uart,
382 /* Direct from ULPD, no real parent */
383 .parent = &armper_ck.clk,
384 .rate = 48000000,
385 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
386 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
387 .enable_bit = 29,
388 },
389 .sysc_addr = 0xfffb0054,
390 };
391
392 static struct clk uart2_ck = {
393 .name = "uart2_ck",
394 .ops = &clkops_null,
395 /* Direct from ULPD, no real parent */
396 .parent = &armper_ck.clk,
397 .rate = 12000000,
398 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
399 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
400 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
401 .set_rate = &omap1_set_uart_rate,
402 .recalc = &omap1_uart_recalc,
403 };
404
405 static struct clk uart3_1510 = {
406 .name = "uart3_ck",
407 .ops = &clkops_null,
408 /* Direct from ULPD, no real parent */
409 .parent = &armper_ck.clk,
410 .rate = 12000000,
411 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
412 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
413 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
414 .set_rate = &omap1_set_uart_rate,
415 .recalc = &omap1_uart_recalc,
416 };
417
418 static struct uart_clk uart3_16xx = {
419 .clk = {
420 .name = "uart3_ck",
421 .ops = &clkops_uart,
422 /* Direct from ULPD, no real parent */
423 .parent = &armper_ck.clk,
424 .rate = 48000000,
425 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
426 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
427 .enable_bit = 31,
428 },
429 .sysc_addr = 0xfffb9854,
430 };
431
432 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
433 .name = "usb_clko",
434 .ops = &clkops_generic,
435 /* Direct from ULPD, no parent */
436 .rate = 6000000,
437 .flags = ENABLE_REG_32BIT,
438 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
439 .enable_bit = USB_MCLK_EN_BIT,
440 };
441
442 static struct clk usb_hhc_ck1510 = {
443 .name = "usb_hhc_ck",
444 .ops = &clkops_generic,
445 /* Direct from ULPD, no parent */
446 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
447 .flags = ENABLE_REG_32BIT,
448 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
449 .enable_bit = USB_HOST_HHC_UHOST_EN,
450 };
451
452 static struct clk usb_hhc_ck16xx = {
453 .name = "usb_hhc_ck",
454 .ops = &clkops_generic,
455 /* Direct from ULPD, no parent */
456 .rate = 48000000,
457 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
458 .flags = ENABLE_REG_32BIT,
459 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
460 .enable_bit = 8 /* UHOST_EN */,
461 };
462
463 static struct clk usb_dc_ck = {
464 .name = "usb_dc_ck",
465 .ops = &clkops_generic,
466 /* Direct from ULPD, no parent */
467 .rate = 48000000,
468 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
469 .enable_bit = 4,
470 };
471
472 static struct clk usb_dc_ck7xx = {
473 .name = "usb_dc_ck",
474 .ops = &clkops_generic,
475 /* Direct from ULPD, no parent */
476 .rate = 48000000,
477 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
478 .enable_bit = 8,
479 };
480
481 static struct clk mclk_1510 = {
482 .name = "mclk",
483 .ops = &clkops_generic,
484 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
485 .rate = 12000000,
486 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
487 .enable_bit = 6,
488 };
489
490 static struct clk mclk_16xx = {
491 .name = "mclk",
492 .ops = &clkops_generic,
493 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
494 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
495 .enable_bit = COM_ULPD_PLL_CLK_REQ,
496 .set_rate = &omap1_set_ext_clk_rate,
497 .round_rate = &omap1_round_ext_clk_rate,
498 .init = &omap1_init_ext_clk,
499 };
500
501 static struct clk bclk_1510 = {
502 .name = "bclk",
503 .ops = &clkops_generic,
504 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
505 .rate = 12000000,
506 };
507
508 static struct clk bclk_16xx = {
509 .name = "bclk",
510 .ops = &clkops_generic,
511 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
512 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
513 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
514 .set_rate = &omap1_set_ext_clk_rate,
515 .round_rate = &omap1_round_ext_clk_rate,
516 .init = &omap1_init_ext_clk,
517 };
518
519 static struct clk mmc1_ck = {
520 .name = "mmc1_ck",
521 .ops = &clkops_generic,
522 /* Functional clock is direct from ULPD, interface clock is ARMPER */
523 .parent = &armper_ck.clk,
524 .rate = 48000000,
525 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
526 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
527 .enable_bit = 23,
528 };
529
530 static struct clk mmc2_ck = {
531 .name = "mmc2_ck",
532 .ops = &clkops_generic,
533 /* Functional clock is direct from ULPD, interface clock is ARMPER */
534 .parent = &armper_ck.clk,
535 .rate = 48000000,
536 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
537 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
538 .enable_bit = 20,
539 };
540
541 static struct clk mmc3_ck = {
542 .name = "mmc3_ck",
543 .ops = &clkops_generic,
544 /* Functional clock is direct from ULPD, interface clock is ARMPER */
545 .parent = &armper_ck.clk,
546 .rate = 48000000,
547 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
548 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
549 .enable_bit = 12,
550 };
551
552 static struct clk virtual_ck_mpu = {
553 .name = "mpu",
554 .ops = &clkops_null,
555 .parent = &arm_ck, /* Is smarter alias for */
556 .recalc = &followparent_recalc,
557 .set_rate = &omap1_select_table_rate,
558 .round_rate = &omap1_round_to_table_rate,
559 };
560
561 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
562 remains active during MPU idle whenever this is enabled */
563 static struct clk i2c_fck = {
564 .name = "i2c_fck",
565 .ops = &clkops_null,
566 .flags = CLOCK_NO_IDLE_PARENT,
567 .parent = &armxor_ck.clk,
568 .recalc = &followparent_recalc,
569 };
570
571 static struct clk i2c_ick = {
572 .name = "i2c_ick",
573 .ops = &clkops_null,
574 .flags = CLOCK_NO_IDLE_PARENT,
575 .parent = &armper_ck.clk,
576 .recalc = &followparent_recalc,
577 };
578
579 /*
580 * clkdev integration
581 */
582
583 static struct omap_clk omap_clks[] = {
584 /* non-ULPD clocks */
585 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
586 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
587 /* CK_GEN1 clocks */
588 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
589 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
590 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
591 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
592 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
593 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
594 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
595 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
596 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
597 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
598 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
599 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
600 /* CK_GEN2 clocks */
601 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
602 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
603 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
604 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
605 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
606 /* CK_GEN3 clocks */
607 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
608 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
609 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
610 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
611 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
612 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
613 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
614 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
615 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
616 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
617 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
618 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
619 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
620 /* ULPD clocks */
621 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
622 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
623 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
624 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
625 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
626 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
627 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
628 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
629 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
630 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
631 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
632 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
633 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
634 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
635 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
636 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
637 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
638 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
639 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
640 /* Virtual clocks */
641 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
642 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
643 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
644 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
645 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
646 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
647 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
648 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
649 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
650 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
651 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
652 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
653 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
654 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
655 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
656 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
657 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
658 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
659 };
660
661 /*
662 * init
663 */
664
665 static struct clk_functions omap1_clk_functions = {
666 .clk_enable = omap1_clk_enable,
667 .clk_disable = omap1_clk_disable,
668 .clk_round_rate = omap1_clk_round_rate,
669 .clk_set_rate = omap1_clk_set_rate,
670 .clk_disable_unused = omap1_clk_disable_unused,
671 };
672
673 int __init omap1_clk_init(void)
674 {
675 struct omap_clk *c;
676 const struct omap_clock_config *info;
677 int crystal_type = 0; /* Default 12 MHz */
678 u32 reg, cpu_mask;
679
680 #ifdef CONFIG_DEBUG_LL
681 /*
682 * Resets some clocks that may be left on from bootloader,
683 * but leaves serial clocks on.
684 */
685 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
686 #endif
687
688 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
689 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
690 omap_writew(reg, SOFT_REQ_REG);
691 if (!cpu_is_omap15xx())
692 omap_writew(0, SOFT_REQ_REG2);
693
694 clk_init(&omap1_clk_functions);
695
696 /* By default all idlect1 clocks are allowed to idle */
697 arm_idlect1_mask = ~0;
698
699 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
700 clk_preinit(c->lk.clk);
701
702 cpu_mask = 0;
703 if (cpu_is_omap16xx())
704 cpu_mask |= CK_16XX;
705 if (cpu_is_omap1510())
706 cpu_mask |= CK_1510;
707 if (cpu_is_omap7xx())
708 cpu_mask |= CK_7XX;
709 if (cpu_is_omap310())
710 cpu_mask |= CK_310;
711
712 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
713 if (c->cpu & cpu_mask) {
714 clkdev_add(&c->lk);
715 clk_register(c->lk.clk);
716 }
717
718 /* Pointers to these clocks are needed by code in clock.c */
719 api_ck_p = clk_get(NULL, "api_ck");
720 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
721 ck_ref_p = clk_get(NULL, "ck_ref");
722
723 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
724 if (info != NULL) {
725 if (!cpu_is_omap15xx())
726 crystal_type = info->system_clock_type;
727 }
728
729 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
730 ck_ref.rate = 13000000;
731 #elif defined(CONFIG_ARCH_OMAP16XX)
732 if (crystal_type == 2)
733 ck_ref.rate = 19200000;
734 #endif
735
736 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
737 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
738 omap_readw(ARM_CKCTL));
739
740 /* We want to be in syncronous scalable mode */
741 omap_writew(0x1000, ARM_SYSST);
742
743 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
744 /* Use values set by bootloader. Determine PLL rate and recalculate
745 * dependent clocks as if kernel had changed PLL or divisors.
746 */
747 {
748 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
749
750 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
751 if (pll_ctl_val & 0x10) {
752 /* PLL enabled, apply multiplier and divisor */
753 if (pll_ctl_val & 0xf80)
754 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
755 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
756 } else {
757 /* PLL disabled, apply bypass divisor */
758 switch (pll_ctl_val & 0xc) {
759 case 0:
760 break;
761 case 0x4:
762 ck_dpll1.rate /= 2;
763 break;
764 default:
765 ck_dpll1.rate /= 4;
766 break;
767 }
768 }
769 }
770 #else
771 /* Find the highest supported frequency and enable it */
772 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
773 printk(KERN_ERR "System frequencies not set. Check your config.\n");
774 /* Guess sane values (60MHz) */
775 omap_writew(0x2290, DPLL_CTL);
776 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
777 ck_dpll1.rate = 60000000;
778 }
779 #endif
780 propagate_rate(&ck_dpll1);
781 /* Cache rates for clocks connected to ck_ref (not dpll1) */
782 propagate_rate(&ck_ref);
783 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
784 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
785 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
786 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
787 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
788
789 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
790 /* Select slicer output as OMAP input clock */
791 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
792 #endif
793
794 /* Amstrad Delta wants BCLK high when inactive */
795 if (machine_is_ams_delta())
796 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
797 (1 << SDW_MCLK_INV_BIT),
798 ULPD_CLOCK_CTRL);
799
800 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
801 /* (on 730, bit 13 must not be cleared) */
802 if (cpu_is_omap7xx())
803 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
804 else
805 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
806
807 /* Put DSP/MPUI into reset until needed */
808 omap_writew(0, ARM_RSTCT1);
809 omap_writew(1, ARM_RSTCT2);
810 omap_writew(0x400, ARM_IDLECT1);
811
812 /*
813 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
814 * of the ARM_IDLECT2 register must be set to zero. The power-on
815 * default value of this bit is one.
816 */
817 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
818
819 /*
820 * Only enable those clocks we will need, let the drivers
821 * enable other clocks as necessary
822 */
823 clk_enable(&armper_ck.clk);
824 clk_enable(&armxor_ck.clk);
825 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
826
827 if (cpu_is_omap15xx())
828 clk_enable(&arm_gpio_ck);
829
830 return 0;
831 }
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