arch/arm/plat-omap/include/plat/iommu2.h

   1 /*
   2  * omap iommu: omap2 architecture specific definitions
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __MACH_IOMMU2_H
  14 #define __MACH_IOMMU2_H
  15
  16 #include <linux/io.h>
  17
  18 /*
  19  * MMU Register offsets
  20  */
  21 #define MMU_REVISION            0x00
  22 #define MMU_SYSCONFIG           0x10
  23 #define MMU_SYSSTATUS           0x14
  24 #define MMU_IRQSTATUS           0x18
  25 #define MMU_IRQENABLE           0x1c
  26 #define MMU_WALKING_ST          0x40
  27 #define MMU_CNTL                0x44
  28 #define MMU_FAULT_AD            0x48
  29 #define MMU_TTB                 0x4c
  30 #define MMU_LOCK                0x50
  31 #define MMU_LD_TLB              0x54
  32 #define MMU_CAM                 0x58
  33 #define MMU_RAM                 0x5c
  34 #define MMU_GFLUSH              0x60
  35 #define MMU_FLUSH_ENTRY         0x64
  36 #define MMU_READ_CAM            0x68
  37 #define MMU_READ_RAM            0x6c
  38 #define MMU_EMU_FAULT_AD        0x70
  39
  40 #define MMU_REG_SIZE            256
  41
  42 /*
  43  * MMU Register bit definitions
  44  */
  45 #define MMU_LOCK_BASE_SHIFT     10
  46 #define MMU_LOCK_BASE_MASK      (0x1f << MMU_LOCK_BASE_SHIFT)
  47 #define MMU_LOCK_BASE(x)        \
  48         ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
  49
  50 #define MMU_LOCK_VICT_SHIFT     4
  51 #define MMU_LOCK_VICT_MASK      (0x1f << MMU_LOCK_VICT_SHIFT)
  52 #define MMU_LOCK_VICT(x)        \
  53         ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
  54
  55 #define MMU_CAM_VATAG_SHIFT     12
  56 #define MMU_CAM_VATAG_MASK \
  57         ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
  58 #define MMU_CAM_P               (1 << 3)
  59 #define MMU_CAM_V               (1 << 2)
  60 #define MMU_CAM_PGSZ_MASK       3
  61 #define MMU_CAM_PGSZ_1M         (0 << 0)
  62 #define MMU_CAM_PGSZ_64K        (1 << 0)
  63 #define MMU_CAM_PGSZ_4K         (2 << 0)
  64 #define MMU_CAM_PGSZ_16M        (3 << 0)
  65
  66 #define MMU_RAM_PADDR_SHIFT     12
  67 #define MMU_RAM_PADDR_MASK \
  68         ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
  69 #define MMU_RAM_ENDIAN_SHIFT    9
  70 #define MMU_RAM_ENDIAN_MASK     (1 << MMU_RAM_ENDIAN_SHIFT)
  71 #define MMU_RAM_ENDIAN_BIG      (1 << MMU_RAM_ENDIAN_SHIFT)
  72 #define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
  73 #define MMU_RAM_ELSZ_SHIFT      7
  74 #define MMU_RAM_ELSZ_MASK       (3 << MMU_RAM_ELSZ_SHIFT)
  75 #define MMU_RAM_ELSZ_8          (0 << MMU_RAM_ELSZ_SHIFT)
  76 #define MMU_RAM_ELSZ_16         (1 << MMU_RAM_ELSZ_SHIFT)
  77 #define MMU_RAM_ELSZ_32         (2 << MMU_RAM_ELSZ_SHIFT)
  78 #define MMU_RAM_ELSZ_NONE       (3 << MMU_RAM_ELSZ_SHIFT)
  79 #define MMU_RAM_MIXED_SHIFT     6
  80 #define MMU_RAM_MIXED_MASK      (1 << MMU_RAM_MIXED_SHIFT)
  81 #define MMU_RAM_MIXED           MMU_RAM_MIXED_MASK
  82
  83 /*
  84  * register accessors
  85  */
  86 static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
  87 {
  88         return __raw_readl(obj->regbase + offs);
  89 }
  90
  91 static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
  92 {
  93         __raw_writel(val, obj->regbase + offs);
  94 }
  95
  96 #endif /* __MACH_IOMMU2_H */