arch/arm/plat-omap/include/plat/omap-pm.h

   1 /*
   2  * omap-pm.h - OMAP power management interface
   3  *
   4  * Copyright (C) 2008-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2008-2009 Nokia Corporation
   6  * Paul Walmsley
   7  *
   8  * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
   9  * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
  10  * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
  11  * Richard Woodruff
  12  */
  13
  14 #ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
  15 #define ASM_ARM_ARCH_OMAP_OMAP_PM_H
  16
  17 #include <linux/device.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include "powerdomain.h"
  21
  22 /**
  23  * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
  24  * @rate: target clock rate
  25  * @opp_id: OPP ID
  26  * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
  27  *
  28  * Operating performance point data.  Can vary by OMAP chip and board.
  29  */
  30 struct omap_opp {
  31         unsigned long rate;
  32         u8 opp_id;
  33         u16 min_vdd;
  34 };
  35
  36 extern struct omap_opp *mpu_opps;
  37 extern struct omap_opp *dsp_opps;
  38 extern struct omap_opp *l3_opps;
  39
  40 /*
  41  * agent_id values for use with omap_pm_set_min_bus_tput():
  42  *
  43  * OCP_INITIATOR_AGENT is only valid for devices that can act as
  44  * initiators -- it represents the device's L3 interconnect
  45  * connection.  OCP_TARGET_AGENT represents the device's L4
  46  * interconnect connection.
  47  */
  48 #define OCP_TARGET_AGENT                1
  49 #define OCP_INITIATOR_AGENT             2
  50
  51 /**
  52  * omap_pm_if_early_init - OMAP PM init code called before clock fw init
  53  * @mpu_opp_table: array ptr to struct omap_opp for MPU
  54  * @dsp_opp_table: array ptr to struct omap_opp for DSP
  55  * @l3_opp_table : array ptr to struct omap_opp for CORE
  56  *
  57  * Initialize anything that must be configured before the clock
  58  * framework starts.  The "_if_" is to avoid name collisions with the
  59  * PM idle-loop code.
  60  */
  61 int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
  62                                  struct omap_opp *dsp_opp_table,
  63                                  struct omap_opp *l3_opp_table);
  64
  65 /**
  66  * omap_pm_if_init - OMAP PM init code called after clock fw init
  67  *
  68  * The main initialization code.  OPP tables are passed in here.  The
  69  * "_if_" is to avoid name collisions with the PM idle-loop code.
  70  */
  71 int __init omap_pm_if_init(void);
  72
  73 /**
  74  * omap_pm_if_exit - OMAP PM exit code
  75  *
  76  * Exit code; currently unused.  The "_if_" is to avoid name
  77  * collisions with the PM idle-loop code.
  78  */
  79 void omap_pm_if_exit(void);
  80
  81 /*
  82  * Device-driver-originated constraints (via board-*.c files, platform_data)
  83  */
  84
  85
  86 /**
  87  * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
  88  * @dev: struct device * requesting the constraint
  89  * @t: maximum MPU wakeup latency in microseconds
  90  *
  91  * Request that the maximum interrupt latency for the MPU to be no
  92  * greater than 't' microseconds. "Interrupt latency" in this case is
  93  * defined as the elapsed time from the occurrence of a hardware or
  94  * timer interrupt to the time when the device driver's interrupt
  95  * service routine has been entered by the MPU.
  96  *
  97  * It is intended that underlying PM code will use this information to
  98  * determine what power state to put the MPU powerdomain into, and
  99  * possibly the CORE powerdomain as well, since interrupt handling
 100  * code currently runs from SDRAM.  Advanced PM or board*.c code may
 101  * also configure interrupt controller priorities, OCP bus priorities,
 102  * CPU speed(s), etc.
 103  *
 104  * This function will not affect device wakeup latency, e.g., time
 105  * elapsed from when a device driver enables a hardware device with
 106  * clk_enable(), to when the device is ready for register access or
 107  * other use.  To control this device wakeup latency, use
 108  * set_max_dev_wakeup_lat()
 109  *
 110  * Multiple calls to set_max_mpu_wakeup_lat() will replace the
 111  * previous t value.  To remove the latency target for the MPU, call
 112  * with t = -1.
 113  *
 114  * No return value.
 115  */
 116 void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
 117
 118
 119 /**
 120  * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
 121  * @dev: struct device * requesting the constraint
 122  * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
 123  * @r: minimum throughput (in KiB/s)
 124  *
 125  * Request that the minimum data throughput on the OCP interconnect
 126  * attached to device 'dev' interconnect agent 'tbus_id' be no less
 127  * than 'r' KiB/s.
 128  *
 129  * It is expected that the OMAP PM or bus code will use this
 130  * information to set the interconnect clock to run at the lowest
 131  * possible speed that satisfies all current system users.  The PM or
 132  * bus code will adjust the estimate based on its model of the bus, so
 133  * device driver authors should attempt to specify an accurate
 134  * quantity for their device use case, and let the PM or bus code
 135  * overestimate the numbers as necessary to handle request/response
 136  * latency, other competing users on the system, etc.  On OMAP2/3, if
 137  * a driver requests a minimum L4 interconnect speed constraint, the
 138  * code will also need to add an minimum L3 interconnect speed
 139  * constraint,
 140  *
 141  * Multiple calls to set_min_bus_tput() will replace the previous rate
 142  * value for this device.  To remove the interconnect throughput
 143  * restriction for this device, call with r = 0.
 144  *
 145  * No return value.
 146  */
 147 void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
 148
 149
 150 /**
 151  * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
 152  * @dev: struct device *
 153  * @t: maximum device wakeup latency in microseconds
 154  *
 155  * Request that the maximum amount of time necessary for a device to
 156  * become accessible after its clocks are enabled should be no greater
 157  * than 't' microseconds.  Specifically, this represents the time from
 158  * when a device driver enables device clocks with clk_enable(), to
 159  * when the register reads and writes on the device will succeed.
 160  * This function should be called before clk_disable() is called,
 161  * since the power state transition decision may be made during
 162  * clk_disable().
 163  *
 164  * It is intended that underlying PM code will use this information to
 165  * determine what power state to put the powerdomain enclosing this
 166  * device into.
 167  *
 168  * Multiple calls to set_max_dev_wakeup_lat() will replace the
 169  * previous wakeup latency values for this device.  To remove the wakeup
 170  * latency restriction for this device, call with t = -1.
 171  *
 172  * No return value.
 173  */
 174 void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
 175
 176
 177 /**
 178  * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
 179  * @dev: struct device *
 180  * @t: maximum DMA transfer start latency in microseconds
 181  *
 182  * Request that the maximum system DMA transfer start latency for this
 183  * device 'dev' should be no greater than 't' microseconds.  "DMA
 184  * transfer start latency" here is defined as the elapsed time from
 185  * when a device (e.g., McBSP) requests that a system DMA transfer
 186  * start or continue, to the time at which data starts to flow into
 187  * that device from the system DMA controller.
 188  *
 189  * It is intended that underlying PM code will use this information to
 190  * determine what power state to put the CORE powerdomain into.
 191  *
 192  * Since system DMA transfers may not involve the MPU, this function
 193  * will not affect MPU wakeup latency.  Use set_max_cpu_lat() to do
 194  * so.  Similarly, this function will not affect device wakeup latency
 195  * -- use set_max_dev_wakeup_lat() to affect that.
 196  *
 197  * Multiple calls to set_max_sdma_lat() will replace the previous t
 198  * value for this device.  To remove the maximum DMA latency for this
 199  * device, call with t = -1.
 200  *
 201  * No return value.
 202  */
 203 void omap_pm_set_max_sdma_lat(struct device *dev, long t);
 204
 205
 206 /*
 207  * DSP Bridge-specific constraints
 208  */
 209
 210 /**
 211  * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
 212  *
 213  * Intended for use by DSPBridge.  Returns an array of OPP->DSP clock
 214  * frequency entries.  The final item in the array should have .rate =
 215  * .opp_id = 0.
 216  */
 217 const struct omap_opp *omap_pm_dsp_get_opp_table(void);
 218
 219 /**
 220  * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
 221  * @opp_id: target DSP OPP ID
 222  *
 223  * Set a minimum OPP ID for the DSP.  This is intended to be called
 224  * only from the DSP Bridge MPU-side driver.  Unfortunately, the only
 225  * information that code receives from the DSP/BIOS load estimator is the
 226  * target OPP ID; hence, this interface.  No return value.
 227  */
 228 void omap_pm_dsp_set_min_opp(u8 opp_id);
 229
 230 /**
 231  * omap_pm_dsp_get_opp - report the current DSP OPP ID
 232  *
 233  * Report the current OPP for the DSP.  Since on OMAP3, the DSP and
 234  * MPU share a single voltage domain, the OPP ID returned back may
 235  * represent a higher DSP speed than the OPP requested via
 236  * omap_pm_dsp_set_min_opp().
 237  *
 238  * Returns the current VDD1 OPP ID, or 0 upon error.
 239  */
 240 u8 omap_pm_dsp_get_opp(void);
 241
 242
 243 /*
 244  * CPUFreq-originated constraint
 245  *
 246  * In the future, this should be handled by custom OPP clocktype
 247  * functions.
 248  */
 249
 250 /**
 251  * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
 252  *
 253  * Provide a frequency table usable by CPUFreq for the current chip/board.
 254  * Returns a pointer to a struct cpufreq_frequency_table array or NULL
 255  * upon error.
 256  */
 257 struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
 258
 259 /**
 260  * omap_pm_cpu_set_freq - set the current minimum MPU frequency
 261  * @f: MPU frequency in Hz
 262  *
 263  * Set the current minimum CPU frequency.  The actual CPU frequency
 264  * used could end up higher if the DSP requested a higher OPP.
 265  * Intended to be called by plat-omap/cpu_omap.c:omap_target().  No
 266  * return value.
 267  */
 268 void omap_pm_cpu_set_freq(unsigned long f);
 269
 270 /**
 271  * omap_pm_cpu_get_freq - report the current CPU frequency
 272  *
 273  * Returns the current MPU frequency, or 0 upon error.
 274  */
 275 unsigned long omap_pm_cpu_get_freq(void);
 276
 277
 278 /*
 279  * Device context loss tracking
 280  */
 281
 282 /**
 283  * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
 284  * @dev: struct device *
 285  *
 286  * This function returns the number of times that the device @dev has
 287  * lost its internal context.  This generally occurs on a powerdomain
 288  * transition to OFF.  Drivers use this as an optimization to avoid restoring
 289  * context if the device hasn't lost it.  To use, drivers should initially
 290  * call this in their context save functions and store the result.  Early in
 291  * the driver's context restore function, the driver should call this function
 292  * again, and compare the result to the stored counter.  If they differ, the
 293  * driver must restore device context.   If the number of context losses
 294  * exceeds the maximum positive integer, the function will wrap to 0 and
 295  * continue counting.  Returns the number of context losses for this device,
 296  * or -EINVAL upon error.
 297  */
 298 int omap_pm_get_dev_context_loss_count(struct device *dev);
 299
 300
 301 #endif