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MIPS: SB1250: Include correct header and fix a warning
[linux-2.6/linux-mips.git] / arch / mips / kernel / traps.c
blob1a4dd657ccb943b6abbf1ff200d263bd7ce61d5d
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/notifier.h>
29
30 #include <asm/bootinfo.h>
31 #include <asm/branch.h>
32 #include <asm/break.h>
33 #include <asm/cop2.h>
34 #include <asm/cpu.h>
35 #include <asm/dsp.h>
36 #include <asm/fpu.h>
37 #include <asm/fpu_emulator.h>
38 #include <asm/mipsregs.h>
39 #include <asm/mipsmtregs.h>
40 #include <asm/module.h>
41 #include <asm/pgtable.h>
42 #include <asm/ptrace.h>
43 #include <asm/sections.h>
44 #include <asm/system.h>
45 #include <asm/tlbdebug.h>
46 #include <asm/traps.h>
47 #include <asm/uaccess.h>
48 #include <asm/watch.h>
49 #include <asm/mmu_context.h>
50 #include <asm/types.h>
51 #include <asm/stacktrace.h>
52 #include <asm/irq.h>
53 #include <asm/uasm.h>
54
55 extern void check_wait(void);
56 extern asmlinkage void r4k_wait(void);
57 extern asmlinkage void rollback_handle_int(void);
58 extern asmlinkage void handle_int(void);
59 extern asmlinkage void handle_tlbm(void);
60 extern asmlinkage void handle_tlbl(void);
61 extern asmlinkage void handle_tlbs(void);
62 extern asmlinkage void handle_adel(void);
63 extern asmlinkage void handle_ades(void);
64 extern asmlinkage void handle_ibe(void);
65 extern asmlinkage void handle_dbe(void);
66 extern asmlinkage void handle_sys(void);
67 extern asmlinkage void handle_bp(void);
68 extern asmlinkage void handle_ri(void);
69 extern asmlinkage void handle_ri_rdhwr_vivt(void);
70 extern asmlinkage void handle_ri_rdhwr(void);
71 extern asmlinkage void handle_cpu(void);
72 extern asmlinkage void handle_ov(void);
73 extern asmlinkage void handle_tr(void);
74 extern asmlinkage void handle_fpe(void);
75 extern asmlinkage void handle_mdmx(void);
76 extern asmlinkage void handle_watch(void);
77 extern asmlinkage void handle_mt(void);
78 extern asmlinkage void handle_dsp(void);
79 extern asmlinkage void handle_mcheck(void);
80 extern asmlinkage void handle_reserved(void);
81
82 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
83 struct mips_fpu_struct *ctx, int has_fpu);
84
85 void (*board_be_init)(void);
86 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
87 void (*board_nmi_handler_setup)(void);
88 void (*board_ejtag_handler_setup)(void);
89 void (*board_bind_eic_interrupt)(int irq, int regset);
90
91
92 static void show_raw_backtrace(unsigned long reg29)
93 {
94 unsigned long *sp = (unsigned long *)(reg29 & ~3);
95 unsigned long addr;
96
97 printk("Call Trace:");
98 #ifdef CONFIG_KALLSYMS
99 printk("\n");
100 #endif
101 while (!kstack_end(sp)) {
102 unsigned long __user *p =
103 (unsigned long __user *)(unsigned long)sp++;
104 if (__get_user(addr, p)) {
105 printk(" (Bad stack address)");
106 break;
107 }
108 if (__kernel_text_address(addr))
109 print_ip_sym(addr);
110 }
111 printk("\n");
112 }
113
114 #ifdef CONFIG_KALLSYMS
115 int raw_show_trace;
116 static int __init set_raw_show_trace(char *str)
117 {
118 raw_show_trace = 1;
119 return 1;
120 }
121 __setup("raw_show_trace", set_raw_show_trace);
122 #endif
123
124 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
125 {
126 unsigned long sp = regs->regs[29];
127 unsigned long ra = regs->regs[31];
128 unsigned long pc = regs->cp0_epc;
129
130 if (raw_show_trace || !__kernel_text_address(pc)) {
131 show_raw_backtrace(sp);
132 return;
133 }
134 printk("Call Trace:\n");
135 do {
136 print_ip_sym(pc);
137 pc = unwind_stack(task, &sp, pc, &ra);
138 } while (pc);
139 printk("\n");
140 }
141
142 /*
143 * This routine abuses get_user()/put_user() to reference pointers
144 * with at least a bit of error checking ...
145 */
146 static void show_stacktrace(struct task_struct *task,
147 const struct pt_regs *regs)
148 {
149 const int field = 2 * sizeof(unsigned long);
150 long stackdata;
151 int i;
152 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
153
154 printk("Stack :");
155 i = 0;
156 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
157 if (i && ((i % (64 / field)) == 0))
158 printk("\n ");
159 if (i > 39) {
160 printk(" ...");
161 break;
162 }
163
164 if (__get_user(stackdata, sp++)) {
165 printk(" (Bad stack address)");
166 break;
167 }
168
169 printk(" %0*lx", field, stackdata);
170 i++;
171 }
172 printk("\n");
173 show_backtrace(task, regs);
174 }
175
176 void show_stack(struct task_struct *task, unsigned long *sp)
177 {
178 struct pt_regs regs;
179 if (sp) {
180 regs.regs[29] = (unsigned long)sp;
181 regs.regs[31] = 0;
182 regs.cp0_epc = 0;
183 } else {
184 if (task && task != current) {
185 regs.regs[29] = task->thread.reg29;
186 regs.regs[31] = 0;
187 regs.cp0_epc = task->thread.reg31;
188 } else {
189 prepare_frametrace(&regs);
190 }
191 }
192 show_stacktrace(task, &regs);
193 }
194
195 /*
196 * The architecture-independent dump_stack generator
197 */
198 void dump_stack(void)
199 {
200 struct pt_regs regs;
201
202 prepare_frametrace(&regs);
203 show_backtrace(current, &regs);
204 }
205
206 EXPORT_SYMBOL(dump_stack);
207
208 static void show_code(unsigned int __user *pc)
209 {
210 long i;
211 unsigned short __user *pc16 = NULL;
212
213 printk("\nCode:");
214
215 if ((unsigned long)pc & 1)
216 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
217 for(i = -3 ; i < 6 ; i++) {
218 unsigned int insn;
219 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
220 printk(" (Bad address in epc)\n");
221 break;
222 }
223 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
224 }
225 }
226
227 static void __show_regs(const struct pt_regs *regs)
228 {
229 const int field = 2 * sizeof(unsigned long);
230 unsigned int cause = regs->cp0_cause;
231 int i;
232
233 printk("Cpu %d\n", smp_processor_id());
234
235 /*
236 * Saved main processor registers
237 */
238 for (i = 0; i < 32; ) {
239 if ((i % 4) == 0)
240 printk("$%2d :", i);
241 if (i == 0)
242 printk(" %0*lx", field, 0UL);
243 else if (i == 26 || i == 27)
244 printk(" %*s", field, "");
245 else
246 printk(" %0*lx", field, regs->regs[i]);
247
248 i++;
249 if ((i % 4) == 0)
250 printk("\n");
251 }
252
253 #ifdef CONFIG_CPU_HAS_SMARTMIPS
254 printk("Acx : %0*lx\n", field, regs->acx);
255 #endif
256 printk("Hi : %0*lx\n", field, regs->hi);
257 printk("Lo : %0*lx\n", field, regs->lo);
258
259 /*
260 * Saved cp0 registers
261 */
262 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
263 (void *) regs->cp0_epc);
264 printk(" %s\n", print_tainted());
265 printk("ra : %0*lx %pS\n", field, regs->regs[31],
266 (void *) regs->regs[31]);
267
268 printk("Status: %08x ", (uint32_t) regs->cp0_status);
269
270 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
271 if (regs->cp0_status & ST0_KUO)
272 printk("KUo ");
273 if (regs->cp0_status & ST0_IEO)
274 printk("IEo ");
275 if (regs->cp0_status & ST0_KUP)
276 printk("KUp ");
277 if (regs->cp0_status & ST0_IEP)
278 printk("IEp ");
279 if (regs->cp0_status & ST0_KUC)
280 printk("KUc ");
281 if (regs->cp0_status & ST0_IEC)
282 printk("IEc ");
283 } else {
284 if (regs->cp0_status & ST0_KX)
285 printk("KX ");
286 if (regs->cp0_status & ST0_SX)
287 printk("SX ");
288 if (regs->cp0_status & ST0_UX)
289 printk("UX ");
290 switch (regs->cp0_status & ST0_KSU) {
291 case KSU_USER:
292 printk("USER ");
293 break;
294 case KSU_SUPERVISOR:
295 printk("SUPERVISOR ");
296 break;
297 case KSU_KERNEL:
298 printk("KERNEL ");
299 break;
300 default:
301 printk("BAD_MODE ");
302 break;
303 }
304 if (regs->cp0_status & ST0_ERL)
305 printk("ERL ");
306 if (regs->cp0_status & ST0_EXL)
307 printk("EXL ");
308 if (regs->cp0_status & ST0_IE)
309 printk("IE ");
310 }
311 printk("\n");
312
313 printk("Cause : %08x\n", cause);
314
315 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
316 if (1 <= cause && cause <= 5)
317 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
318
319 printk("PrId : %08x (%s)\n", read_c0_prid(),
320 cpu_name_string());
321 }
322
323 /*
324 * FIXME: really the generic show_regs should take a const pointer argument.
325 */
326 void show_regs(struct pt_regs *regs)
327 {
328 __show_regs((struct pt_regs *)regs);
329 }
330
331 void show_registers(const struct pt_regs *regs)
332 {
333 const int field = 2 * sizeof(unsigned long);
334
335 __show_regs(regs);
336 print_modules();
337 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
338 current->comm, current->pid, current_thread_info(), current,
339 field, current_thread_info()->tp_value);
340 if (cpu_has_userlocal) {
341 unsigned long tls;
342
343 tls = read_c0_userlocal();
344 if (tls != current_thread_info()->tp_value)
345 printk("*HwTLS: %0*lx\n", field, tls);
346 }
347
348 show_stacktrace(current, regs);
349 show_code((unsigned int __user *) regs->cp0_epc);
350 printk("\n");
351 }
352
353 static DEFINE_SPINLOCK(die_lock);
354
355 void __noreturn die(const char * str, const struct pt_regs * regs)
356 {
357 static int die_counter;
358 #ifdef CONFIG_MIPS_MT_SMTC
359 unsigned long dvpret = dvpe();
360 #endif /* CONFIG_MIPS_MT_SMTC */
361
362 console_verbose();
363 spin_lock_irq(&die_lock);
364 bust_spinlocks(1);
365 #ifdef CONFIG_MIPS_MT_SMTC
366 mips_mt_regdump(dvpret);
367 #endif /* CONFIG_MIPS_MT_SMTC */
368 printk("%s[#%d]:\n", str, ++die_counter);
369 show_registers(regs);
370 add_taint(TAINT_DIE);
371 spin_unlock_irq(&die_lock);
372
373 if (in_interrupt())
374 panic("Fatal exception in interrupt");
375
376 if (panic_on_oops) {
377 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
378 ssleep(5);
379 panic("Fatal exception");
380 }
381
382 do_exit(SIGSEGV);
383 }
384
385 extern struct exception_table_entry __start___dbe_table[];
386 extern struct exception_table_entry __stop___dbe_table[];
387
388 __asm__(
389 " .section __dbe_table, \"a\"\n"
390 " .previous \n");
391
392 /* Given an address, look for it in the exception tables. */
393 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
394 {
395 const struct exception_table_entry *e;
396
397 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
398 if (!e)
399 e = search_module_dbetables(addr);
400 return e;
401 }
402
403 asmlinkage void do_be(struct pt_regs *regs)
404 {
405 const int field = 2 * sizeof(unsigned long);
406 const struct exception_table_entry *fixup = NULL;
407 int data = regs->cp0_cause & 4;
408 int action = MIPS_BE_FATAL;
409
410 /* XXX For now. Fixme, this searches the wrong table ... */
411 if (data && !user_mode(regs))
412 fixup = search_dbe_tables(exception_epc(regs));
413
414 if (fixup)
415 action = MIPS_BE_FIXUP;
416
417 if (board_be_handler)
418 action = board_be_handler(regs, fixup != NULL);
419
420 switch (action) {
421 case MIPS_BE_DISCARD:
422 return;
423 case MIPS_BE_FIXUP:
424 if (fixup) {
425 regs->cp0_epc = fixup->nextinsn;
426 return;
427 }
428 break;
429 default:
430 break;
431 }
432
433 /*
434 * Assume it would be too dangerous to continue ...
435 */
436 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
437 data ? "Data" : "Instruction",
438 field, regs->cp0_epc, field, regs->regs[31]);
439 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
440 == NOTIFY_STOP)
441 return;
442
443 die_if_kernel("Oops", regs);
444 force_sig(SIGBUS, current);
445 }
446
447 /*
448 * ll/sc, rdhwr, sync emulation
449 */
450
451 #define OPCODE 0xfc000000
452 #define BASE 0x03e00000
453 #define RT 0x001f0000
454 #define OFFSET 0x0000ffff
455 #define LL 0xc0000000
456 #define SC 0xe0000000
457 #define SPEC0 0x00000000
458 #define SPEC3 0x7c000000
459 #define RD 0x0000f800
460 #define FUNC 0x0000003f
461 #define SYNC 0x0000000f
462 #define RDHWR 0x0000003b
463
464 /*
465 * The ll_bit is cleared by r*_switch.S
466 */
467
468 unsigned int ll_bit;
469 struct task_struct *ll_task;
470
471 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
472 {
473 unsigned long value, __user *vaddr;
474 long offset;
475
476 /*
477 * analyse the ll instruction that just caused a ri exception
478 * and put the referenced address to addr.
479 */
480
481 /* sign extend offset */
482 offset = opcode & OFFSET;
483 offset <<= 16;
484 offset >>= 16;
485
486 vaddr = (unsigned long __user *)
487 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
488
489 if ((unsigned long)vaddr & 3)
490 return SIGBUS;
491 if (get_user(value, vaddr))
492 return SIGSEGV;
493
494 preempt_disable();
495
496 if (ll_task == NULL || ll_task == current) {
497 ll_bit = 1;
498 } else {
499 ll_bit = 0;
500 }
501 ll_task = current;
502
503 preempt_enable();
504
505 regs->regs[(opcode & RT) >> 16] = value;
506
507 return 0;
508 }
509
510 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
511 {
512 unsigned long __user *vaddr;
513 unsigned long reg;
514 long offset;
515
516 /*
517 * analyse the sc instruction that just caused a ri exception
518 * and put the referenced address to addr.
519 */
520
521 /* sign extend offset */
522 offset = opcode & OFFSET;
523 offset <<= 16;
524 offset >>= 16;
525
526 vaddr = (unsigned long __user *)
527 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
528 reg = (opcode & RT) >> 16;
529
530 if ((unsigned long)vaddr & 3)
531 return SIGBUS;
532
533 preempt_disable();
534
535 if (ll_bit == 0 || ll_task != current) {
536 regs->regs[reg] = 0;
537 preempt_enable();
538 return 0;
539 }
540
541 preempt_enable();
542
543 if (put_user(regs->regs[reg], vaddr))
544 return SIGSEGV;
545
546 regs->regs[reg] = 1;
547
548 return 0;
549 }
550
551 /*
552 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
553 * opcodes are supposed to result in coprocessor unusable exceptions if
554 * executed on ll/sc-less processors. That's the theory. In practice a
555 * few processors such as NEC's VR4100 throw reserved instruction exceptions
556 * instead, so we're doing the emulation thing in both exception handlers.
557 */
558 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
559 {
560 if ((opcode & OPCODE) == LL)
561 return simulate_ll(regs, opcode);
562 if ((opcode & OPCODE) == SC)
563 return simulate_sc(regs, opcode);
564
565 return -1; /* Must be something else ... */
566 }
567
568 /*
569 * Simulate trapping 'rdhwr' instructions to provide user accessible
570 * registers not implemented in hardware.
571 */
572 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
573 {
574 struct thread_info *ti = task_thread_info(current);
575
576 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
577 int rd = (opcode & RD) >> 11;
578 int rt = (opcode & RT) >> 16;
579 switch (rd) {
580 case 0: /* CPU number */
581 regs->regs[rt] = smp_processor_id();
582 return 0;
583 case 1: /* SYNCI length */
584 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
585 current_cpu_data.icache.linesz);
586 return 0;
587 case 2: /* Read count register */
588 regs->regs[rt] = read_c0_count();
589 return 0;
590 case 3: /* Count register resolution */
591 switch (current_cpu_data.cputype) {
592 case CPU_20KC:
593 case CPU_25KF:
594 regs->regs[rt] = 1;
595 break;
596 default:
597 regs->regs[rt] = 2;
598 }
599 return 0;
600 case 29:
601 regs->regs[rt] = ti->tp_value;
602 return 0;
603 default:
604 return -1;
605 }
606 }
607
608 /* Not ours. */
609 return -1;
610 }
611
612 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
613 {
614 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
615 return 0;
616
617 return -1; /* Must be something else ... */
618 }
619
620 asmlinkage void do_ov(struct pt_regs *regs)
621 {
622 siginfo_t info;
623
624 die_if_kernel("Integer overflow", regs);
625
626 info.si_code = FPE_INTOVF;
627 info.si_signo = SIGFPE;
628 info.si_errno = 0;
629 info.si_addr = (void __user *) regs->cp0_epc;
630 force_sig_info(SIGFPE, &info, current);
631 }
632
633 /*
634 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
635 */
636 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
637 {
638 siginfo_t info;
639
640 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
641 == NOTIFY_STOP)
642 return;
643 die_if_kernel("FP exception in kernel code", regs);
644
645 if (fcr31 & FPU_CSR_UNI_X) {
646 int sig;
647
648 /*
649 * Unimplemented operation exception. If we've got the full
650 * software emulator on-board, let's use it...
651 *
652 * Force FPU to dump state into task/thread context. We're
653 * moving a lot of data here for what is probably a single
654 * instruction, but the alternative is to pre-decode the FP
655 * register operands before invoking the emulator, which seems
656 * a bit extreme for what should be an infrequent event.
657 */
658 /* Ensure 'resume' not overwrite saved fp context again. */
659 lose_fpu(1);
660
661 /* Run the emulator */
662 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
663
664 /*
665 * We can't allow the emulated instruction to leave any of
666 * the cause bit set in $fcr31.
667 */
668 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
669
670 /* Restore the hardware register state */
671 own_fpu(1); /* Using the FPU again. */
672
673 /* If something went wrong, signal */
674 if (sig)
675 force_sig(sig, current);
676
677 return;
678 } else if (fcr31 & FPU_CSR_INV_X)
679 info.si_code = FPE_FLTINV;
680 else if (fcr31 & FPU_CSR_DIV_X)
681 info.si_code = FPE_FLTDIV;
682 else if (fcr31 & FPU_CSR_OVF_X)
683 info.si_code = FPE_FLTOVF;
684 else if (fcr31 & FPU_CSR_UDF_X)
685 info.si_code = FPE_FLTUND;
686 else if (fcr31 & FPU_CSR_INE_X)
687 info.si_code = FPE_FLTRES;
688 else
689 info.si_code = __SI_FAULT;
690 info.si_signo = SIGFPE;
691 info.si_errno = 0;
692 info.si_addr = (void __user *) regs->cp0_epc;
693 force_sig_info(SIGFPE, &info, current);
694 }
695
696 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
697 const char *str)
698 {
699 siginfo_t info;
700 char b[40];
701
702 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
703 return;
704
705 /*
706 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
707 * insns, even for trap and break codes that indicate arithmetic
708 * failures. Weird ...
709 * But should we continue the brokenness??? --macro
710 */
711 switch (code) {
712 case BRK_OVERFLOW:
713 case BRK_DIVZERO:
714 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
715 die_if_kernel(b, regs);
716 if (code == BRK_DIVZERO)
717 info.si_code = FPE_INTDIV;
718 else
719 info.si_code = FPE_INTOVF;
720 info.si_signo = SIGFPE;
721 info.si_errno = 0;
722 info.si_addr = (void __user *) regs->cp0_epc;
723 force_sig_info(SIGFPE, &info, current);
724 break;
725 case BRK_BUG:
726 die_if_kernel("Kernel bug detected", regs);
727 force_sig(SIGTRAP, current);
728 break;
729 case BRK_MEMU:
730 /*
731 * Address errors may be deliberately induced by the FPU
732 * emulator to retake control of the CPU after executing the
733 * instruction in the delay slot of an emulated branch.
734 *
735 * Terminate if exception was recognized as a delay slot return
736 * otherwise handle as normal.
737 */
738 if (do_dsemulret(regs))
739 return;
740
741 die_if_kernel("Math emu break/trap", regs);
742 force_sig(SIGTRAP, current);
743 break;
744 default:
745 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
746 die_if_kernel(b, regs);
747 force_sig(SIGTRAP, current);
748 }
749 }
750
751 asmlinkage void do_bp(struct pt_regs *regs)
752 {
753 unsigned int opcode, bcode;
754
755 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
756 goto out_sigsegv;
757
758 /*
759 * There is the ancient bug in the MIPS assemblers that the break
760 * code starts left to bit 16 instead to bit 6 in the opcode.
761 * Gas is bug-compatible, but not always, grrr...
762 * We handle both cases with a simple heuristics. --macro
763 */
764 bcode = ((opcode >> 6) & ((1 << 20) - 1));
765 if (bcode >= (1 << 10))
766 bcode >>= 10;
767
768 do_trap_or_bp(regs, bcode, "Break");
769 return;
770
771 out_sigsegv:
772 force_sig(SIGSEGV, current);
773 }
774
775 asmlinkage void do_tr(struct pt_regs *regs)
776 {
777 unsigned int opcode, tcode = 0;
778
779 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
780 goto out_sigsegv;
781
782 /* Immediate versions don't provide a code. */
783 if (!(opcode & OPCODE))
784 tcode = ((opcode >> 6) & ((1 << 10) - 1));
785
786 do_trap_or_bp(regs, tcode, "Trap");
787 return;
788
789 out_sigsegv:
790 force_sig(SIGSEGV, current);
791 }
792
793 asmlinkage void do_ri(struct pt_regs *regs)
794 {
795 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
796 unsigned long old_epc = regs->cp0_epc;
797 unsigned int opcode = 0;
798 int status = -1;
799
800 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
801 == NOTIFY_STOP)
802 return;
803
804 die_if_kernel("Reserved instruction in kernel code", regs);
805
806 if (unlikely(compute_return_epc(regs) < 0))
807 return;
808
809 if (unlikely(get_user(opcode, epc) < 0))
810 status = SIGSEGV;
811
812 if (!cpu_has_llsc && status < 0)
813 status = simulate_llsc(regs, opcode);
814
815 if (status < 0)
816 status = simulate_rdhwr(regs, opcode);
817
818 if (status < 0)
819 status = simulate_sync(regs, opcode);
820
821 if (status < 0)
822 status = SIGILL;
823
824 if (unlikely(status > 0)) {
825 regs->cp0_epc = old_epc; /* Undo skip-over. */
826 force_sig(status, current);
827 }
828 }
829
830 /*
831 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
832 * emulated more than some threshold number of instructions, force migration to
833 * a "CPU" that has FP support.
834 */
835 static void mt_ase_fp_affinity(void)
836 {
837 #ifdef CONFIG_MIPS_MT_FPAFF
838 if (mt_fpemul_threshold > 0 &&
839 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
840 /*
841 * If there's no FPU present, or if the application has already
842 * restricted the allowed set to exclude any CPUs with FPUs,
843 * we'll skip the procedure.
844 */
845 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
846 cpumask_t tmask;
847
848 current->thread.user_cpus_allowed
849 = current->cpus_allowed;
850 cpus_and(tmask, current->cpus_allowed,
851 mt_fpu_cpumask);
852 set_cpus_allowed(current, tmask);
853 set_thread_flag(TIF_FPUBOUND);
854 }
855 }
856 #endif /* CONFIG_MIPS_MT_FPAFF */
857 }
858
859 /*
860 * No lock; only written during early bootup by CPU 0.
861 */
862 static RAW_NOTIFIER_HEAD(cu2_chain);
863
864 int __ref register_cu2_notifier(struct notifier_block *nb)
865 {
866 return raw_notifier_chain_register(&cu2_chain, nb);
867 }
868
869 int cu2_notifier_call_chain(unsigned long val, void *v)
870 {
871 return raw_notifier_call_chain(&cu2_chain, val, v);
872 }
873
874 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
875 void *data)
876 {
877 struct pt_regs *regs = data;
878
879 switch (action) {
880 default:
881 die_if_kernel("Unhandled kernel unaligned access or invalid "
882 "instruction", regs);
883 /* Fall through */
884
885 case CU2_EXCEPTION:
886 force_sig(SIGILL, current);
887 }
888
889 return NOTIFY_OK;
890 }
891
892 static struct notifier_block default_cu2_notifier = {
893 .notifier_call = default_cu2_call,
894 .priority = 0x80000000, /* Run last */
895 };
896
897 asmlinkage void do_cpu(struct pt_regs *regs)
898 {
899 unsigned int __user *epc;
900 unsigned long old_epc;
901 unsigned int opcode;
902 unsigned int cpid;
903 int status;
904 unsigned long __maybe_unused flags;
905
906 die_if_kernel("do_cpu invoked from kernel context!", regs);
907
908 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
909
910 switch (cpid) {
911 case 0:
912 epc = (unsigned int __user *)exception_epc(regs);
913 old_epc = regs->cp0_epc;
914 opcode = 0;
915 status = -1;
916
917 if (unlikely(compute_return_epc(regs) < 0))
918 return;
919
920 if (unlikely(get_user(opcode, epc) < 0))
921 status = SIGSEGV;
922
923 if (!cpu_has_llsc && status < 0)
924 status = simulate_llsc(regs, opcode);
925
926 if (status < 0)
927 status = simulate_rdhwr(regs, opcode);
928
929 if (status < 0)
930 status = SIGILL;
931
932 if (unlikely(status > 0)) {
933 regs->cp0_epc = old_epc; /* Undo skip-over. */
934 force_sig(status, current);
935 }
936
937 return;
938
939 case 1:
940 if (used_math()) /* Using the FPU again. */
941 own_fpu(1);
942 else { /* First time FPU user. */
943 init_fpu();
944 set_used_math();
945 }
946
947 if (!raw_cpu_has_fpu) {
948 int sig;
949 sig = fpu_emulator_cop1Handler(regs,
950 &current->thread.fpu, 0);
951 if (sig)
952 force_sig(sig, current);
953 else
954 mt_ase_fp_affinity();
955 }
956
957 return;
958
959 case 2:
960 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
961 break;
962
963 case 3:
964 break;
965 }
966
967 force_sig(SIGILL, current);
968 }
969
970 asmlinkage void do_mdmx(struct pt_regs *regs)
971 {
972 force_sig(SIGILL, current);
973 }
974
975 /*
976 * Called with interrupts disabled.
977 */
978 asmlinkage void do_watch(struct pt_regs *regs)
979 {
980 u32 cause;
981
982 /*
983 * Clear WP (bit 22) bit of cause register so we don't loop
984 * forever.
985 */
986 cause = read_c0_cause();
987 cause &= ~(1 << 22);
988 write_c0_cause(cause);
989
990 /*
991 * If the current thread has the watch registers loaded, save
992 * their values and send SIGTRAP. Otherwise another thread
993 * left the registers set, clear them and continue.
994 */
995 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
996 mips_read_watch_registers();
997 local_irq_enable();
998 force_sig(SIGTRAP, current);
999 } else {
1000 mips_clear_watch_registers();
1001 local_irq_enable();
1002 }
1003 }
1004
1005 asmlinkage void do_mcheck(struct pt_regs *regs)
1006 {
1007 const int field = 2 * sizeof(unsigned long);
1008 int multi_match = regs->cp0_status & ST0_TS;
1009
1010 show_regs(regs);
1011
1012 if (multi_match) {
1013 printk("Index : %0x\n", read_c0_index());
1014 printk("Pagemask: %0x\n", read_c0_pagemask());
1015 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1016 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1017 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1018 printk("\n");
1019 dump_tlb_all();
1020 }
1021
1022 show_code((unsigned int __user *) regs->cp0_epc);
1023
1024 /*
1025 * Some chips may have other causes of machine check (e.g. SB1
1026 * graduation timer)
1027 */
1028 panic("Caught Machine Check exception - %scaused by multiple "
1029 "matching entries in the TLB.",
1030 (multi_match) ? "" : "not ");
1031 }
1032
1033 asmlinkage void do_mt(struct pt_regs *regs)
1034 {
1035 int subcode;
1036
1037 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1038 >> VPECONTROL_EXCPT_SHIFT;
1039 switch (subcode) {
1040 case 0:
1041 printk(KERN_DEBUG "Thread Underflow\n");
1042 break;
1043 case 1:
1044 printk(KERN_DEBUG "Thread Overflow\n");
1045 break;
1046 case 2:
1047 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1048 break;
1049 case 3:
1050 printk(KERN_DEBUG "Gating Storage Exception\n");
1051 break;
1052 case 4:
1053 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1054 break;
1055 case 5:
1056 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1057 break;
1058 default:
1059 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1060 subcode);
1061 break;
1062 }
1063 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1064
1065 force_sig(SIGILL, current);
1066 }
1067
1068
1069 asmlinkage void do_dsp(struct pt_regs *regs)
1070 {
1071 if (cpu_has_dsp)
1072 panic("Unexpected DSP exception\n");
1073
1074 force_sig(SIGILL, current);
1075 }
1076
1077 asmlinkage void do_reserved(struct pt_regs *regs)
1078 {
1079 /*
1080 * Game over - no way to handle this if it ever occurs. Most probably
1081 * caused by a new unknown cpu type or after another deadly
1082 * hard/software error.
1083 */
1084 show_regs(regs);
1085 panic("Caught reserved exception %ld - should not happen.",
1086 (regs->cp0_cause & 0x7f) >> 2);
1087 }
1088
1089 static int __initdata l1parity = 1;
1090 static int __init nol1parity(char *s)
1091 {
1092 l1parity = 0;
1093 return 1;
1094 }
1095 __setup("nol1par", nol1parity);
1096 static int __initdata l2parity = 1;
1097 static int __init nol2parity(char *s)
1098 {
1099 l2parity = 0;
1100 return 1;
1101 }
1102 __setup("nol2par", nol2parity);
1103
1104 /*
1105 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1106 * it different ways.
1107 */
1108 static inline void parity_protection_init(void)
1109 {
1110 switch (current_cpu_type()) {
1111 case CPU_24K:
1112 case CPU_34K:
1113 case CPU_74K:
1114 case CPU_1004K:
1115 {
1116 #define ERRCTL_PE 0x80000000
1117 #define ERRCTL_L2P 0x00800000
1118 unsigned long errctl;
1119 unsigned int l1parity_present, l2parity_present;
1120
1121 errctl = read_c0_ecc();
1122 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1123
1124 /* probe L1 parity support */
1125 write_c0_ecc(errctl | ERRCTL_PE);
1126 back_to_back_c0_hazard();
1127 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1128
1129 /* probe L2 parity support */
1130 write_c0_ecc(errctl|ERRCTL_L2P);
1131 back_to_back_c0_hazard();
1132 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1133
1134 if (l1parity_present && l2parity_present) {
1135 if (l1parity)
1136 errctl |= ERRCTL_PE;
1137 if (l1parity ^ l2parity)
1138 errctl |= ERRCTL_L2P;
1139 } else if (l1parity_present) {
1140 if (l1parity)
1141 errctl |= ERRCTL_PE;
1142 } else if (l2parity_present) {
1143 if (l2parity)
1144 errctl |= ERRCTL_L2P;
1145 } else {
1146 /* No parity available */
1147 }
1148
1149 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1150
1151 write_c0_ecc(errctl);
1152 back_to_back_c0_hazard();
1153 errctl = read_c0_ecc();
1154 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1155
1156 if (l1parity_present)
1157 printk(KERN_INFO "Cache parity protection %sabled\n",
1158 (errctl & ERRCTL_PE) ? "en" : "dis");
1159
1160 if (l2parity_present) {
1161 if (l1parity_present && l1parity)
1162 errctl ^= ERRCTL_L2P;
1163 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1164 (errctl & ERRCTL_L2P) ? "en" : "dis");
1165 }
1166 }
1167 break;
1168
1169 case CPU_5KC:
1170 write_c0_ecc(0x80000000);
1171 back_to_back_c0_hazard();
1172 /* Set the PE bit (bit 31) in the c0_errctl register. */
1173 printk(KERN_INFO "Cache parity protection %sabled\n",
1174 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1175 break;
1176 case CPU_20KC:
1177 case CPU_25KF:
1178 /* Clear the DE bit (bit 16) in the c0_status register. */
1179 printk(KERN_INFO "Enable cache parity protection for "
1180 "MIPS 20KC/25KF CPUs.\n");
1181 clear_c0_status(ST0_DE);
1182 break;
1183 default:
1184 break;
1185 }
1186 }
1187
1188 asmlinkage void cache_parity_error(void)
1189 {
1190 const int field = 2 * sizeof(unsigned long);
1191 unsigned int reg_val;
1192
1193 /* For the moment, report the problem and hang. */
1194 printk("Cache error exception:\n");
1195 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1196 reg_val = read_c0_cacheerr();
1197 printk("c0_cacheerr == %08x\n", reg_val);
1198
1199 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1200 reg_val & (1<<30) ? "secondary" : "primary",
1201 reg_val & (1<<31) ? "data" : "insn");
1202 printk("Error bits: %s%s%s%s%s%s%s\n",
1203 reg_val & (1<<29) ? "ED " : "",
1204 reg_val & (1<<28) ? "ET " : "",
1205 reg_val & (1<<26) ? "EE " : "",
1206 reg_val & (1<<25) ? "EB " : "",
1207 reg_val & (1<<24) ? "EI " : "",
1208 reg_val & (1<<23) ? "E1 " : "",
1209 reg_val & (1<<22) ? "E0 " : "");
1210 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1211
1212 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1213 if (reg_val & (1<<22))
1214 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1215
1216 if (reg_val & (1<<23))
1217 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1218 #endif
1219
1220 panic("Can't handle the cache error!");
1221 }
1222
1223 /*
1224 * SDBBP EJTAG debug exception handler.
1225 * We skip the instruction and return to the next instruction.
1226 */
1227 void ejtag_exception_handler(struct pt_regs *regs)
1228 {
1229 const int field = 2 * sizeof(unsigned long);
1230 unsigned long depc, old_epc;
1231 unsigned int debug;
1232
1233 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1234 depc = read_c0_depc();
1235 debug = read_c0_debug();
1236 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1237 if (debug & 0x80000000) {
1238 /*
1239 * In branch delay slot.
1240 * We cheat a little bit here and use EPC to calculate the
1241 * debug return address (DEPC). EPC is restored after the
1242 * calculation.
1243 */
1244 old_epc = regs->cp0_epc;
1245 regs->cp0_epc = depc;
1246 __compute_return_epc(regs);
1247 depc = regs->cp0_epc;
1248 regs->cp0_epc = old_epc;
1249 } else
1250 depc += 4;
1251 write_c0_depc(depc);
1252
1253 #if 0
1254 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1255 write_c0_debug(debug | 0x100);
1256 #endif
1257 }
1258
1259 /*
1260 * NMI exception handler.
1261 */
1262 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1263 {
1264 bust_spinlocks(1);
1265 printk("NMI taken!!!!\n");
1266 die("NMI", regs);
1267 }
1268
1269 #define VECTORSPACING 0x100 /* for EI/VI mode */
1270
1271 unsigned long ebase;
1272 unsigned long exception_handlers[32];
1273 unsigned long vi_handlers[64];
1274
1275 void __init *set_except_vector(int n, void *addr)
1276 {
1277 unsigned long handler = (unsigned long) addr;
1278 unsigned long old_handler = exception_handlers[n];
1279
1280 exception_handlers[n] = handler;
1281 if (n == 0 && cpu_has_divec) {
1282 unsigned long jump_mask = ~((1 << 28) - 1);
1283 u32 *buf = (u32 *)(ebase + 0x200);
1284 unsigned int k0 = 26;
1285 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1286 uasm_i_j(&buf, handler & ~jump_mask);
1287 uasm_i_nop(&buf);
1288 } else {
1289 UASM_i_LA(&buf, k0, handler);
1290 uasm_i_jr(&buf, k0);
1291 uasm_i_nop(&buf);
1292 }
1293 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1294 }
1295 return (void *)old_handler;
1296 }
1297
1298 static asmlinkage void do_default_vi(void)
1299 {
1300 show_regs(get_irq_regs());
1301 panic("Caught unexpected vectored interrupt.");
1302 }
1303
1304 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1305 {
1306 unsigned long handler;
1307 unsigned long old_handler = vi_handlers[n];
1308 int srssets = current_cpu_data.srsets;
1309 u32 *w;
1310 unsigned char *b;
1311
1312 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1313
1314 if (addr == NULL) {
1315 handler = (unsigned long) do_default_vi;
1316 srs = 0;
1317 } else
1318 handler = (unsigned long) addr;
1319 vi_handlers[n] = (unsigned long) addr;
1320
1321 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1322
1323 if (srs >= srssets)
1324 panic("Shadow register set %d not supported", srs);
1325
1326 if (cpu_has_veic) {
1327 if (board_bind_eic_interrupt)
1328 board_bind_eic_interrupt(n, srs);
1329 } else if (cpu_has_vint) {
1330 /* SRSMap is only defined if shadow sets are implemented */
1331 if (srssets > 1)
1332 change_c0_srsmap(0xf << n*4, srs << n*4);
1333 }
1334
1335 if (srs == 0) {
1336 /*
1337 * If no shadow set is selected then use the default handler
1338 * that does normal register saving and a standard interrupt exit
1339 */
1340
1341 extern char except_vec_vi, except_vec_vi_lui;
1342 extern char except_vec_vi_ori, except_vec_vi_end;
1343 extern char rollback_except_vec_vi;
1344 char *vec_start = (cpu_wait == r4k_wait) ?
1345 &rollback_except_vec_vi : &except_vec_vi;
1346 #ifdef CONFIG_MIPS_MT_SMTC
1347 /*
1348 * We need to provide the SMTC vectored interrupt handler
1349 * not only with the address of the handler, but with the
1350 * Status.IM bit to be masked before going there.
1351 */
1352 extern char except_vec_vi_mori;
1353 const int mori_offset = &except_vec_vi_mori - vec_start;
1354 #endif /* CONFIG_MIPS_MT_SMTC */
1355 const int handler_len = &except_vec_vi_end - vec_start;
1356 const int lui_offset = &except_vec_vi_lui - vec_start;
1357 const int ori_offset = &except_vec_vi_ori - vec_start;
1358
1359 if (handler_len > VECTORSPACING) {
1360 /*
1361 * Sigh... panicing won't help as the console
1362 * is probably not configured :(
1363 */
1364 panic("VECTORSPACING too small");
1365 }
1366
1367 memcpy(b, vec_start, handler_len);
1368 #ifdef CONFIG_MIPS_MT_SMTC
1369 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1370
1371 w = (u32 *)(b + mori_offset);
1372 *w = (*w & 0xffff0000) | (0x100 << n);
1373 #endif /* CONFIG_MIPS_MT_SMTC */
1374 w = (u32 *)(b + lui_offset);
1375 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1376 w = (u32 *)(b + ori_offset);
1377 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1378 local_flush_icache_range((unsigned long)b,
1379 (unsigned long)(b+handler_len));
1380 }
1381 else {
1382 /*
1383 * In other cases jump directly to the interrupt handler
1384 *
1385 * It is the handlers responsibility to save registers if required
1386 * (eg hi/lo) and return from the exception using "eret"
1387 */
1388 w = (u32 *)b;
1389 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1390 *w = 0;
1391 local_flush_icache_range((unsigned long)b,
1392 (unsigned long)(b+8));
1393 }
1394
1395 return (void *)old_handler;
1396 }
1397
1398 void *set_vi_handler(int n, vi_handler_t addr)
1399 {
1400 return set_vi_srs_handler(n, addr, 0);
1401 }
1402
1403 extern void cpu_cache_init(void);
1404 extern void tlb_init(void);
1405 extern void flush_tlb_handlers(void);
1406
1407 /*
1408 * Timer interrupt
1409 */
1410 int cp0_compare_irq;
1411 int cp0_compare_irq_shift;
1412
1413 /*
1414 * Performance counter IRQ or -1 if shared with timer
1415 */
1416 int cp0_perfcount_irq;
1417 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1418
1419 static int __cpuinitdata noulri;
1420
1421 static int __init ulri_disable(char *s)
1422 {
1423 pr_info("Disabling ulri\n");
1424 noulri = 1;
1425
1426 return 1;
1427 }
1428 __setup("noulri", ulri_disable);
1429
1430 void __cpuinit per_cpu_trap_init(void)
1431 {
1432 unsigned int cpu = smp_processor_id();
1433 unsigned int status_set = ST0_CU0;
1434 #ifdef CONFIG_MIPS_MT_SMTC
1435 int secondaryTC = 0;
1436 int bootTC = (cpu == 0);
1437
1438 /*
1439 * Only do per_cpu_trap_init() for first TC of Each VPE.
1440 * Note that this hack assumes that the SMTC init code
1441 * assigns TCs consecutively and in ascending order.
1442 */
1443
1444 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1445 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1446 secondaryTC = 1;
1447 #endif /* CONFIG_MIPS_MT_SMTC */
1448
1449 /*
1450 * Disable coprocessors and select 32-bit or 64-bit addressing
1451 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1452 * flag that some firmware may have left set and the TS bit (for
1453 * IP27). Set XX for ISA IV code to work.
1454 */
1455 #ifdef CONFIG_64BIT
1456 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1457 #endif
1458 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1459 status_set |= ST0_XX;
1460 if (cpu_has_dsp)
1461 status_set |= ST0_MX;
1462
1463 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1464 status_set);
1465
1466 if (cpu_has_mips_r2) {
1467 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
1468
1469 if (!noulri && cpu_has_userlocal)
1470 enable |= (1 << 29);
1471
1472 write_c0_hwrena(enable);
1473 }
1474
1475 #ifdef CONFIG_MIPS_MT_SMTC
1476 if (!secondaryTC) {
1477 #endif /* CONFIG_MIPS_MT_SMTC */
1478
1479 if (cpu_has_veic || cpu_has_vint) {
1480 unsigned long sr = set_c0_status(ST0_BEV);
1481 write_c0_ebase(ebase);
1482 write_c0_status(sr);
1483 /* Setting vector spacing enables EI/VI mode */
1484 change_c0_intctl(0x3e0, VECTORSPACING);
1485 }
1486 if (cpu_has_divec) {
1487 if (cpu_has_mipsmt) {
1488 unsigned int vpflags = dvpe();
1489 set_c0_cause(CAUSEF_IV);
1490 evpe(vpflags);
1491 } else
1492 set_c0_cause(CAUSEF_IV);
1493 }
1494
1495 /*
1496 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1497 *
1498 * o read IntCtl.IPTI to determine the timer interrupt
1499 * o read IntCtl.IPPCI to determine the performance counter interrupt
1500 */
1501 if (cpu_has_mips_r2) {
1502 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1503 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1504 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1505 if (cp0_perfcount_irq == cp0_compare_irq)
1506 cp0_perfcount_irq = -1;
1507 } else {
1508 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1509 cp0_compare_irq_shift = cp0_compare_irq;
1510 cp0_perfcount_irq = -1;
1511 }
1512
1513 #ifdef CONFIG_MIPS_MT_SMTC
1514 }
1515 #endif /* CONFIG_MIPS_MT_SMTC */
1516
1517 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1518 TLBMISS_HANDLER_SETUP();
1519
1520 atomic_inc(&init_mm.mm_count);
1521 current->active_mm = &init_mm;
1522 BUG_ON(current->mm);
1523 enter_lazy_tlb(&init_mm, current);
1524
1525 #ifdef CONFIG_MIPS_MT_SMTC
1526 if (bootTC) {
1527 #endif /* CONFIG_MIPS_MT_SMTC */
1528 cpu_cache_init();
1529 tlb_init();
1530 #ifdef CONFIG_MIPS_MT_SMTC
1531 } else if (!secondaryTC) {
1532 /*
1533 * First TC in non-boot VPE must do subset of tlb_init()
1534 * for MMU countrol registers.
1535 */
1536 write_c0_pagemask(PM_DEFAULT_MASK);
1537 write_c0_wired(0);
1538 }
1539 #endif /* CONFIG_MIPS_MT_SMTC */
1540 }
1541
1542 /* Install CPU exception handler */
1543 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1544 {
1545 memcpy((void *)(ebase + offset), addr, size);
1546 local_flush_icache_range(ebase + offset, ebase + offset + size);
1547 }
1548
1549 static char panic_null_cerr[] __cpuinitdata =
1550 "Trying to set NULL cache error exception handler";
1551
1552 /*
1553 * Install uncached CPU exception handler.
1554 * This is suitable only for the cache error exception which is the only
1555 * exception handler that is being run uncached.
1556 */
1557 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1558 unsigned long size)
1559 {
1560 #ifdef CONFIG_32BIT
1561 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1562 #endif
1563 #ifdef CONFIG_64BIT
1564 unsigned long uncached_ebase = TO_UNCAC(ebase);
1565 #endif
1566
1567 if (!addr)
1568 panic(panic_null_cerr);
1569
1570 memcpy((void *)(uncached_ebase + offset), addr, size);
1571 }
1572
1573 static int __initdata rdhwr_noopt;
1574 static int __init set_rdhwr_noopt(char *str)
1575 {
1576 rdhwr_noopt = 1;
1577 return 1;
1578 }
1579
1580 __setup("rdhwr_noopt", set_rdhwr_noopt);
1581
1582 void __init trap_init(void)
1583 {
1584 extern char except_vec3_generic, except_vec3_r4000;
1585 extern char except_vec4;
1586 unsigned long i;
1587 int rollback;
1588
1589 check_wait();
1590 rollback = (cpu_wait == r4k_wait);
1591
1592 #if defined(CONFIG_KGDB)
1593 if (kgdb_early_setup)
1594 return; /* Already done */
1595 #endif
1596
1597 if (cpu_has_veic || cpu_has_vint) {
1598 unsigned long size = 0x200 + VECTORSPACING*64;
1599 ebase = (unsigned long)
1600 __alloc_bootmem(size, 1 << fls(size), 0);
1601 } else {
1602 ebase = CKSEG0;
1603 if (cpu_has_mips_r2)
1604 ebase += (read_c0_ebase() & 0x3ffff000);
1605 }
1606
1607 per_cpu_trap_init();
1608
1609 /*
1610 * Copy the generic exception handlers to their final destination.
1611 * This will be overriden later as suitable for a particular
1612 * configuration.
1613 */
1614 set_handler(0x180, &except_vec3_generic, 0x80);
1615
1616 /*
1617 * Setup default vectors
1618 */
1619 for (i = 0; i <= 31; i++)
1620 set_except_vector(i, handle_reserved);
1621
1622 /*
1623 * Copy the EJTAG debug exception vector handler code to it's final
1624 * destination.
1625 */
1626 if (cpu_has_ejtag && board_ejtag_handler_setup)
1627 board_ejtag_handler_setup();
1628
1629 /*
1630 * Only some CPUs have the watch exceptions.
1631 */
1632 if (cpu_has_watch)
1633 set_except_vector(23, handle_watch);
1634
1635 /*
1636 * Initialise interrupt handlers
1637 */
1638 if (cpu_has_veic || cpu_has_vint) {
1639 int nvec = cpu_has_veic ? 64 : 8;
1640 for (i = 0; i < nvec; i++)
1641 set_vi_handler(i, NULL);
1642 }
1643 else if (cpu_has_divec)
1644 set_handler(0x200, &except_vec4, 0x8);
1645
1646 /*
1647 * Some CPUs can enable/disable for cache parity detection, but does
1648 * it different ways.
1649 */
1650 parity_protection_init();
1651
1652 /*
1653 * The Data Bus Errors / Instruction Bus Errors are signaled
1654 * by external hardware. Therefore these two exceptions
1655 * may have board specific handlers.
1656 */
1657 if (board_be_init)
1658 board_be_init();
1659
1660 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1661 set_except_vector(1, handle_tlbm);
1662 set_except_vector(2, handle_tlbl);
1663 set_except_vector(3, handle_tlbs);
1664
1665 set_except_vector(4, handle_adel);
1666 set_except_vector(5, handle_ades);
1667
1668 set_except_vector(6, handle_ibe);
1669 set_except_vector(7, handle_dbe);
1670
1671 set_except_vector(8, handle_sys);
1672 set_except_vector(9, handle_bp);
1673 set_except_vector(10, rdhwr_noopt ? handle_ri :
1674 (cpu_has_vtag_icache ?
1675 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1676 set_except_vector(11, handle_cpu);
1677 set_except_vector(12, handle_ov);
1678 set_except_vector(13, handle_tr);
1679
1680 if (current_cpu_type() == CPU_R6000 ||
1681 current_cpu_type() == CPU_R6000A) {
1682 /*
1683 * The R6000 is the only R-series CPU that features a machine
1684 * check exception (similar to the R4000 cache error) and
1685 * unaligned ldc1/sdc1 exception. The handlers have not been
1686 * written yet. Well, anyway there is no R6000 machine on the
1687 * current list of targets for Linux/MIPS.
1688 * (Duh, crap, there is someone with a triple R6k machine)
1689 */
1690 //set_except_vector(14, handle_mc);
1691 //set_except_vector(15, handle_ndc);
1692 }
1693
1694
1695 if (board_nmi_handler_setup)
1696 board_nmi_handler_setup();
1697
1698 if (cpu_has_fpu && !cpu_has_nofpuex)
1699 set_except_vector(15, handle_fpe);
1700
1701 set_except_vector(22, handle_mdmx);
1702
1703 if (cpu_has_mcheck)
1704 set_except_vector(24, handle_mcheck);
1705
1706 if (cpu_has_mipsmt)
1707 set_except_vector(25, handle_mt);
1708
1709 set_except_vector(26, handle_dsp);
1710
1711 if (cpu_has_vce)
1712 /* Special exception: R4[04]00 uses also the divec space. */
1713 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1714 else if (cpu_has_4kex)
1715 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1716 else
1717 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1718
1719 local_flush_icache_range(ebase, ebase + 0x400);
1720 flush_tlb_handlers();
1721
1722 sort_extable(__start___dbe_table, __stop___dbe_table);
1723
1724 register_cu2_notifier(&default_cu2_notifier);
1725 }
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