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MIPS: SB1250: Include correct header and fix a warning
[linux-2.6/linux-mips.git] / arch / x86 / kernel / cpu / intel_cacheinfo.c
blobb3eeb66c0a51af93e3d7015aa737ce3af66ed1e3
1 /*
2 * Routines to indentify caches on Intel CPU.
3 *
4 * Changes:
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
8 */
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17
18 #include <asm/processor.h>
19 #include <linux/smp.h>
20 #include <asm/k8.h>
21 #include <asm/smp.h>
22
23 #define LVL_1_INST 1
24 #define LVL_1_DATA 2
25 #define LVL_2 3
26 #define LVL_3 4
27 #define LVL_TRACE 5
28
29 struct _cache_table {
30 unsigned char descriptor;
31 char cache_type;
32 short size;
33 };
34
35 #define MB(x) ((x) * 1024)
36
37 /* All the cache descriptor types we care about (no TLB or
38 trace cache entries) */
39
40 static const struct _cache_table __cpuinitconst cache_table[] =
41 {
42 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
43 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
44 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
45 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
46 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
48 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
49 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
50 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
51 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
52 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
53 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
54 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
55 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
56 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
57 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
58 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
59 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
60 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
62 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
63 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
64 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
65 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
66 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
67 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
68 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
69 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
70 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
71 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
72 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
73 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
74 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
75 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
76 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
78 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
79 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
80 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
81 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
82 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
83 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
84 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
85 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
86 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
87 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
88 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
89 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
90 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
91 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
92 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
93 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
94 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
95 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
96 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
97 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
98 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
99 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
100 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
101 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
102 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
103 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
104 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
105 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
106 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
107 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
108 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
109 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
110 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
111 { 0x00, 0, 0}
112 };
113
114
115 enum _cache_type {
116 CACHE_TYPE_NULL = 0,
117 CACHE_TYPE_DATA = 1,
118 CACHE_TYPE_INST = 2,
119 CACHE_TYPE_UNIFIED = 3
120 };
121
122 union _cpuid4_leaf_eax {
123 struct {
124 enum _cache_type type:5;
125 unsigned int level:3;
126 unsigned int is_self_initializing:1;
127 unsigned int is_fully_associative:1;
128 unsigned int reserved:4;
129 unsigned int num_threads_sharing:12;
130 unsigned int num_cores_on_die:6;
131 } split;
132 u32 full;
133 };
134
135 union _cpuid4_leaf_ebx {
136 struct {
137 unsigned int coherency_line_size:12;
138 unsigned int physical_line_partition:10;
139 unsigned int ways_of_associativity:10;
140 } split;
141 u32 full;
142 };
143
144 union _cpuid4_leaf_ecx {
145 struct {
146 unsigned int number_of_sets:32;
147 } split;
148 u32 full;
149 };
150
151 struct _cpuid4_info {
152 union _cpuid4_leaf_eax eax;
153 union _cpuid4_leaf_ebx ebx;
154 union _cpuid4_leaf_ecx ecx;
155 unsigned long size;
156 bool can_disable;
157 unsigned int l3_indices;
158 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
159 };
160
161 /* subset of above _cpuid4_info w/o shared_cpu_map */
162 struct _cpuid4_info_regs {
163 union _cpuid4_leaf_eax eax;
164 union _cpuid4_leaf_ebx ebx;
165 union _cpuid4_leaf_ecx ecx;
166 unsigned long size;
167 bool can_disable;
168 unsigned int l3_indices;
169 };
170
171 unsigned short num_cache_leaves;
172
173 /* AMD doesn't have CPUID4. Emulate it here to report the same
174 information to the user. This makes some assumptions about the machine:
175 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
176
177 In theory the TLBs could be reported as fake type (they are in "dummy").
178 Maybe later */
179 union l1_cache {
180 struct {
181 unsigned line_size:8;
182 unsigned lines_per_tag:8;
183 unsigned assoc:8;
184 unsigned size_in_kb:8;
185 };
186 unsigned val;
187 };
188
189 union l2_cache {
190 struct {
191 unsigned line_size:8;
192 unsigned lines_per_tag:4;
193 unsigned assoc:4;
194 unsigned size_in_kb:16;
195 };
196 unsigned val;
197 };
198
199 union l3_cache {
200 struct {
201 unsigned line_size:8;
202 unsigned lines_per_tag:4;
203 unsigned assoc:4;
204 unsigned res:2;
205 unsigned size_encoded:14;
206 };
207 unsigned val;
208 };
209
210 static const unsigned short __cpuinitconst assocs[] = {
211 [1] = 1,
212 [2] = 2,
213 [4] = 4,
214 [6] = 8,
215 [8] = 16,
216 [0xa] = 32,
217 [0xb] = 48,
218 [0xc] = 64,
219 [0xd] = 96,
220 [0xe] = 128,
221 [0xf] = 0xffff /* fully associative - no way to show this currently */
222 };
223
224 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
225 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
226
227 static void __cpuinit
228 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
229 union _cpuid4_leaf_ebx *ebx,
230 union _cpuid4_leaf_ecx *ecx)
231 {
232 unsigned dummy;
233 unsigned line_size, lines_per_tag, assoc, size_in_kb;
234 union l1_cache l1i, l1d;
235 union l2_cache l2;
236 union l3_cache l3;
237 union l1_cache *l1 = &l1d;
238
239 eax->full = 0;
240 ebx->full = 0;
241 ecx->full = 0;
242
243 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
244 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
245
246 switch (leaf) {
247 case 1:
248 l1 = &l1i;
249 case 0:
250 if (!l1->val)
251 return;
252 assoc = assocs[l1->assoc];
253 line_size = l1->line_size;
254 lines_per_tag = l1->lines_per_tag;
255 size_in_kb = l1->size_in_kb;
256 break;
257 case 2:
258 if (!l2.val)
259 return;
260 assoc = assocs[l2.assoc];
261 line_size = l2.line_size;
262 lines_per_tag = l2.lines_per_tag;
263 /* cpu_data has errata corrections for K7 applied */
264 size_in_kb = current_cpu_data.x86_cache_size;
265 break;
266 case 3:
267 if (!l3.val)
268 return;
269 assoc = assocs[l3.assoc];
270 line_size = l3.line_size;
271 lines_per_tag = l3.lines_per_tag;
272 size_in_kb = l3.size_encoded * 512;
273 if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
274 size_in_kb = size_in_kb >> 1;
275 assoc = assoc >> 1;
276 }
277 break;
278 default:
279 return;
280 }
281
282 eax->split.is_self_initializing = 1;
283 eax->split.type = types[leaf];
284 eax->split.level = levels[leaf];
285 eax->split.num_threads_sharing = 0;
286 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
287
288
289 if (assoc == 0xffff)
290 eax->split.is_fully_associative = 1;
291 ebx->split.coherency_line_size = line_size - 1;
292 ebx->split.ways_of_associativity = assoc - 1;
293 ebx->split.physical_line_partition = lines_per_tag - 1;
294 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
295 (ebx->split.ways_of_associativity + 1) - 1;
296 }
297
298 struct _cache_attr {
299 struct attribute attr;
300 ssize_t (*show)(struct _cpuid4_info *, char *);
301 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
302 };
303
304 #ifdef CONFIG_CPU_SUP_AMD
305 static unsigned int __cpuinit amd_calc_l3_indices(void)
306 {
307 /*
308 * We're called over smp_call_function_single() and therefore
309 * are on the correct cpu.
310 */
311 int cpu = smp_processor_id();
312 int node = cpu_to_node(cpu);
313 struct pci_dev *dev = node_to_k8_nb_misc(node);
314 unsigned int sc0, sc1, sc2, sc3;
315 u32 val = 0;
316
317 pci_read_config_dword(dev, 0x1C4, &val);
318
319 /* calculate subcache sizes */
320 sc0 = !(val & BIT(0));
321 sc1 = !(val & BIT(4));
322 sc2 = !(val & BIT(8)) + !(val & BIT(9));
323 sc3 = !(val & BIT(12)) + !(val & BIT(13));
324
325 return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
326 }
327
328 static void __cpuinit
329 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
330 {
331 if (index < 3)
332 return;
333
334 if (boot_cpu_data.x86 == 0x11)
335 return;
336
337 /* see errata #382 and #388 */
338 if ((boot_cpu_data.x86 == 0x10) &&
339 ((boot_cpu_data.x86_model < 0x8) ||
340 (boot_cpu_data.x86_mask < 0x1)))
341 return;
342
343 this_leaf->can_disable = true;
344 this_leaf->l3_indices = amd_calc_l3_indices();
345 }
346
347 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
348 unsigned int index)
349 {
350 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
351 int node = amd_get_nb_id(cpu);
352 struct pci_dev *dev = node_to_k8_nb_misc(node);
353 unsigned int reg = 0;
354
355 if (!this_leaf->can_disable)
356 return -EINVAL;
357
358 if (!dev)
359 return -EINVAL;
360
361 pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
362 return sprintf(buf, "0x%08x\n", reg);
363 }
364
365 #define SHOW_CACHE_DISABLE(index) \
366 static ssize_t \
367 show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
368 { \
369 return show_cache_disable(this_leaf, buf, index); \
370 }
371 SHOW_CACHE_DISABLE(0)
372 SHOW_CACHE_DISABLE(1)
373
374 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
375 const char *buf, size_t count, unsigned int index)
376 {
377 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
378 int node = amd_get_nb_id(cpu);
379 struct pci_dev *dev = node_to_k8_nb_misc(node);
380 unsigned long val = 0;
381
382 #define SUBCACHE_MASK (3UL << 20)
383 #define SUBCACHE_INDEX 0xfff
384
385 if (!this_leaf->can_disable)
386 return -EINVAL;
387
388 if (!capable(CAP_SYS_ADMIN))
389 return -EPERM;
390
391 if (!dev)
392 return -EINVAL;
393
394 if (strict_strtoul(buf, 10, &val) < 0)
395 return -EINVAL;
396
397 /* do not allow writes outside of allowed bits */
398 if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
399 ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
400 return -EINVAL;
401
402 val |= BIT(30);
403 pci_write_config_dword(dev, 0x1BC + index * 4, val);
404 /*
405 * We need to WBINVD on a core on the node containing the L3 cache which
406 * indices we disable therefore a simple wbinvd() is not sufficient.
407 */
408 wbinvd_on_cpu(cpu);
409 pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
410 return count;
411 }
412
413 #define STORE_CACHE_DISABLE(index) \
414 static ssize_t \
415 store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
416 const char *buf, size_t count) \
417 { \
418 return store_cache_disable(this_leaf, buf, count, index); \
419 }
420 STORE_CACHE_DISABLE(0)
421 STORE_CACHE_DISABLE(1)
422
423 static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
424 show_cache_disable_0, store_cache_disable_0);
425 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
426 show_cache_disable_1, store_cache_disable_1);
427
428 #else /* CONFIG_CPU_SUP_AMD */
429 static void __cpuinit
430 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
431 {
432 };
433 #endif /* CONFIG_CPU_SUP_AMD */
434
435 static int
436 __cpuinit cpuid4_cache_lookup_regs(int index,
437 struct _cpuid4_info_regs *this_leaf)
438 {
439 union _cpuid4_leaf_eax eax;
440 union _cpuid4_leaf_ebx ebx;
441 union _cpuid4_leaf_ecx ecx;
442 unsigned edx;
443
444 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
445 amd_cpuid4(index, &eax, &ebx, &ecx);
446 if (boot_cpu_data.x86 >= 0x10)
447 amd_check_l3_disable(index, this_leaf);
448 } else {
449 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
450 }
451
452 if (eax.split.type == CACHE_TYPE_NULL)
453 return -EIO; /* better error ? */
454
455 this_leaf->eax = eax;
456 this_leaf->ebx = ebx;
457 this_leaf->ecx = ecx;
458 this_leaf->size = (ecx.split.number_of_sets + 1) *
459 (ebx.split.coherency_line_size + 1) *
460 (ebx.split.physical_line_partition + 1) *
461 (ebx.split.ways_of_associativity + 1);
462 return 0;
463 }
464
465 static int __cpuinit find_num_cache_leaves(void)
466 {
467 unsigned int eax, ebx, ecx, edx;
468 union _cpuid4_leaf_eax cache_eax;
469 int i = -1;
470
471 do {
472 ++i;
473 /* Do cpuid(4) loop to find out num_cache_leaves */
474 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
475 cache_eax.full = eax;
476 } while (cache_eax.split.type != CACHE_TYPE_NULL);
477 return i;
478 }
479
480 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
481 {
482 /* Cache sizes */
483 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
484 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
485 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
486 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
487 #ifdef CONFIG_X86_HT
488 unsigned int cpu = c->cpu_index;
489 #endif
490
491 if (c->cpuid_level > 3) {
492 static int is_initialized;
493
494 if (is_initialized == 0) {
495 /* Init num_cache_leaves from boot CPU */
496 num_cache_leaves = find_num_cache_leaves();
497 is_initialized++;
498 }
499
500 /*
501 * Whenever possible use cpuid(4), deterministic cache
502 * parameters cpuid leaf to find the cache details
503 */
504 for (i = 0; i < num_cache_leaves; i++) {
505 struct _cpuid4_info_regs this_leaf;
506 int retval;
507
508 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
509 if (retval >= 0) {
510 switch (this_leaf.eax.split.level) {
511 case 1:
512 if (this_leaf.eax.split.type ==
513 CACHE_TYPE_DATA)
514 new_l1d = this_leaf.size/1024;
515 else if (this_leaf.eax.split.type ==
516 CACHE_TYPE_INST)
517 new_l1i = this_leaf.size/1024;
518 break;
519 case 2:
520 new_l2 = this_leaf.size/1024;
521 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
522 index_msb = get_count_order(num_threads_sharing);
523 l2_id = c->apicid >> index_msb;
524 break;
525 case 3:
526 new_l3 = this_leaf.size/1024;
527 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
528 index_msb = get_count_order(
529 num_threads_sharing);
530 l3_id = c->apicid >> index_msb;
531 break;
532 default:
533 break;
534 }
535 }
536 }
537 }
538 /*
539 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
540 * trace cache
541 */
542 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
543 /* supports eax=2 call */
544 int j, n;
545 unsigned int regs[4];
546 unsigned char *dp = (unsigned char *)regs;
547 int only_trace = 0;
548
549 if (num_cache_leaves != 0 && c->x86 == 15)
550 only_trace = 1;
551
552 /* Number of times to iterate */
553 n = cpuid_eax(2) & 0xFF;
554
555 for (i = 0 ; i < n ; i++) {
556 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
557
558 /* If bit 31 is set, this is an unknown format */
559 for (j = 0 ; j < 3 ; j++)
560 if (regs[j] & (1 << 31))
561 regs[j] = 0;
562
563 /* Byte 0 is level count, not a descriptor */
564 for (j = 1 ; j < 16 ; j++) {
565 unsigned char des = dp[j];
566 unsigned char k = 0;
567
568 /* look up this descriptor in the table */
569 while (cache_table[k].descriptor != 0) {
570 if (cache_table[k].descriptor == des) {
571 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
572 break;
573 switch (cache_table[k].cache_type) {
574 case LVL_1_INST:
575 l1i += cache_table[k].size;
576 break;
577 case LVL_1_DATA:
578 l1d += cache_table[k].size;
579 break;
580 case LVL_2:
581 l2 += cache_table[k].size;
582 break;
583 case LVL_3:
584 l3 += cache_table[k].size;
585 break;
586 case LVL_TRACE:
587 trace += cache_table[k].size;
588 break;
589 }
590
591 break;
592 }
593
594 k++;
595 }
596 }
597 }
598 }
599
600 if (new_l1d)
601 l1d = new_l1d;
602
603 if (new_l1i)
604 l1i = new_l1i;
605
606 if (new_l2) {
607 l2 = new_l2;
608 #ifdef CONFIG_X86_HT
609 per_cpu(cpu_llc_id, cpu) = l2_id;
610 #endif
611 }
612
613 if (new_l3) {
614 l3 = new_l3;
615 #ifdef CONFIG_X86_HT
616 per_cpu(cpu_llc_id, cpu) = l3_id;
617 #endif
618 }
619
620 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
621
622 return l2;
623 }
624
625 #ifdef CONFIG_SYSFS
626
627 /* pointer to _cpuid4_info array (for each cache leaf) */
628 static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
629 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
630
631 #ifdef CONFIG_SMP
632 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
633 {
634 struct _cpuid4_info *this_leaf, *sibling_leaf;
635 unsigned long num_threads_sharing;
636 int index_msb, i, sibling;
637 struct cpuinfo_x86 *c = &cpu_data(cpu);
638
639 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
640 for_each_cpu(i, c->llc_shared_map) {
641 if (!per_cpu(ici_cpuid4_info, i))
642 continue;
643 this_leaf = CPUID4_INFO_IDX(i, index);
644 for_each_cpu(sibling, c->llc_shared_map) {
645 if (!cpu_online(sibling))
646 continue;
647 set_bit(sibling, this_leaf->shared_cpu_map);
648 }
649 }
650 return;
651 }
652 this_leaf = CPUID4_INFO_IDX(cpu, index);
653 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
654
655 if (num_threads_sharing == 1)
656 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
657 else {
658 index_msb = get_count_order(num_threads_sharing);
659
660 for_each_online_cpu(i) {
661 if (cpu_data(i).apicid >> index_msb ==
662 c->apicid >> index_msb) {
663 cpumask_set_cpu(i,
664 to_cpumask(this_leaf->shared_cpu_map));
665 if (i != cpu && per_cpu(ici_cpuid4_info, i)) {
666 sibling_leaf =
667 CPUID4_INFO_IDX(i, index);
668 cpumask_set_cpu(cpu, to_cpumask(
669 sibling_leaf->shared_cpu_map));
670 }
671 }
672 }
673 }
674 }
675 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
676 {
677 struct _cpuid4_info *this_leaf, *sibling_leaf;
678 int sibling;
679
680 this_leaf = CPUID4_INFO_IDX(cpu, index);
681 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
682 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
683 cpumask_clear_cpu(cpu,
684 to_cpumask(sibling_leaf->shared_cpu_map));
685 }
686 }
687 #else
688 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
689 {
690 }
691
692 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
693 {
694 }
695 #endif
696
697 static void __cpuinit free_cache_attributes(unsigned int cpu)
698 {
699 int i;
700
701 for (i = 0; i < num_cache_leaves; i++)
702 cache_remove_shared_cpu_map(cpu, i);
703
704 kfree(per_cpu(ici_cpuid4_info, cpu));
705 per_cpu(ici_cpuid4_info, cpu) = NULL;
706 }
707
708 static int
709 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
710 {
711 struct _cpuid4_info_regs *leaf_regs =
712 (struct _cpuid4_info_regs *)this_leaf;
713
714 return cpuid4_cache_lookup_regs(index, leaf_regs);
715 }
716
717 static void __cpuinit get_cpu_leaves(void *_retval)
718 {
719 int j, *retval = _retval, cpu = smp_processor_id();
720
721 /* Do cpuid and store the results */
722 for (j = 0; j < num_cache_leaves; j++) {
723 struct _cpuid4_info *this_leaf;
724 this_leaf = CPUID4_INFO_IDX(cpu, j);
725 *retval = cpuid4_cache_lookup(j, this_leaf);
726 if (unlikely(*retval < 0)) {
727 int i;
728
729 for (i = 0; i < j; i++)
730 cache_remove_shared_cpu_map(cpu, i);
731 break;
732 }
733 cache_shared_cpu_map_setup(cpu, j);
734 }
735 }
736
737 static int __cpuinit detect_cache_attributes(unsigned int cpu)
738 {
739 int retval;
740
741 if (num_cache_leaves == 0)
742 return -ENOENT;
743
744 per_cpu(ici_cpuid4_info, cpu) = kzalloc(
745 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
746 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
747 return -ENOMEM;
748
749 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
750 if (retval) {
751 kfree(per_cpu(ici_cpuid4_info, cpu));
752 per_cpu(ici_cpuid4_info, cpu) = NULL;
753 }
754
755 return retval;
756 }
757
758 #include <linux/kobject.h>
759 #include <linux/sysfs.h>
760
761 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
762
763 /* pointer to kobject for cpuX/cache */
764 static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
765
766 struct _index_kobject {
767 struct kobject kobj;
768 unsigned int cpu;
769 unsigned short index;
770 };
771
772 /* pointer to array of kobjects for cpuX/cache/indexY */
773 static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
774 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
775
776 #define show_one_plus(file_name, object, val) \
777 static ssize_t show_##file_name \
778 (struct _cpuid4_info *this_leaf, char *buf) \
779 { \
780 return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
781 }
782
783 show_one_plus(level, eax.split.level, 0);
784 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
785 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
786 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
787 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
788
789 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
790 {
791 return sprintf(buf, "%luK\n", this_leaf->size / 1024);
792 }
793
794 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
795 int type, char *buf)
796 {
797 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
798 int n = 0;
799
800 if (len > 1) {
801 const struct cpumask *mask;
802
803 mask = to_cpumask(this_leaf->shared_cpu_map);
804 n = type ?
805 cpulist_scnprintf(buf, len-2, mask) :
806 cpumask_scnprintf(buf, len-2, mask);
807 buf[n++] = '\n';
808 buf[n] = '\0';
809 }
810 return n;
811 }
812
813 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
814 {
815 return show_shared_cpu_map_func(leaf, 0, buf);
816 }
817
818 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
819 {
820 return show_shared_cpu_map_func(leaf, 1, buf);
821 }
822
823 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
824 {
825 switch (this_leaf->eax.split.type) {
826 case CACHE_TYPE_DATA:
827 return sprintf(buf, "Data\n");
828 case CACHE_TYPE_INST:
829 return sprintf(buf, "Instruction\n");
830 case CACHE_TYPE_UNIFIED:
831 return sprintf(buf, "Unified\n");
832 default:
833 return sprintf(buf, "Unknown\n");
834 }
835 }
836
837 #define to_object(k) container_of(k, struct _index_kobject, kobj)
838 #define to_attr(a) container_of(a, struct _cache_attr, attr)
839
840 #define define_one_ro(_name) \
841 static struct _cache_attr _name = \
842 __ATTR(_name, 0444, show_##_name, NULL)
843
844 define_one_ro(level);
845 define_one_ro(type);
846 define_one_ro(coherency_line_size);
847 define_one_ro(physical_line_partition);
848 define_one_ro(ways_of_associativity);
849 define_one_ro(number_of_sets);
850 define_one_ro(size);
851 define_one_ro(shared_cpu_map);
852 define_one_ro(shared_cpu_list);
853
854 #define DEFAULT_SYSFS_CACHE_ATTRS \
855 &type.attr, \
856 &level.attr, \
857 &coherency_line_size.attr, \
858 &physical_line_partition.attr, \
859 &ways_of_associativity.attr, \
860 &number_of_sets.attr, \
861 &size.attr, \
862 &shared_cpu_map.attr, \
863 &shared_cpu_list.attr
864
865 static struct attribute *default_attrs[] = {
866 DEFAULT_SYSFS_CACHE_ATTRS,
867 NULL
868 };
869
870 static struct attribute *default_l3_attrs[] = {
871 DEFAULT_SYSFS_CACHE_ATTRS,
872 #ifdef CONFIG_CPU_SUP_AMD
873 &cache_disable_0.attr,
874 &cache_disable_1.attr,
875 #endif
876 NULL
877 };
878
879 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
880 {
881 struct _cache_attr *fattr = to_attr(attr);
882 struct _index_kobject *this_leaf = to_object(kobj);
883 ssize_t ret;
884
885 ret = fattr->show ?
886 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
887 buf) :
888 0;
889 return ret;
890 }
891
892 static ssize_t store(struct kobject *kobj, struct attribute *attr,
893 const char *buf, size_t count)
894 {
895 struct _cache_attr *fattr = to_attr(attr);
896 struct _index_kobject *this_leaf = to_object(kobj);
897 ssize_t ret;
898
899 ret = fattr->store ?
900 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
901 buf, count) :
902 0;
903 return ret;
904 }
905
906 static const struct sysfs_ops sysfs_ops = {
907 .show = show,
908 .store = store,
909 };
910
911 static struct kobj_type ktype_cache = {
912 .sysfs_ops = &sysfs_ops,
913 .default_attrs = default_attrs,
914 };
915
916 static struct kobj_type ktype_percpu_entry = {
917 .sysfs_ops = &sysfs_ops,
918 };
919
920 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
921 {
922 kfree(per_cpu(ici_cache_kobject, cpu));
923 kfree(per_cpu(ici_index_kobject, cpu));
924 per_cpu(ici_cache_kobject, cpu) = NULL;
925 per_cpu(ici_index_kobject, cpu) = NULL;
926 free_cache_attributes(cpu);
927 }
928
929 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
930 {
931 int err;
932
933 if (num_cache_leaves == 0)
934 return -ENOENT;
935
936 err = detect_cache_attributes(cpu);
937 if (err)
938 return err;
939
940 /* Allocate all required memory */
941 per_cpu(ici_cache_kobject, cpu) =
942 kzalloc(sizeof(struct kobject), GFP_KERNEL);
943 if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
944 goto err_out;
945
946 per_cpu(ici_index_kobject, cpu) = kzalloc(
947 sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
948 if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
949 goto err_out;
950
951 return 0;
952
953 err_out:
954 cpuid4_cache_sysfs_exit(cpu);
955 return -ENOMEM;
956 }
957
958 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
959
960 /* Add/Remove cache interface for CPU device */
961 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
962 {
963 unsigned int cpu = sys_dev->id;
964 unsigned long i, j;
965 struct _index_kobject *this_object;
966 struct _cpuid4_info *this_leaf;
967 int retval;
968
969 retval = cpuid4_cache_sysfs_init(cpu);
970 if (unlikely(retval < 0))
971 return retval;
972
973 retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
974 &ktype_percpu_entry,
975 &sys_dev->kobj, "%s", "cache");
976 if (retval < 0) {
977 cpuid4_cache_sysfs_exit(cpu);
978 return retval;
979 }
980
981 for (i = 0; i < num_cache_leaves; i++) {
982 this_object = INDEX_KOBJECT_PTR(cpu, i);
983 this_object->cpu = cpu;
984 this_object->index = i;
985
986 this_leaf = CPUID4_INFO_IDX(cpu, i);
987
988 if (this_leaf->can_disable)
989 ktype_cache.default_attrs = default_l3_attrs;
990 else
991 ktype_cache.default_attrs = default_attrs;
992
993 retval = kobject_init_and_add(&(this_object->kobj),
994 &ktype_cache,
995 per_cpu(ici_cache_kobject, cpu),
996 "index%1lu", i);
997 if (unlikely(retval)) {
998 for (j = 0; j < i; j++)
999 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
1000 kobject_put(per_cpu(ici_cache_kobject, cpu));
1001 cpuid4_cache_sysfs_exit(cpu);
1002 return retval;
1003 }
1004 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
1005 }
1006 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
1007
1008 kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
1009 return 0;
1010 }
1011
1012 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
1013 {
1014 unsigned int cpu = sys_dev->id;
1015 unsigned long i;
1016
1017 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
1018 return;
1019 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
1020 return;
1021 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
1022
1023 for (i = 0; i < num_cache_leaves; i++)
1024 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
1025 kobject_put(per_cpu(ici_cache_kobject, cpu));
1026 cpuid4_cache_sysfs_exit(cpu);
1027 }
1028
1029 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
1030 unsigned long action, void *hcpu)
1031 {
1032 unsigned int cpu = (unsigned long)hcpu;
1033 struct sys_device *sys_dev;
1034
1035 sys_dev = get_cpu_sysdev(cpu);
1036 switch (action) {
1037 case CPU_ONLINE:
1038 case CPU_ONLINE_FROZEN:
1039 cache_add_dev(sys_dev);
1040 break;
1041 case CPU_DEAD:
1042 case CPU_DEAD_FROZEN:
1043 cache_remove_dev(sys_dev);
1044 break;
1045 }
1046 return NOTIFY_OK;
1047 }
1048
1049 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
1050 .notifier_call = cacheinfo_cpu_callback,
1051 };
1052
1053 static int __cpuinit cache_sysfs_init(void)
1054 {
1055 int i;
1056
1057 if (num_cache_leaves == 0)
1058 return 0;
1059
1060 for_each_online_cpu(i) {
1061 int err;
1062 struct sys_device *sys_dev = get_cpu_sysdev(i);
1063
1064 err = cache_add_dev(sys_dev);
1065 if (err)
1066 return err;
1067 }
1068 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
1069 return 0;
1070 }
1071
1072 device_initcall(cache_sysfs_init);
1073
1074 #endif
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