arch/arm/mach-imx/clock-imx25.c

   1 /*
   2  * Copyright (C) 2009 by Sascha Hauer, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  16  * MA 02110-1301, USA.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/clock.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/mx25.h>
  30
  31 #define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
  32
  33 #define CCM_MPCTL       0x00
  34 #define CCM_UPCTL       0x04
  35 #define CCM_CCTL        0x08
  36 #define CCM_CGCR0       0x0C
  37 #define CCM_CGCR1       0x10
  38 #define CCM_CGCR2       0x14
  39 #define CCM_PCDR0       0x18
  40 #define CCM_PCDR1       0x1C
  41 #define CCM_PCDR2       0x20
  42 #define CCM_PCDR3       0x24
  43 #define CCM_RCSR        0x28
  44 #define CCM_CRDR        0x2C
  45 #define CCM_DCVR0       0x30
  46 #define CCM_DCVR1       0x34
  47 #define CCM_DCVR2       0x38
  48 #define CCM_DCVR3       0x3c
  49 #define CCM_LTR0        0x40
  50 #define CCM_LTR1        0x44
  51 #define CCM_LTR2        0x48
  52 #define CCM_LTR3        0x4c
  53
  54 static unsigned long get_rate_mpll(void)
  55 {
  56         ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
  57
  58         return mxc_decode_pll(mpctl, 24000000);
  59 }
  60
  61 static unsigned long get_rate_upll(void)
  62 {
  63         ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
  64
  65         return mxc_decode_pll(mpctl, 24000000);
  66 }
  67
  68 unsigned long get_rate_arm(struct clk *clk)
  69 {
  70         unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
  71         unsigned long rate = get_rate_mpll();
  72
  73         if (cctl & (1 << 14))
  74                 rate = (rate * 3) >> 2;
  75
  76         return rate / ((cctl >> 30) + 1);
  77 }
  78
  79 static unsigned long get_rate_ahb(struct clk *clk)
  80 {
  81         unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
  82
  83         return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
  84 }
  85
  86 static unsigned long get_rate_ipg(struct clk *clk)
  87 {
  88         return get_rate_ahb(NULL) >> 1;
  89 }
  90
  91 static unsigned long get_rate_per(int per)
  92 {
  93         unsigned long ofs = (per & 0x3) * 8;
  94         unsigned long reg = per & ~0x3;
  95         unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
  96         unsigned long fref;
  97
  98         if (readl(CRM_BASE + 0x64) & (1 << per))
  99                 fref = get_rate_upll();
 100         else
 101                 fref = get_rate_ahb(NULL);
 102
 103         return fref / (val + 1);
 104 }
 105
 106 static unsigned long get_rate_uart(struct clk *clk)
 107 {
 108         return get_rate_per(15);
 109 }
 110
 111 static unsigned long get_rate_ssi2(struct clk *clk)
 112 {
 113         return get_rate_per(14);
 114 }
 115
 116 static unsigned long get_rate_ssi1(struct clk *clk)
 117 {
 118         return get_rate_per(13);
 119 }
 120
 121 static unsigned long get_rate_i2c(struct clk *clk)
 122 {
 123         return get_rate_per(6);
 124 }
 125
 126 static unsigned long get_rate_nfc(struct clk *clk)
 127 {
 128         return get_rate_per(8);
 129 }
 130
 131 static unsigned long get_rate_gpt(struct clk *clk)
 132 {
 133         return get_rate_per(5);
 134 }
 135
 136 static unsigned long get_rate_lcdc(struct clk *clk)
 137 {
 138         return get_rate_per(7);
 139 }
 140
 141 static unsigned long get_rate_esdhc1(struct clk *clk)
 142 {
 143         return get_rate_per(3);
 144 }
 145
 146 static unsigned long get_rate_esdhc2(struct clk *clk)
 147 {
 148         return get_rate_per(4);
 149 }
 150
 151 static unsigned long get_rate_csi(struct clk *clk)
 152 {
 153         return get_rate_per(0);
 154 }
 155
 156 static unsigned long get_rate_otg(struct clk *clk)
 157 {
 158         unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
 159         unsigned long rate = get_rate_upll();
 160
 161         return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
 162 }
 163
 164 static int clk_cgcr_enable(struct clk *clk)
 165 {
 166         u32 reg;
 167
 168         reg = __raw_readl(clk->enable_reg);
 169         reg |= 1 << clk->enable_shift;
 170         __raw_writel(reg, clk->enable_reg);
 171
 172         return 0;
 173 }
 174
 175 static void clk_cgcr_disable(struct clk *clk)
 176 {
 177         u32 reg;
 178
 179         reg = __raw_readl(clk->enable_reg);
 180         reg &= ~(1 << clk->enable_shift);
 181         __raw_writel(reg, clk->enable_reg);
 182 }
 183
 184 #define DEFINE_CLOCK(name, i, er, es, gr, sr, s)        \
 185         static struct clk name = {                      \
 186                 .id             = i,                    \
 187                 .enable_reg     = CRM_BASE + er,        \
 188                 .enable_shift   = es,                   \
 189                 .get_rate       = gr,                   \
 190                 .set_rate       = sr,                   \
 191                 .enable         = clk_cgcr_enable,      \
 192                 .disable        = clk_cgcr_disable,     \
 193                 .secondary      = s,                    \
 194         }
 195
 196 /*
 197  * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
 198  * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
 199  * taken from the Freescale released BSP.
 200  *
 201  * bit  reg     offset  clock
 202  *
 203  * 0    CGCR1   0       AUDMUX
 204  * 12   CGCR1   12      ESAI
 205  * 16   CGCR1   16      GPIO1
 206  * 17   CGCR1   17      GPIO2
 207  * 18   CGCR1   18      GPIO3
 208  * 23   CGCR1   23      I2C1
 209  * 24   CGCR1   24      I2C2
 210  * 25   CGCR1   25      I2C3
 211  * 27   CGCR1   27      IOMUXC
 212  * 28   CGCR1   28      KPP
 213  * 30   CGCR1   30      OWIRE
 214  * 36   CGCR2   4       RTIC
 215  * 51   CGCR2   19      WDOG
 216  */
 217
 218 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 219 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
 220 DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
 221 DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 222 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 223 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 224 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
 225 DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,  NULL, NULL);
 226 DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,  NULL,
 227                 &esdhc1_ahb_clk);
 228 DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,  NULL, NULL);
 229 DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,  NULL,
 230                 &esdhc2_ahb_clk);
 231 DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,       NULL, NULL);
 232 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 233 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 234 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
 235 DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
 236 DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
 237 DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
 238 DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
 239 DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
 240 DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
 241 DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
 242 DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);
 243 DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
 244 DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
 245 DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);
 246 DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);
 247 DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);
 248 DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
 249 DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
 250 DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 251 DEFINE_CLOCK(fec_clk,    0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 252 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 253 DEFINE_CLOCK(lcdc_clk,   0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
 254 DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 255 DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
 256 DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
 257 DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
 258 DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
 259                 &esdhc1_per_clk);
 260 DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
 261                 &esdhc2_per_clk);
 262 DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 263 DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 264 DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
 265 DEFINE_CLOCK(can2_clk,   1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
 266
 267 #define _REGISTER_CLOCK(d, n, c)        \
 268         {                               \
 269                 .dev_id = d,            \
 270                 .con_id = n,            \
 271                 .clk = &c,              \
 272         },
 273
 274 static struct clk_lookup lookups[] = {
 275         /* i.mx25 has the i.mx21 type uart */
 276         _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
 277         _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
 278         _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
 279         _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
 280         _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
 281         _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
 282         _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
 283         _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
 284         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
 285         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 286         /* i.mx25 has the i.mx35 type cspi */
 287         _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
 288         _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
 289         _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
 290         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
 291         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
 292         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
 293         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
 294         _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
 295         _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
 296         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
 297         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
 298         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
 299         _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
 300         _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
 301         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
 302         _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
 303         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
 304         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
 305         _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
 306         _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
 307         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
 308         _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
 309         _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
 310         _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
 311         /* i.mx25 has the i.mx35 type sdma */
 312         _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
 313 };
 314
 315 int __init mx25_clocks_init(void)
 316 {
 317         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 318
 319         /* Turn off all clocks except the ones we need to survive, namely:
 320          * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
 321          * SCC
 322          */
 323         __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
 324         __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
 325         __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
 326 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
 327         clk_enable(&uart1_clk);
 328 #endif
 329
 330         /* Clock source for lcdc and csi is upll */
 331         __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
 332                         CRM_BASE + 0x64);
 333
 334         /* Clock source for gpt is ahb_div */
 335         __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
 336
 337         mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 338
 339         return 0;
 340 }