?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MIPS: Alchemy: prom_putchar is board dependent
[linux-2.6/linux-mips.git] / arch / sparc / kernel / irq_64.c
blobe1cbdb94d97bc10030e7ac5add8f1b22a54cc47e
1 /* irq.c: UltraSparc IRQ handling/init/registry.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/linkage.h>
11 #include <linux/ptrace.h>
12 #include <linux/errno.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/signal.h>
15 #include <linux/mm.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/random.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/proc_fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/irq.h>
24
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/atomic.h>
28 #include <asm/system.h>
29 #include <asm/irq.h>
30 #include <asm/io.h>
31 #include <asm/iommu.h>
32 #include <asm/upa.h>
33 #include <asm/oplib.h>
34 #include <asm/prom.h>
35 #include <asm/timer.h>
36 #include <asm/smp.h>
37 #include <asm/starfire.h>
38 #include <asm/uaccess.h>
39 #include <asm/cache.h>
40 #include <asm/cpudata.h>
41 #include <asm/auxio.h>
42 #include <asm/head.h>
43 #include <asm/hypervisor.h>
44 #include <asm/cacheflush.h>
45
46 #include "entry.h"
47 #include "cpumap.h"
48
49 #define NUM_IVECS (IMAP_INR + 1)
50
51 struct ino_bucket *ivector_table;
52 unsigned long ivector_table_pa;
53
54 /* On several sun4u processors, it is illegal to mix bypass and
55 * non-bypass accesses. Therefore we access all INO buckets
56 * using bypass accesses only.
57 */
58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
59 {
60 unsigned long ret;
61
62 __asm__ __volatile__("ldxa [%1] %2, %0"
63 : "=&r" (ret)
64 : "r" (bucket_pa +
65 offsetof(struct ino_bucket,
66 __irq_chain_pa)),
67 "i" (ASI_PHYS_USE_EC));
68
69 return ret;
70 }
71
72 static void bucket_clear_chain_pa(unsigned long bucket_pa)
73 {
74 __asm__ __volatile__("stxa %%g0, [%0] %1"
75 : /* no outputs */
76 : "r" (bucket_pa +
77 offsetof(struct ino_bucket,
78 __irq_chain_pa)),
79 "i" (ASI_PHYS_USE_EC));
80 }
81
82 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
83 {
84 unsigned int ret;
85
86 __asm__ __volatile__("lduwa [%1] %2, %0"
87 : "=&r" (ret)
88 : "r" (bucket_pa +
89 offsetof(struct ino_bucket,
90 __virt_irq)),
91 "i" (ASI_PHYS_USE_EC));
92
93 return ret;
94 }
95
96 static void bucket_set_virt_irq(unsigned long bucket_pa,
97 unsigned int virt_irq)
98 {
99 __asm__ __volatile__("stwa %0, [%1] %2"
100 : /* no outputs */
101 : "r" (virt_irq),
102 "r" (bucket_pa +
103 offsetof(struct ino_bucket,
104 __virt_irq)),
105 "i" (ASI_PHYS_USE_EC));
106 }
107
108 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
109
110 static struct {
111 unsigned int dev_handle;
112 unsigned int dev_ino;
113 unsigned int in_use;
114 } virt_irq_table[NR_IRQS];
115 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
116
117 unsigned char virt_irq_alloc(unsigned int dev_handle,
118 unsigned int dev_ino)
119 {
120 unsigned long flags;
121 unsigned char ent;
122
123 BUILD_BUG_ON(NR_IRQS >= 256);
124
125 spin_lock_irqsave(&virt_irq_alloc_lock, flags);
126
127 for (ent = 1; ent < NR_IRQS; ent++) {
128 if (!virt_irq_table[ent].in_use)
129 break;
130 }
131 if (ent >= NR_IRQS) {
132 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
133 ent = 0;
134 } else {
135 virt_irq_table[ent].dev_handle = dev_handle;
136 virt_irq_table[ent].dev_ino = dev_ino;
137 virt_irq_table[ent].in_use = 1;
138 }
139
140 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
141
142 return ent;
143 }
144
145 #ifdef CONFIG_PCI_MSI
146 void virt_irq_free(unsigned int virt_irq)
147 {
148 unsigned long flags;
149
150 if (virt_irq >= NR_IRQS)
151 return;
152
153 spin_lock_irqsave(&virt_irq_alloc_lock, flags);
154
155 virt_irq_table[virt_irq].in_use = 0;
156
157 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
158 }
159 #endif
160
161 /*
162 * /proc/interrupts printing:
163 */
164
165 int show_interrupts(struct seq_file *p, void *v)
166 {
167 int i = *(loff_t *) v, j;
168 struct irqaction * action;
169 unsigned long flags;
170
171 if (i == 0) {
172 seq_printf(p, " ");
173 for_each_online_cpu(j)
174 seq_printf(p, "CPU%d ",j);
175 seq_putc(p, '\n');
176 }
177
178 if (i < NR_IRQS) {
179 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
180 action = irq_desc[i].action;
181 if (!action)
182 goto skip;
183 seq_printf(p, "%3d: ",i);
184 #ifndef CONFIG_SMP
185 seq_printf(p, "%10u ", kstat_irqs(i));
186 #else
187 for_each_online_cpu(j)
188 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
189 #endif
190 seq_printf(p, " %9s", irq_desc[i].chip->name);
191 seq_printf(p, " %s", action->name);
192
193 for (action=action->next; action; action = action->next)
194 seq_printf(p, ", %s", action->name);
195
196 seq_putc(p, '\n');
197 skip:
198 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
199 } else if (i == NR_IRQS) {
200 seq_printf(p, "NMI: ");
201 for_each_online_cpu(j)
202 seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
203 seq_printf(p, " Non-maskable interrupts\n");
204 }
205 return 0;
206 }
207
208 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
209 {
210 unsigned int tid;
211
212 if (this_is_starfire) {
213 tid = starfire_translate(imap, cpuid);
214 tid <<= IMAP_TID_SHIFT;
215 tid &= IMAP_TID_UPA;
216 } else {
217 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
218 unsigned long ver;
219
220 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
221 if ((ver >> 32UL) == __JALAPENO_ID ||
222 (ver >> 32UL) == __SERRANO_ID) {
223 tid = cpuid << IMAP_TID_SHIFT;
224 tid &= IMAP_TID_JBUS;
225 } else {
226 unsigned int a = cpuid & 0x1f;
227 unsigned int n = (cpuid >> 5) & 0x1f;
228
229 tid = ((a << IMAP_AID_SHIFT) |
230 (n << IMAP_NID_SHIFT));
231 tid &= (IMAP_AID_SAFARI |
232 IMAP_NID_SAFARI);
233 }
234 } else {
235 tid = cpuid << IMAP_TID_SHIFT;
236 tid &= IMAP_TID_UPA;
237 }
238 }
239
240 return tid;
241 }
242
243 struct irq_handler_data {
244 unsigned long iclr;
245 unsigned long imap;
246
247 void (*pre_handler)(unsigned int, void *, void *);
248 void *arg1;
249 void *arg2;
250 };
251
252 #ifdef CONFIG_SMP
253 static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity)
254 {
255 cpumask_t mask;
256 int cpuid;
257
258 cpumask_copy(&mask, affinity);
259 if (cpus_equal(mask, cpu_online_map)) {
260 cpuid = map_to_cpu(virt_irq);
261 } else {
262 cpumask_t tmp;
263
264 cpus_and(tmp, cpu_online_map, mask);
265 cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp);
266 }
267
268 return cpuid;
269 }
270 #else
271 #define irq_choose_cpu(virt_irq, affinity) \
272 real_hard_smp_processor_id()
273 #endif
274
275 static void sun4u_irq_enable(unsigned int virt_irq)
276 {
277 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
278
279 if (likely(data)) {
280 unsigned long cpuid, imap, val;
281 unsigned int tid;
282
283 cpuid = irq_choose_cpu(virt_irq,
284 irq_desc[virt_irq].affinity);
285 imap = data->imap;
286
287 tid = sun4u_compute_tid(imap, cpuid);
288
289 val = upa_readq(imap);
290 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
291 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
292 val |= tid | IMAP_VALID;
293 upa_writeq(val, imap);
294 upa_writeq(ICLR_IDLE, data->iclr);
295 }
296 }
297
298 static int sun4u_set_affinity(unsigned int virt_irq,
299 const struct cpumask *mask)
300 {
301 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
302
303 if (likely(data)) {
304 unsigned long cpuid, imap, val;
305 unsigned int tid;
306
307 cpuid = irq_choose_cpu(virt_irq, mask);
308 imap = data->imap;
309
310 tid = sun4u_compute_tid(imap, cpuid);
311
312 val = upa_readq(imap);
313 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
314 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
315 val |= tid | IMAP_VALID;
316 upa_writeq(val, imap);
317 upa_writeq(ICLR_IDLE, data->iclr);
318 }
319
320 return 0;
321 }
322
323 /* Don't do anything. The desc->status check for IRQ_DISABLED in
324 * handler_irq() will skip the handler call and that will leave the
325 * interrupt in the sent state. The next ->enable() call will hit the
326 * ICLR register to reset the state machine.
327 *
328 * This scheme is necessary, instead of clearing the Valid bit in the
329 * IMAP register, to handle the case of IMAP registers being shared by
330 * multiple INOs (and thus ICLR registers). Since we use a different
331 * virtual IRQ for each shared IMAP instance, the generic code thinks
332 * there is only one user so it prematurely calls ->disable() on
333 * free_irq().
334 *
335 * We have to provide an explicit ->disable() method instead of using
336 * NULL to get the default. The reason is that if the generic code
337 * sees that, it also hooks up a default ->shutdown method which
338 * invokes ->mask() which we do not want. See irq_chip_set_defaults().
339 */
340 static void sun4u_irq_disable(unsigned int virt_irq)
341 {
342 }
343
344 static void sun4u_irq_eoi(unsigned int virt_irq)
345 {
346 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
347 struct irq_desc *desc = irq_desc + virt_irq;
348
349 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
350 return;
351
352 if (likely(data))
353 upa_writeq(ICLR_IDLE, data->iclr);
354 }
355
356 static void sun4v_irq_enable(unsigned int virt_irq)
357 {
358 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
359 unsigned long cpuid = irq_choose_cpu(virt_irq,
360 irq_desc[virt_irq].affinity);
361 int err;
362
363 err = sun4v_intr_settarget(ino, cpuid);
364 if (err != HV_EOK)
365 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
366 "err(%d)\n", ino, cpuid, err);
367 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
368 if (err != HV_EOK)
369 printk(KERN_ERR "sun4v_intr_setstate(%x): "
370 "err(%d)\n", ino, err);
371 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
372 if (err != HV_EOK)
373 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
374 ino, err);
375 }
376
377 static int sun4v_set_affinity(unsigned int virt_irq,
378 const struct cpumask *mask)
379 {
380 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
381 unsigned long cpuid = irq_choose_cpu(virt_irq, mask);
382 int err;
383
384 err = sun4v_intr_settarget(ino, cpuid);
385 if (err != HV_EOK)
386 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
387 "err(%d)\n", ino, cpuid, err);
388
389 return 0;
390 }
391
392 static void sun4v_irq_disable(unsigned int virt_irq)
393 {
394 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
395 int err;
396
397 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
398 if (err != HV_EOK)
399 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
400 "err(%d)\n", ino, err);
401 }
402
403 static void sun4v_irq_eoi(unsigned int virt_irq)
404 {
405 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
406 struct irq_desc *desc = irq_desc + virt_irq;
407 int err;
408
409 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
410 return;
411
412 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
413 if (err != HV_EOK)
414 printk(KERN_ERR "sun4v_intr_setstate(%x): "
415 "err(%d)\n", ino, err);
416 }
417
418 static void sun4v_virq_enable(unsigned int virt_irq)
419 {
420 unsigned long cpuid, dev_handle, dev_ino;
421 int err;
422
423 cpuid = irq_choose_cpu(virt_irq, irq_desc[virt_irq].affinity);
424
425 dev_handle = virt_irq_table[virt_irq].dev_handle;
426 dev_ino = virt_irq_table[virt_irq].dev_ino;
427
428 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
429 if (err != HV_EOK)
430 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
431 "err(%d)\n",
432 dev_handle, dev_ino, cpuid, err);
433 err = sun4v_vintr_set_state(dev_handle, dev_ino,
434 HV_INTR_STATE_IDLE);
435 if (err != HV_EOK)
436 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
437 "HV_INTR_STATE_IDLE): err(%d)\n",
438 dev_handle, dev_ino, err);
439 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
440 HV_INTR_ENABLED);
441 if (err != HV_EOK)
442 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
443 "HV_INTR_ENABLED): err(%d)\n",
444 dev_handle, dev_ino, err);
445 }
446
447 static int sun4v_virt_set_affinity(unsigned int virt_irq,
448 const struct cpumask *mask)
449 {
450 unsigned long cpuid, dev_handle, dev_ino;
451 int err;
452
453 cpuid = irq_choose_cpu(virt_irq, mask);
454
455 dev_handle = virt_irq_table[virt_irq].dev_handle;
456 dev_ino = virt_irq_table[virt_irq].dev_ino;
457
458 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
459 if (err != HV_EOK)
460 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
461 "err(%d)\n",
462 dev_handle, dev_ino, cpuid, err);
463
464 return 0;
465 }
466
467 static void sun4v_virq_disable(unsigned int virt_irq)
468 {
469 unsigned long dev_handle, dev_ino;
470 int err;
471
472 dev_handle = virt_irq_table[virt_irq].dev_handle;
473 dev_ino = virt_irq_table[virt_irq].dev_ino;
474
475 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
476 HV_INTR_DISABLED);
477 if (err != HV_EOK)
478 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
479 "HV_INTR_DISABLED): err(%d)\n",
480 dev_handle, dev_ino, err);
481 }
482
483 static void sun4v_virq_eoi(unsigned int virt_irq)
484 {
485 struct irq_desc *desc = irq_desc + virt_irq;
486 unsigned long dev_handle, dev_ino;
487 int err;
488
489 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
490 return;
491
492 dev_handle = virt_irq_table[virt_irq].dev_handle;
493 dev_ino = virt_irq_table[virt_irq].dev_ino;
494
495 err = sun4v_vintr_set_state(dev_handle, dev_ino,
496 HV_INTR_STATE_IDLE);
497 if (err != HV_EOK)
498 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
499 "HV_INTR_STATE_IDLE): err(%d)\n",
500 dev_handle, dev_ino, err);
501 }
502
503 static struct irq_chip sun4u_irq = {
504 .name = "sun4u",
505 .enable = sun4u_irq_enable,
506 .disable = sun4u_irq_disable,
507 .eoi = sun4u_irq_eoi,
508 .set_affinity = sun4u_set_affinity,
509 };
510
511 static struct irq_chip sun4v_irq = {
512 .name = "sun4v",
513 .enable = sun4v_irq_enable,
514 .disable = sun4v_irq_disable,
515 .eoi = sun4v_irq_eoi,
516 .set_affinity = sun4v_set_affinity,
517 };
518
519 static struct irq_chip sun4v_virq = {
520 .name = "vsun4v",
521 .enable = sun4v_virq_enable,
522 .disable = sun4v_virq_disable,
523 .eoi = sun4v_virq_eoi,
524 .set_affinity = sun4v_virt_set_affinity,
525 };
526
527 static void pre_flow_handler(unsigned int virt_irq,
528 struct irq_desc *desc)
529 {
530 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
531 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
532
533 data->pre_handler(ino, data->arg1, data->arg2);
534
535 handle_fasteoi_irq(virt_irq, desc);
536 }
537
538 void irq_install_pre_handler(int virt_irq,
539 void (*func)(unsigned int, void *, void *),
540 void *arg1, void *arg2)
541 {
542 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
543 struct irq_desc *desc = irq_desc + virt_irq;
544
545 data->pre_handler = func;
546 data->arg1 = arg1;
547 data->arg2 = arg2;
548
549 desc->handle_irq = pre_flow_handler;
550 }
551
552 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
553 {
554 struct ino_bucket *bucket;
555 struct irq_handler_data *data;
556 unsigned int virt_irq;
557 int ino;
558
559 BUG_ON(tlb_type == hypervisor);
560
561 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
562 bucket = &ivector_table[ino];
563 virt_irq = bucket_get_virt_irq(__pa(bucket));
564 if (!virt_irq) {
565 virt_irq = virt_irq_alloc(0, ino);
566 bucket_set_virt_irq(__pa(bucket), virt_irq);
567 set_irq_chip_and_handler_name(virt_irq,
568 &sun4u_irq,
569 handle_fasteoi_irq,
570 "IVEC");
571 }
572
573 data = get_irq_chip_data(virt_irq);
574 if (unlikely(data))
575 goto out;
576
577 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
578 if (unlikely(!data)) {
579 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
580 prom_halt();
581 }
582 set_irq_chip_data(virt_irq, data);
583
584 data->imap = imap;
585 data->iclr = iclr;
586
587 out:
588 return virt_irq;
589 }
590
591 static unsigned int sun4v_build_common(unsigned long sysino,
592 struct irq_chip *chip)
593 {
594 struct ino_bucket *bucket;
595 struct irq_handler_data *data;
596 unsigned int virt_irq;
597
598 BUG_ON(tlb_type != hypervisor);
599
600 bucket = &ivector_table[sysino];
601 virt_irq = bucket_get_virt_irq(__pa(bucket));
602 if (!virt_irq) {
603 virt_irq = virt_irq_alloc(0, sysino);
604 bucket_set_virt_irq(__pa(bucket), virt_irq);
605 set_irq_chip_and_handler_name(virt_irq, chip,
606 handle_fasteoi_irq,
607 "IVEC");
608 }
609
610 data = get_irq_chip_data(virt_irq);
611 if (unlikely(data))
612 goto out;
613
614 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
615 if (unlikely(!data)) {
616 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
617 prom_halt();
618 }
619 set_irq_chip_data(virt_irq, data);
620
621 /* Catch accidental accesses to these things. IMAP/ICLR handling
622 * is done by hypervisor calls on sun4v platforms, not by direct
623 * register accesses.
624 */
625 data->imap = ~0UL;
626 data->iclr = ~0UL;
627
628 out:
629 return virt_irq;
630 }
631
632 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
633 {
634 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
635
636 return sun4v_build_common(sysino, &sun4v_irq);
637 }
638
639 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
640 {
641 struct irq_handler_data *data;
642 unsigned long hv_err, cookie;
643 struct ino_bucket *bucket;
644 struct irq_desc *desc;
645 unsigned int virt_irq;
646
647 bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
648 if (unlikely(!bucket))
649 return 0;
650 __flush_dcache_range((unsigned long) bucket,
651 ((unsigned long) bucket +
652 sizeof(struct ino_bucket)));
653
654 virt_irq = virt_irq_alloc(devhandle, devino);
655 bucket_set_virt_irq(__pa(bucket), virt_irq);
656
657 set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
658 handle_fasteoi_irq,
659 "IVEC");
660
661 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
662 if (unlikely(!data))
663 return 0;
664
665 /* In order to make the LDC channel startup sequence easier,
666 * especially wrt. locking, we do not let request_irq() enable
667 * the interrupt.
668 */
669 desc = irq_desc + virt_irq;
670 desc->status |= IRQ_NOAUTOEN;
671
672 set_irq_chip_data(virt_irq, data);
673
674 /* Catch accidental accesses to these things. IMAP/ICLR handling
675 * is done by hypervisor calls on sun4v platforms, not by direct
676 * register accesses.
677 */
678 data->imap = ~0UL;
679 data->iclr = ~0UL;
680
681 cookie = ~__pa(bucket);
682 hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
683 if (hv_err) {
684 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
685 "err=%lu\n", devhandle, devino, hv_err);
686 prom_halt();
687 }
688
689 return virt_irq;
690 }
691
692 void ack_bad_irq(unsigned int virt_irq)
693 {
694 unsigned int ino = virt_irq_table[virt_irq].dev_ino;
695
696 if (!ino)
697 ino = 0xdeadbeef;
698
699 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
700 ino, virt_irq);
701 }
702
703 void *hardirq_stack[NR_CPUS];
704 void *softirq_stack[NR_CPUS];
705
706 static __attribute__((always_inline)) void *set_hardirq_stack(void)
707 {
708 void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
709
710 __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
711 if (orig_sp < sp ||
712 orig_sp > (sp + THREAD_SIZE)) {
713 sp += THREAD_SIZE - 192 - STACK_BIAS;
714 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
715 }
716
717 return orig_sp;
718 }
719 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
720 {
721 __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
722 }
723
724 void handler_irq(int irq, struct pt_regs *regs)
725 {
726 unsigned long pstate, bucket_pa;
727 struct pt_regs *old_regs;
728 void *orig_sp;
729
730 clear_softint(1 << irq);
731
732 old_regs = set_irq_regs(regs);
733 irq_enter();
734
735 /* Grab an atomic snapshot of the pending IVECs. */
736 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
737 "wrpr %0, %3, %%pstate\n\t"
738 "ldx [%2], %1\n\t"
739 "stx %%g0, [%2]\n\t"
740 "wrpr %0, 0x0, %%pstate\n\t"
741 : "=&r" (pstate), "=&r" (bucket_pa)
742 : "r" (irq_work_pa(smp_processor_id())),
743 "i" (PSTATE_IE)
744 : "memory");
745
746 orig_sp = set_hardirq_stack();
747
748 while (bucket_pa) {
749 struct irq_desc *desc;
750 unsigned long next_pa;
751 unsigned int virt_irq;
752
753 next_pa = bucket_get_chain_pa(bucket_pa);
754 virt_irq = bucket_get_virt_irq(bucket_pa);
755 bucket_clear_chain_pa(bucket_pa);
756
757 desc = irq_desc + virt_irq;
758
759 if (!(desc->status & IRQ_DISABLED))
760 desc->handle_irq(virt_irq, desc);
761
762 bucket_pa = next_pa;
763 }
764
765 restore_hardirq_stack(orig_sp);
766
767 irq_exit();
768 set_irq_regs(old_regs);
769 }
770
771 void do_softirq(void)
772 {
773 unsigned long flags;
774
775 if (in_interrupt())
776 return;
777
778 local_irq_save(flags);
779
780 if (local_softirq_pending()) {
781 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
782
783 sp += THREAD_SIZE - 192 - STACK_BIAS;
784
785 __asm__ __volatile__("mov %%sp, %0\n\t"
786 "mov %1, %%sp"
787 : "=&r" (orig_sp)
788 : "r" (sp));
789 __do_softirq();
790 __asm__ __volatile__("mov %0, %%sp"
791 : : "r" (orig_sp));
792 }
793
794 local_irq_restore(flags);
795 }
796
797 #ifdef CONFIG_HOTPLUG_CPU
798 void fixup_irqs(void)
799 {
800 unsigned int irq;
801
802 for (irq = 0; irq < NR_IRQS; irq++) {
803 unsigned long flags;
804
805 raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
806 if (irq_desc[irq].action &&
807 !(irq_desc[irq].status & IRQ_PER_CPU)) {
808 if (irq_desc[irq].chip->set_affinity)
809 irq_desc[irq].chip->set_affinity(irq,
810 irq_desc[irq].affinity);
811 }
812 raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
813 }
814
815 tick_ops->disable_irq();
816 }
817 #endif
818
819 struct sun5_timer {
820 u64 count0;
821 u64 limit0;
822 u64 count1;
823 u64 limit1;
824 };
825
826 static struct sun5_timer *prom_timers;
827 static u64 prom_limit0, prom_limit1;
828
829 static void map_prom_timers(void)
830 {
831 struct device_node *dp;
832 const unsigned int *addr;
833
834 /* PROM timer node hangs out in the top level of device siblings... */
835 dp = of_find_node_by_path("/");
836 dp = dp->child;
837 while (dp) {
838 if (!strcmp(dp->name, "counter-timer"))
839 break;
840 dp = dp->sibling;
841 }
842
843 /* Assume if node is not present, PROM uses different tick mechanism
844 * which we should not care about.
845 */
846 if (!dp) {
847 prom_timers = (struct sun5_timer *) 0;
848 return;
849 }
850
851 /* If PROM is really using this, it must be mapped by him. */
852 addr = of_get_property(dp, "address", NULL);
853 if (!addr) {
854 prom_printf("PROM does not have timer mapped, trying to continue.\n");
855 prom_timers = (struct sun5_timer *) 0;
856 return;
857 }
858 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
859 }
860
861 static void kill_prom_timer(void)
862 {
863 if (!prom_timers)
864 return;
865
866 /* Save them away for later. */
867 prom_limit0 = prom_timers->limit0;
868 prom_limit1 = prom_timers->limit1;
869
870 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
871 * We turn both off here just to be paranoid.
872 */
873 prom_timers->limit0 = 0;
874 prom_timers->limit1 = 0;
875
876 /* Wheee, eat the interrupt packet too... */
877 __asm__ __volatile__(
878 " mov 0x40, %%g2\n"
879 " ldxa [%%g0] %0, %%g1\n"
880 " ldxa [%%g2] %1, %%g1\n"
881 " stxa %%g0, [%%g0] %0\n"
882 " membar #Sync\n"
883 : /* no outputs */
884 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
885 : "g1", "g2");
886 }
887
888 void notrace init_irqwork_curcpu(void)
889 {
890 int cpu = hard_smp_processor_id();
891
892 trap_block[cpu].irq_worklist_pa = 0UL;
893 }
894
895 /* Please be very careful with register_one_mondo() and
896 * sun4v_register_mondo_queues().
897 *
898 * On SMP this gets invoked from the CPU trampoline before
899 * the cpu has fully taken over the trap table from OBP,
900 * and it's kernel stack + %g6 thread register state is
901 * not fully cooked yet.
902 *
903 * Therefore you cannot make any OBP calls, not even prom_printf,
904 * from these two routines.
905 */
906 static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
907 {
908 unsigned long num_entries = (qmask + 1) / 64;
909 unsigned long status;
910
911 status = sun4v_cpu_qconf(type, paddr, num_entries);
912 if (status != HV_EOK) {
913 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
914 "err %lu\n", type, paddr, num_entries, status);
915 prom_halt();
916 }
917 }
918
919 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
920 {
921 struct trap_per_cpu *tb = &trap_block[this_cpu];
922
923 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
924 tb->cpu_mondo_qmask);
925 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
926 tb->dev_mondo_qmask);
927 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
928 tb->resum_qmask);
929 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
930 tb->nonresum_qmask);
931 }
932
933 /* Each queue region must be a power of 2 multiple of 64 bytes in
934 * size. The base real address must be aligned to the size of the
935 * region. Thus, an 8KB queue must be 8KB aligned, for example.
936 */
937 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
938 {
939 unsigned long size = PAGE_ALIGN(qmask + 1);
940 unsigned long order = get_order(size);
941 unsigned long p;
942
943 p = __get_free_pages(GFP_KERNEL, order);
944 if (!p) {
945 prom_printf("SUN4V: Error, cannot allocate queue.\n");
946 prom_halt();
947 }
948
949 *pa_ptr = __pa(p);
950 }
951
952 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
953 {
954 #ifdef CONFIG_SMP
955 unsigned long page;
956
957 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
958
959 page = get_zeroed_page(GFP_KERNEL);
960 if (!page) {
961 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
962 prom_halt();
963 }
964
965 tb->cpu_mondo_block_pa = __pa(page);
966 tb->cpu_list_pa = __pa(page + 64);
967 #endif
968 }
969
970 /* Allocate mondo and error queues for all possible cpus. */
971 static void __init sun4v_init_mondo_queues(void)
972 {
973 int cpu;
974
975 for_each_possible_cpu(cpu) {
976 struct trap_per_cpu *tb = &trap_block[cpu];
977
978 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
979 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
980 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
981 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
982 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
983 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
984 tb->nonresum_qmask);
985 }
986 }
987
988 static void __init init_send_mondo_info(void)
989 {
990 int cpu;
991
992 for_each_possible_cpu(cpu) {
993 struct trap_per_cpu *tb = &trap_block[cpu];
994
995 init_cpu_send_mondo_info(tb);
996 }
997 }
998
999 static struct irqaction timer_irq_action = {
1000 .name = "timer",
1001 };
1002
1003 /* Only invoked on boot processor. */
1004 void __init init_IRQ(void)
1005 {
1006 unsigned long size;
1007
1008 map_prom_timers();
1009 kill_prom_timer();
1010
1011 size = sizeof(struct ino_bucket) * NUM_IVECS;
1012 ivector_table = kzalloc(size, GFP_KERNEL);
1013 if (!ivector_table) {
1014 prom_printf("Fatal error, cannot allocate ivector_table\n");
1015 prom_halt();
1016 }
1017 __flush_dcache_range((unsigned long) ivector_table,
1018 ((unsigned long) ivector_table) + size);
1019
1020 ivector_table_pa = __pa(ivector_table);
1021
1022 if (tlb_type == hypervisor)
1023 sun4v_init_mondo_queues();
1024
1025 init_send_mondo_info();
1026
1027 if (tlb_type == hypervisor) {
1028 /* Load up the boot cpu's entries. */
1029 sun4v_register_mondo_queues(hard_smp_processor_id());
1030 }
1031
1032 /* We need to clear any IRQ's pending in the soft interrupt
1033 * registers, a spurious one could be left around from the
1034 * PROM timer which we just disabled.
1035 */
1036 clear_softint(get_softint());
1037
1038 /* Now that ivector table is initialized, it is safe
1039 * to receive IRQ vector traps. We will normally take
1040 * one or two right now, in case some device PROM used
1041 * to boot us wants to speak to us. We just ignore them.
1042 */
1043 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
1044 "or %%g1, %0, %%g1\n\t"
1045 "wrpr %%g1, 0x0, %%pstate"
1046 : /* No outputs */
1047 : "i" (PSTATE_IE)
1048 : "g1");
1049
1050 irq_desc[0].action = &timer_irq_action;
1051 }
Mirror of the linux-mips.org kernel tree