?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
timerfd: Allow timers to be cancelled when clock was set
[linux-2.6/linux-mips.git] / drivers / net / dl2k.c
blobc05db6046050981360c7789859a12b953bafe20c
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12
13 #define DRV_NAME "DL2000/TC902x-based linux driver"
14 #define DRV_VERSION "v1.19"
15 #define DRV_RELDATE "2007/08/12"
16 #include "dl2k.h"
17 #include <linux/dma-mapping.h>
18
19 static char version[] __devinitdata =
20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
21 #define MAX_UNITS 8
22 static int mtu[MAX_UNITS];
23 static int vlan[MAX_UNITS];
24 static int jumbo[MAX_UNITS];
25 static char *media[MAX_UNITS];
26 static int tx_flow=-1;
27 static int rx_flow=-1;
28 static int copy_thresh;
29 static int rx_coalesce=10; /* Rx frame count each interrupt */
30 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34 MODULE_AUTHOR ("Edward Peng");
35 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36 MODULE_LICENSE("GPL");
37 module_param_array(mtu, int, NULL, 0);
38 module_param_array(media, charp, NULL, 0);
39 module_param_array(vlan, int, NULL, 0);
40 module_param_array(jumbo, int, NULL, 0);
41 module_param(tx_flow, int, 0);
42 module_param(rx_flow, int, 0);
43 module_param(copy_thresh, int, 0);
44 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49 /* Enable the default interrupts */
50 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52 #define EnableInt() \
53 writew(DEFAULT_INTR, ioaddr + IntEnable)
54
55 static const int max_intrloop = 50;
56 static const int multicast_filter_limit = 0x40;
57
58 static int rio_open (struct net_device *dev);
59 static void rio_timer (unsigned long data);
60 static void rio_tx_timeout (struct net_device *dev);
61 static void alloc_list (struct net_device *dev);
62 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
63 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
64 static void rio_free_tx (struct net_device *dev, int irq);
65 static void tx_error (struct net_device *dev, int tx_status);
66 static int receive_packet (struct net_device *dev);
67 static void rio_error (struct net_device *dev, int int_status);
68 static int change_mtu (struct net_device *dev, int new_mtu);
69 static void set_multicast (struct net_device *dev);
70 static struct net_device_stats *get_stats (struct net_device *dev);
71 static int clear_stats (struct net_device *dev);
72 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
73 static int rio_close (struct net_device *dev);
74 static int find_miiphy (struct net_device *dev);
75 static int parse_eeprom (struct net_device *dev);
76 static int read_eeprom (long ioaddr, int eep_addr);
77 static int mii_wait_link (struct net_device *dev, int wait);
78 static int mii_set_media (struct net_device *dev);
79 static int mii_get_media (struct net_device *dev);
80 static int mii_set_media_pcs (struct net_device *dev);
81 static int mii_get_media_pcs (struct net_device *dev);
82 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
83 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
84 u16 data);
85
86 static const struct ethtool_ops ethtool_ops;
87
88 static const struct net_device_ops netdev_ops = {
89 .ndo_open = rio_open,
90 .ndo_start_xmit = start_xmit,
91 .ndo_stop = rio_close,
92 .ndo_get_stats = get_stats,
93 .ndo_validate_addr = eth_validate_addr,
94 .ndo_set_mac_address = eth_mac_addr,
95 .ndo_set_multicast_list = set_multicast,
96 .ndo_do_ioctl = rio_ioctl,
97 .ndo_tx_timeout = rio_tx_timeout,
98 .ndo_change_mtu = change_mtu,
99 };
100
101 static int __devinit
102 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
103 {
104 struct net_device *dev;
105 struct netdev_private *np;
106 static int card_idx;
107 int chip_idx = ent->driver_data;
108 int err, irq;
109 long ioaddr;
110 static int version_printed;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 if (!version_printed++)
115 printk ("%s", version);
116
117 err = pci_enable_device (pdev);
118 if (err)
119 return err;
120
121 irq = pdev->irq;
122 err = pci_request_regions (pdev, "dl2k");
123 if (err)
124 goto err_out_disable;
125
126 pci_set_master (pdev);
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev) {
129 err = -ENOMEM;
130 goto err_out_res;
131 }
132 SET_NETDEV_DEV(dev, &pdev->dev);
133
134 #ifdef MEM_MAPPING
135 ioaddr = pci_resource_start (pdev, 1);
136 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
137 if (!ioaddr) {
138 err = -ENOMEM;
139 goto err_out_dev;
140 }
141 #else
142 ioaddr = pci_resource_start (pdev, 0);
143 #endif
144 dev->base_addr = ioaddr;
145 dev->irq = irq;
146 np = netdev_priv(dev);
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149 spin_lock_init (&np->tx_lock);
150 spin_lock_init (&np->rx_lock);
151
152 /* Parse manual configuration */
153 np->an_enable = 1;
154 np->tx_coalesce = 1;
155 if (card_idx < MAX_UNITS) {
156 if (media[card_idx] != NULL) {
157 np->an_enable = 0;
158 if (strcmp (media[card_idx], "auto") == 0 ||
159 strcmp (media[card_idx], "autosense") == 0 ||
160 strcmp (media[card_idx], "0") == 0 ) {
161 np->an_enable = 2;
162 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
163 strcmp (media[card_idx], "4") == 0) {
164 np->speed = 100;
165 np->full_duplex = 1;
166 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
167 strcmp (media[card_idx], "3") == 0) {
168 np->speed = 100;
169 np->full_duplex = 0;
170 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
171 strcmp (media[card_idx], "2") == 0) {
172 np->speed = 10;
173 np->full_duplex = 1;
174 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
175 strcmp (media[card_idx], "1") == 0) {
176 np->speed = 10;
177 np->full_duplex = 0;
178 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
179 strcmp (media[card_idx], "6") == 0) {
180 np->speed=1000;
181 np->full_duplex=1;
182 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
183 strcmp (media[card_idx], "5") == 0) {
184 np->speed = 1000;
185 np->full_duplex = 0;
186 } else {
187 np->an_enable = 1;
188 }
189 }
190 if (jumbo[card_idx] != 0) {
191 np->jumbo = 1;
192 dev->mtu = MAX_JUMBO;
193 } else {
194 np->jumbo = 0;
195 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
196 dev->mtu = mtu[card_idx];
197 }
198 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
199 vlan[card_idx] : 0;
200 if (rx_coalesce > 0 && rx_timeout > 0) {
201 np->rx_coalesce = rx_coalesce;
202 np->rx_timeout = rx_timeout;
203 np->coalesce = 1;
204 }
205 np->tx_flow = (tx_flow == 0) ? 0 : 1;
206 np->rx_flow = (rx_flow == 0) ? 0 : 1;
207
208 if (tx_coalesce < 1)
209 tx_coalesce = 1;
210 else if (tx_coalesce > TX_RING_SIZE-1)
211 tx_coalesce = TX_RING_SIZE - 1;
212 }
213 dev->netdev_ops = &netdev_ops;
214 dev->watchdog_timeo = TX_TIMEOUT;
215 SET_ETHTOOL_OPS(dev, &ethtool_ops);
216 #if 0
217 dev->features = NETIF_F_IP_CSUM;
218 #endif
219 pci_set_drvdata (pdev, dev);
220
221 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
222 if (!ring_space)
223 goto err_out_iounmap;
224 np->tx_ring = (struct netdev_desc *) ring_space;
225 np->tx_ring_dma = ring_dma;
226
227 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
228 if (!ring_space)
229 goto err_out_unmap_tx;
230 np->rx_ring = (struct netdev_desc *) ring_space;
231 np->rx_ring_dma = ring_dma;
232
233 /* Parse eeprom data */
234 parse_eeprom (dev);
235
236 /* Find PHY address */
237 err = find_miiphy (dev);
238 if (err)
239 goto err_out_unmap_rx;
240
241 /* Fiber device? */
242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
243 np->link_status = 0;
244 /* Set media and reset PHY */
245 if (np->phy_media) {
246 /* default Auto-Negotiation for fiber deivices */
247 if (np->an_enable == 2) {
248 np->an_enable = 1;
249 }
250 mii_set_media_pcs (dev);
251 } else {
252 /* Auto-Negotiation is mandatory for 1000BASE-T,
253 IEEE 802.3ab Annex 28D page 14 */
254 if (np->speed == 1000)
255 np->an_enable = 1;
256 mii_set_media (dev);
257 }
258
259 err = register_netdev (dev);
260 if (err)
261 goto err_out_unmap_rx;
262
263 card_idx++;
264
265 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
266 dev->name, np->name, dev->dev_addr, irq);
267 if (tx_coalesce > 1)
268 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
269 tx_coalesce);
270 if (np->coalesce)
271 printk(KERN_INFO
272 "rx_coalesce:\t%d packets\n"
273 "rx_timeout: \t%d ns\n",
274 np->rx_coalesce, np->rx_timeout*640);
275 if (np->vlan)
276 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
277 return 0;
278
279 err_out_unmap_rx:
280 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
281 err_out_unmap_tx:
282 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
283 err_out_iounmap:
284 #ifdef MEM_MAPPING
285 iounmap ((void *) ioaddr);
286
287 err_out_dev:
288 #endif
289 free_netdev (dev);
290
291 err_out_res:
292 pci_release_regions (pdev);
293
294 err_out_disable:
295 pci_disable_device (pdev);
296 return err;
297 }
298
299 static int
300 find_miiphy (struct net_device *dev)
301 {
302 int i, phy_found = 0;
303 struct netdev_private *np;
304 long ioaddr;
305 np = netdev_priv(dev);
306 ioaddr = dev->base_addr;
307 np->phy_addr = 1;
308
309 for (i = 31; i >= 0; i--) {
310 int mii_status = mii_read (dev, i, 1);
311 if (mii_status != 0xffff && mii_status != 0x0000) {
312 np->phy_addr = i;
313 phy_found++;
314 }
315 }
316 if (!phy_found) {
317 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
318 return -ENODEV;
319 }
320 return 0;
321 }
322
323 static int
324 parse_eeprom (struct net_device *dev)
325 {
326 int i, j;
327 long ioaddr = dev->base_addr;
328 u8 sromdata[256];
329 u8 *psib;
330 u32 crc;
331 PSROM_t psrom = (PSROM_t) sromdata;
332 struct netdev_private *np = netdev_priv(dev);
333
334 int cid, next;
335
336 #ifdef MEM_MAPPING
337 ioaddr = pci_resource_start (np->pdev, 0);
338 #endif
339 /* Read eeprom */
340 for (i = 0; i < 128; i++) {
341 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
342 }
343 #ifdef MEM_MAPPING
344 ioaddr = dev->base_addr;
345 #endif
346 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
347 /* Check CRC */
348 crc = ~ether_crc_le (256 - 4, sromdata);
349 if (psrom->crc != crc) {
350 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
351 dev->name);
352 return -1;
353 }
354 }
355
356 /* Set MAC address */
357 for (i = 0; i < 6; i++)
358 dev->dev_addr[i] = psrom->mac_addr[i];
359
360 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
361 return 0;
362 }
363
364 /* Parse Software Information Block */
365 i = 0x30;
366 psib = (u8 *) sromdata;
367 do {
368 cid = psib[i++];
369 next = psib[i++];
370 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
371 printk (KERN_ERR "Cell data error\n");
372 return -1;
373 }
374 switch (cid) {
375 case 0: /* Format version */
376 break;
377 case 1: /* End of cell */
378 return 0;
379 case 2: /* Duplex Polarity */
380 np->duplex_polarity = psib[i];
381 writeb (readb (ioaddr + PhyCtrl) | psib[i],
382 ioaddr + PhyCtrl);
383 break;
384 case 3: /* Wake Polarity */
385 np->wake_polarity = psib[i];
386 break;
387 case 9: /* Adapter description */
388 j = (next - i > 255) ? 255 : next - i;
389 memcpy (np->name, &(psib[i]), j);
390 break;
391 case 4:
392 case 5:
393 case 6:
394 case 7:
395 case 8: /* Reversed */
396 break;
397 default: /* Unknown cell */
398 return -1;
399 }
400 i = next;
401 } while (1);
402
403 return 0;
404 }
405
406 static int
407 rio_open (struct net_device *dev)
408 {
409 struct netdev_private *np = netdev_priv(dev);
410 long ioaddr = dev->base_addr;
411 int i;
412 u16 macctrl;
413
414 i = request_irq (dev->irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
415 if (i)
416 return i;
417
418 /* Reset all logic functions */
419 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
420 ioaddr + ASICCtrl + 2);
421 mdelay(10);
422
423 /* DebugCtrl bit 4, 5, 9 must set */
424 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
425
426 /* Jumbo frame */
427 if (np->jumbo != 0)
428 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
429
430 alloc_list (dev);
431
432 /* Get station address */
433 for (i = 0; i < 6; i++)
434 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
435
436 set_multicast (dev);
437 if (np->coalesce) {
438 writel (np->rx_coalesce | np->rx_timeout << 16,
439 ioaddr + RxDMAIntCtrl);
440 }
441 /* Set RIO to poll every N*320nsec. */
442 writeb (0x20, ioaddr + RxDMAPollPeriod);
443 writeb (0xff, ioaddr + TxDMAPollPeriod);
444 writeb (0x30, ioaddr + RxDMABurstThresh);
445 writeb (0x30, ioaddr + RxDMAUrgentThresh);
446 writel (0x0007ffff, ioaddr + RmonStatMask);
447 /* clear statistics */
448 clear_stats (dev);
449
450 /* VLAN supported */
451 if (np->vlan) {
452 /* priority field in RxDMAIntCtrl */
453 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
454 ioaddr + RxDMAIntCtrl);
455 /* VLANId */
456 writew (np->vlan, ioaddr + VLANId);
457 /* Length/Type should be 0x8100 */
458 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
459 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
460 VLAN information tagged by TFC' VID, CFI fields. */
461 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
462 ioaddr + MACCtrl);
463 }
464
465 init_timer (&np->timer);
466 np->timer.expires = jiffies + 1*HZ;
467 np->timer.data = (unsigned long) dev;
468 np->timer.function = rio_timer;
469 add_timer (&np->timer);
470
471 /* Start Tx/Rx */
472 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
473 ioaddr + MACCtrl);
474
475 macctrl = 0;
476 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
477 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
478 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
479 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
480 writew(macctrl, ioaddr + MACCtrl);
481
482 netif_start_queue (dev);
483
484 /* Enable default interrupts */
485 EnableInt ();
486 return 0;
487 }
488
489 static void
490 rio_timer (unsigned long data)
491 {
492 struct net_device *dev = (struct net_device *)data;
493 struct netdev_private *np = netdev_priv(dev);
494 unsigned int entry;
495 int next_tick = 1*HZ;
496 unsigned long flags;
497
498 spin_lock_irqsave(&np->rx_lock, flags);
499 /* Recover rx ring exhausted error */
500 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
501 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
502 /* Re-allocate skbuffs to fill the descriptor ring */
503 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
504 struct sk_buff *skb;
505 entry = np->old_rx % RX_RING_SIZE;
506 /* Dropped packets don't need to re-allocate */
507 if (np->rx_skbuff[entry] == NULL) {
508 skb = netdev_alloc_skb_ip_align(dev,
509 np->rx_buf_sz);
510 if (skb == NULL) {
511 np->rx_ring[entry].fraginfo = 0;
512 printk (KERN_INFO
513 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
514 dev->name, entry);
515 break;
516 }
517 np->rx_skbuff[entry] = skb;
518 np->rx_ring[entry].fraginfo =
519 cpu_to_le64 (pci_map_single
520 (np->pdev, skb->data, np->rx_buf_sz,
521 PCI_DMA_FROMDEVICE));
522 }
523 np->rx_ring[entry].fraginfo |=
524 cpu_to_le64((u64)np->rx_buf_sz << 48);
525 np->rx_ring[entry].status = 0;
526 } /* end for */
527 } /* end if */
528 spin_unlock_irqrestore (&np->rx_lock, flags);
529 np->timer.expires = jiffies + next_tick;
530 add_timer(&np->timer);
531 }
532
533 static void
534 rio_tx_timeout (struct net_device *dev)
535 {
536 long ioaddr = dev->base_addr;
537
538 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
539 dev->name, readl (ioaddr + TxStatus));
540 rio_free_tx(dev, 0);
541 dev->if_port = 0;
542 dev->trans_start = jiffies; /* prevent tx timeout */
543 }
544
545 /* allocate and initialize Tx and Rx descriptors */
546 static void
547 alloc_list (struct net_device *dev)
548 {
549 struct netdev_private *np = netdev_priv(dev);
550 int i;
551
552 np->cur_rx = np->cur_tx = 0;
553 np->old_rx = np->old_tx = 0;
554 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
555
556 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
557 for (i = 0; i < TX_RING_SIZE; i++) {
558 np->tx_skbuff[i] = NULL;
559 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
560 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
561 ((i+1)%TX_RING_SIZE) *
562 sizeof (struct netdev_desc));
563 }
564
565 /* Initialize Rx descriptors */
566 for (i = 0; i < RX_RING_SIZE; i++) {
567 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
568 ((i + 1) % RX_RING_SIZE) *
569 sizeof (struct netdev_desc));
570 np->rx_ring[i].status = 0;
571 np->rx_ring[i].fraginfo = 0;
572 np->rx_skbuff[i] = NULL;
573 }
574
575 /* Allocate the rx buffers */
576 for (i = 0; i < RX_RING_SIZE; i++) {
577 /* Allocated fixed size of skbuff */
578 struct sk_buff *skb;
579
580 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
581 np->rx_skbuff[i] = skb;
582 if (skb == NULL) {
583 printk (KERN_ERR
584 "%s: alloc_list: allocate Rx buffer error! ",
585 dev->name);
586 break;
587 }
588 /* Rubicon now supports 40 bits of addressing space. */
589 np->rx_ring[i].fraginfo =
590 cpu_to_le64 ( pci_map_single (
591 np->pdev, skb->data, np->rx_buf_sz,
592 PCI_DMA_FROMDEVICE));
593 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
594 }
595
596 /* Set RFDListPtr */
597 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
598 writel (0, dev->base_addr + RFDListPtr1);
599 }
600
601 static netdev_tx_t
602 start_xmit (struct sk_buff *skb, struct net_device *dev)
603 {
604 struct netdev_private *np = netdev_priv(dev);
605 struct netdev_desc *txdesc;
606 unsigned entry;
607 u32 ioaddr;
608 u64 tfc_vlan_tag = 0;
609
610 if (np->link_status == 0) { /* Link Down */
611 dev_kfree_skb(skb);
612 return NETDEV_TX_OK;
613 }
614 ioaddr = dev->base_addr;
615 entry = np->cur_tx % TX_RING_SIZE;
616 np->tx_skbuff[entry] = skb;
617 txdesc = &np->tx_ring[entry];
618
619 #if 0
620 if (skb->ip_summed == CHECKSUM_PARTIAL) {
621 txdesc->status |=
622 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
623 IPChecksumEnable);
624 }
625 #endif
626 if (np->vlan) {
627 tfc_vlan_tag = VLANTagInsert |
628 ((u64)np->vlan << 32) |
629 ((u64)skb->priority << 45);
630 }
631 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
632 skb->len,
633 PCI_DMA_TODEVICE));
634 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
635
636 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
637 * Work around: Always use 1 descriptor in 10Mbps mode */
638 if (entry % np->tx_coalesce == 0 || np->speed == 10)
639 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
640 WordAlignDisable |
641 TxDMAIndicate |
642 (1 << FragCountShift));
643 else
644 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
645 WordAlignDisable |
646 (1 << FragCountShift));
647
648 /* TxDMAPollNow */
649 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
650 /* Schedule ISR */
651 writel(10000, ioaddr + CountDown);
652 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
653 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
654 < TX_QUEUE_LEN - 1 && np->speed != 10) {
655 /* do nothing */
656 } else if (!netif_queue_stopped(dev)) {
657 netif_stop_queue (dev);
658 }
659
660 /* The first TFDListPtr */
661 if (readl (dev->base_addr + TFDListPtr0) == 0) {
662 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
663 dev->base_addr + TFDListPtr0);
664 writel (0, dev->base_addr + TFDListPtr1);
665 }
666
667 return NETDEV_TX_OK;
668 }
669
670 static irqreturn_t
671 rio_interrupt (int irq, void *dev_instance)
672 {
673 struct net_device *dev = dev_instance;
674 struct netdev_private *np;
675 unsigned int_status;
676 long ioaddr;
677 int cnt = max_intrloop;
678 int handled = 0;
679
680 ioaddr = dev->base_addr;
681 np = netdev_priv(dev);
682 while (1) {
683 int_status = readw (ioaddr + IntStatus);
684 writew (int_status, ioaddr + IntStatus);
685 int_status &= DEFAULT_INTR;
686 if (int_status == 0 || --cnt < 0)
687 break;
688 handled = 1;
689 /* Processing received packets */
690 if (int_status & RxDMAComplete)
691 receive_packet (dev);
692 /* TxDMAComplete interrupt */
693 if ((int_status & (TxDMAComplete|IntRequested))) {
694 int tx_status;
695 tx_status = readl (ioaddr + TxStatus);
696 if (tx_status & 0x01)
697 tx_error (dev, tx_status);
698 /* Free used tx skbuffs */
699 rio_free_tx (dev, 1);
700 }
701
702 /* Handle uncommon events */
703 if (int_status &
704 (HostError | LinkEvent | UpdateStats))
705 rio_error (dev, int_status);
706 }
707 if (np->cur_tx != np->old_tx)
708 writel (100, ioaddr + CountDown);
709 return IRQ_RETVAL(handled);
710 }
711
712 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
713 {
714 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
715 }
716
717 static void
718 rio_free_tx (struct net_device *dev, int irq)
719 {
720 struct netdev_private *np = netdev_priv(dev);
721 int entry = np->old_tx % TX_RING_SIZE;
722 int tx_use = 0;
723 unsigned long flag = 0;
724
725 if (irq)
726 spin_lock(&np->tx_lock);
727 else
728 spin_lock_irqsave(&np->tx_lock, flag);
729
730 /* Free used tx skbuffs */
731 while (entry != np->cur_tx) {
732 struct sk_buff *skb;
733
734 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
735 break;
736 skb = np->tx_skbuff[entry];
737 pci_unmap_single (np->pdev,
738 desc_to_dma(&np->tx_ring[entry]),
739 skb->len, PCI_DMA_TODEVICE);
740 if (irq)
741 dev_kfree_skb_irq (skb);
742 else
743 dev_kfree_skb (skb);
744
745 np->tx_skbuff[entry] = NULL;
746 entry = (entry + 1) % TX_RING_SIZE;
747 tx_use++;
748 }
749 if (irq)
750 spin_unlock(&np->tx_lock);
751 else
752 spin_unlock_irqrestore(&np->tx_lock, flag);
753 np->old_tx = entry;
754
755 /* If the ring is no longer full, clear tx_full and
756 call netif_wake_queue() */
757
758 if (netif_queue_stopped(dev) &&
759 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
760 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
761 netif_wake_queue (dev);
762 }
763 }
764
765 static void
766 tx_error (struct net_device *dev, int tx_status)
767 {
768 struct netdev_private *np;
769 long ioaddr = dev->base_addr;
770 int frame_id;
771 int i;
772
773 np = netdev_priv(dev);
774
775 frame_id = (tx_status & 0xffff0000);
776 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
777 dev->name, tx_status, frame_id);
778 np->stats.tx_errors++;
779 /* Ttransmit Underrun */
780 if (tx_status & 0x10) {
781 np->stats.tx_fifo_errors++;
782 writew (readw (ioaddr + TxStartThresh) + 0x10,
783 ioaddr + TxStartThresh);
784 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
785 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
786 ioaddr + ASICCtrl + 2);
787 /* Wait for ResetBusy bit clear */
788 for (i = 50; i > 0; i--) {
789 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
790 break;
791 mdelay (1);
792 }
793 rio_free_tx (dev, 1);
794 /* Reset TFDListPtr */
795 writel (np->tx_ring_dma +
796 np->old_tx * sizeof (struct netdev_desc),
797 dev->base_addr + TFDListPtr0);
798 writel (0, dev->base_addr + TFDListPtr1);
799
800 /* Let TxStartThresh stay default value */
801 }
802 /* Late Collision */
803 if (tx_status & 0x04) {
804 np->stats.tx_fifo_errors++;
805 /* TxReset and clear FIFO */
806 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
807 /* Wait reset done */
808 for (i = 50; i > 0; i--) {
809 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
810 break;
811 mdelay (1);
812 }
813 /* Let TxStartThresh stay default value */
814 }
815 /* Maximum Collisions */
816 #ifdef ETHER_STATS
817 if (tx_status & 0x08)
818 np->stats.collisions16++;
819 #else
820 if (tx_status & 0x08)
821 np->stats.collisions++;
822 #endif
823 /* Restart the Tx */
824 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
825 }
826
827 static int
828 receive_packet (struct net_device *dev)
829 {
830 struct netdev_private *np = netdev_priv(dev);
831 int entry = np->cur_rx % RX_RING_SIZE;
832 int cnt = 30;
833
834 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
835 while (1) {
836 struct netdev_desc *desc = &np->rx_ring[entry];
837 int pkt_len;
838 u64 frame_status;
839
840 if (!(desc->status & cpu_to_le64(RFDDone)) ||
841 !(desc->status & cpu_to_le64(FrameStart)) ||
842 !(desc->status & cpu_to_le64(FrameEnd)))
843 break;
844
845 /* Chip omits the CRC. */
846 frame_status = le64_to_cpu(desc->status);
847 pkt_len = frame_status & 0xffff;
848 if (--cnt < 0)
849 break;
850 /* Update rx error statistics, drop packet. */
851 if (frame_status & RFS_Errors) {
852 np->stats.rx_errors++;
853 if (frame_status & (RxRuntFrame | RxLengthError))
854 np->stats.rx_length_errors++;
855 if (frame_status & RxFCSError)
856 np->stats.rx_crc_errors++;
857 if (frame_status & RxAlignmentError && np->speed != 1000)
858 np->stats.rx_frame_errors++;
859 if (frame_status & RxFIFOOverrun)
860 np->stats.rx_fifo_errors++;
861 } else {
862 struct sk_buff *skb;
863
864 /* Small skbuffs for short packets */
865 if (pkt_len > copy_thresh) {
866 pci_unmap_single (np->pdev,
867 desc_to_dma(desc),
868 np->rx_buf_sz,
869 PCI_DMA_FROMDEVICE);
870 skb_put (skb = np->rx_skbuff[entry], pkt_len);
871 np->rx_skbuff[entry] = NULL;
872 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
873 pci_dma_sync_single_for_cpu(np->pdev,
874 desc_to_dma(desc),
875 np->rx_buf_sz,
876 PCI_DMA_FROMDEVICE);
877 skb_copy_to_linear_data (skb,
878 np->rx_skbuff[entry]->data,
879 pkt_len);
880 skb_put (skb, pkt_len);
881 pci_dma_sync_single_for_device(np->pdev,
882 desc_to_dma(desc),
883 np->rx_buf_sz,
884 PCI_DMA_FROMDEVICE);
885 }
886 skb->protocol = eth_type_trans (skb, dev);
887 #if 0
888 /* Checksum done by hw, but csum value unavailable. */
889 if (np->pdev->pci_rev_id >= 0x0c &&
890 !(frame_status & (TCPError | UDPError | IPError))) {
891 skb->ip_summed = CHECKSUM_UNNECESSARY;
892 }
893 #endif
894 netif_rx (skb);
895 }
896 entry = (entry + 1) % RX_RING_SIZE;
897 }
898 spin_lock(&np->rx_lock);
899 np->cur_rx = entry;
900 /* Re-allocate skbuffs to fill the descriptor ring */
901 entry = np->old_rx;
902 while (entry != np->cur_rx) {
903 struct sk_buff *skb;
904 /* Dropped packets don't need to re-allocate */
905 if (np->rx_skbuff[entry] == NULL) {
906 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
907 if (skb == NULL) {
908 np->rx_ring[entry].fraginfo = 0;
909 printk (KERN_INFO
910 "%s: receive_packet: "
911 "Unable to re-allocate Rx skbuff.#%d\n",
912 dev->name, entry);
913 break;
914 }
915 np->rx_skbuff[entry] = skb;
916 np->rx_ring[entry].fraginfo =
917 cpu_to_le64 (pci_map_single
918 (np->pdev, skb->data, np->rx_buf_sz,
919 PCI_DMA_FROMDEVICE));
920 }
921 np->rx_ring[entry].fraginfo |=
922 cpu_to_le64((u64)np->rx_buf_sz << 48);
923 np->rx_ring[entry].status = 0;
924 entry = (entry + 1) % RX_RING_SIZE;
925 }
926 np->old_rx = entry;
927 spin_unlock(&np->rx_lock);
928 return 0;
929 }
930
931 static void
932 rio_error (struct net_device *dev, int int_status)
933 {
934 long ioaddr = dev->base_addr;
935 struct netdev_private *np = netdev_priv(dev);
936 u16 macctrl;
937
938 /* Link change event */
939 if (int_status & LinkEvent) {
940 if (mii_wait_link (dev, 10) == 0) {
941 printk (KERN_INFO "%s: Link up\n", dev->name);
942 if (np->phy_media)
943 mii_get_media_pcs (dev);
944 else
945 mii_get_media (dev);
946 if (np->speed == 1000)
947 np->tx_coalesce = tx_coalesce;
948 else
949 np->tx_coalesce = 1;
950 macctrl = 0;
951 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
952 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
953 macctrl |= (np->tx_flow) ?
954 TxFlowControlEnable : 0;
955 macctrl |= (np->rx_flow) ?
956 RxFlowControlEnable : 0;
957 writew(macctrl, ioaddr + MACCtrl);
958 np->link_status = 1;
959 netif_carrier_on(dev);
960 } else {
961 printk (KERN_INFO "%s: Link off\n", dev->name);
962 np->link_status = 0;
963 netif_carrier_off(dev);
964 }
965 }
966
967 /* UpdateStats statistics registers */
968 if (int_status & UpdateStats) {
969 get_stats (dev);
970 }
971
972 /* PCI Error, a catastronphic error related to the bus interface
973 occurs, set GlobalReset and HostReset to reset. */
974 if (int_status & HostError) {
975 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
976 dev->name, int_status);
977 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
978 mdelay (500);
979 }
980 }
981
982 static struct net_device_stats *
983 get_stats (struct net_device *dev)
984 {
985 long ioaddr = dev->base_addr;
986 struct netdev_private *np = netdev_priv(dev);
987 #ifdef MEM_MAPPING
988 int i;
989 #endif
990 unsigned int stat_reg;
991
992 /* All statistics registers need to be acknowledged,
993 else statistic overflow could cause problems */
994
995 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
996 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
997 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
998 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
999
1000 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1001 np->stats.collisions += readl (ioaddr + SingleColFrames)
1002 + readl (ioaddr + MultiColFrames);
1003
1004 /* detailed tx errors */
1005 stat_reg = readw (ioaddr + FramesAbortXSColls);
1006 np->stats.tx_aborted_errors += stat_reg;
1007 np->stats.tx_errors += stat_reg;
1008
1009 stat_reg = readw (ioaddr + CarrierSenseErrors);
1010 np->stats.tx_carrier_errors += stat_reg;
1011 np->stats.tx_errors += stat_reg;
1012
1013 /* Clear all other statistic register. */
1014 readl (ioaddr + McstOctetXmtOk);
1015 readw (ioaddr + BcstFramesXmtdOk);
1016 readl (ioaddr + McstFramesXmtdOk);
1017 readw (ioaddr + BcstFramesRcvdOk);
1018 readw (ioaddr + MacControlFramesRcvd);
1019 readw (ioaddr + FrameTooLongErrors);
1020 readw (ioaddr + InRangeLengthErrors);
1021 readw (ioaddr + FramesCheckSeqErrors);
1022 readw (ioaddr + FramesLostRxErrors);
1023 readl (ioaddr + McstOctetXmtOk);
1024 readl (ioaddr + BcstOctetXmtOk);
1025 readl (ioaddr + McstFramesXmtdOk);
1026 readl (ioaddr + FramesWDeferredXmt);
1027 readl (ioaddr + LateCollisions);
1028 readw (ioaddr + BcstFramesXmtdOk);
1029 readw (ioaddr + MacControlFramesXmtd);
1030 readw (ioaddr + FramesWEXDeferal);
1031
1032 #ifdef MEM_MAPPING
1033 for (i = 0x100; i <= 0x150; i += 4)
1034 readl (ioaddr + i);
1035 #endif
1036 readw (ioaddr + TxJumboFrames);
1037 readw (ioaddr + RxJumboFrames);
1038 readw (ioaddr + TCPCheckSumErrors);
1039 readw (ioaddr + UDPCheckSumErrors);
1040 readw (ioaddr + IPCheckSumErrors);
1041 return &np->stats;
1042 }
1043
1044 static int
1045 clear_stats (struct net_device *dev)
1046 {
1047 long ioaddr = dev->base_addr;
1048 #ifdef MEM_MAPPING
1049 int i;
1050 #endif
1051
1052 /* All statistics registers need to be acknowledged,
1053 else statistic overflow could cause problems */
1054 readl (ioaddr + FramesRcvOk);
1055 readl (ioaddr + FramesXmtOk);
1056 readl (ioaddr + OctetRcvOk);
1057 readl (ioaddr + OctetXmtOk);
1058
1059 readl (ioaddr + McstFramesRcvdOk);
1060 readl (ioaddr + SingleColFrames);
1061 readl (ioaddr + MultiColFrames);
1062 readl (ioaddr + LateCollisions);
1063 /* detailed rx errors */
1064 readw (ioaddr + FrameTooLongErrors);
1065 readw (ioaddr + InRangeLengthErrors);
1066 readw (ioaddr + FramesCheckSeqErrors);
1067 readw (ioaddr + FramesLostRxErrors);
1068
1069 /* detailed tx errors */
1070 readw (ioaddr + FramesAbortXSColls);
1071 readw (ioaddr + CarrierSenseErrors);
1072
1073 /* Clear all other statistic register. */
1074 readl (ioaddr + McstOctetXmtOk);
1075 readw (ioaddr + BcstFramesXmtdOk);
1076 readl (ioaddr + McstFramesXmtdOk);
1077 readw (ioaddr + BcstFramesRcvdOk);
1078 readw (ioaddr + MacControlFramesRcvd);
1079 readl (ioaddr + McstOctetXmtOk);
1080 readl (ioaddr + BcstOctetXmtOk);
1081 readl (ioaddr + McstFramesXmtdOk);
1082 readl (ioaddr + FramesWDeferredXmt);
1083 readw (ioaddr + BcstFramesXmtdOk);
1084 readw (ioaddr + MacControlFramesXmtd);
1085 readw (ioaddr + FramesWEXDeferal);
1086 #ifdef MEM_MAPPING
1087 for (i = 0x100; i <= 0x150; i += 4)
1088 readl (ioaddr + i);
1089 #endif
1090 readw (ioaddr + TxJumboFrames);
1091 readw (ioaddr + RxJumboFrames);
1092 readw (ioaddr + TCPCheckSumErrors);
1093 readw (ioaddr + UDPCheckSumErrors);
1094 readw (ioaddr + IPCheckSumErrors);
1095 return 0;
1096 }
1097
1098
1099 static int
1100 change_mtu (struct net_device *dev, int new_mtu)
1101 {
1102 struct netdev_private *np = netdev_priv(dev);
1103 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1104
1105 if ((new_mtu < 68) || (new_mtu > max)) {
1106 return -EINVAL;
1107 }
1108
1109 dev->mtu = new_mtu;
1110
1111 return 0;
1112 }
1113
1114 static void
1115 set_multicast (struct net_device *dev)
1116 {
1117 long ioaddr = dev->base_addr;
1118 u32 hash_table[2];
1119 u16 rx_mode = 0;
1120 struct netdev_private *np = netdev_priv(dev);
1121
1122 hash_table[0] = hash_table[1] = 0;
1123 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1124 hash_table[1] |= 0x02000000;
1125 if (dev->flags & IFF_PROMISC) {
1126 /* Receive all frames promiscuously. */
1127 rx_mode = ReceiveAllFrames;
1128 } else if ((dev->flags & IFF_ALLMULTI) ||
1129 (netdev_mc_count(dev) > multicast_filter_limit)) {
1130 /* Receive broadcast and multicast frames */
1131 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1132 } else if (!netdev_mc_empty(dev)) {
1133 struct netdev_hw_addr *ha;
1134 /* Receive broadcast frames and multicast frames filtering
1135 by Hashtable */
1136 rx_mode =
1137 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1138 netdev_for_each_mc_addr(ha, dev) {
1139 int bit, index = 0;
1140 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1141 /* The inverted high significant 6 bits of CRC are
1142 used as an index to hashtable */
1143 for (bit = 0; bit < 6; bit++)
1144 if (crc & (1 << (31 - bit)))
1145 index |= (1 << bit);
1146 hash_table[index / 32] |= (1 << (index % 32));
1147 }
1148 } else {
1149 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1150 }
1151 if (np->vlan) {
1152 /* ReceiveVLANMatch field in ReceiveMode */
1153 rx_mode |= ReceiveVLANMatch;
1154 }
1155
1156 writel (hash_table[0], ioaddr + HashTable0);
1157 writel (hash_table[1], ioaddr + HashTable1);
1158 writew (rx_mode, ioaddr + ReceiveMode);
1159 }
1160
1161 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1162 {
1163 struct netdev_private *np = netdev_priv(dev);
1164 strcpy(info->driver, "dl2k");
1165 strcpy(info->version, DRV_VERSION);
1166 strcpy(info->bus_info, pci_name(np->pdev));
1167 }
1168
1169 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1170 {
1171 struct netdev_private *np = netdev_priv(dev);
1172 if (np->phy_media) {
1173 /* fiber device */
1174 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1175 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1176 cmd->port = PORT_FIBRE;
1177 cmd->transceiver = XCVR_INTERNAL;
1178 } else {
1179 /* copper device */
1180 cmd->supported = SUPPORTED_10baseT_Half |
1181 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1182 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1183 SUPPORTED_Autoneg | SUPPORTED_MII;
1184 cmd->advertising = ADVERTISED_10baseT_Half |
1185 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1186 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1187 ADVERTISED_Autoneg | ADVERTISED_MII;
1188 cmd->port = PORT_MII;
1189 cmd->transceiver = XCVR_INTERNAL;
1190 }
1191 if ( np->link_status ) {
1192 cmd->speed = np->speed;
1193 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1194 } else {
1195 cmd->speed = -1;
1196 cmd->duplex = -1;
1197 }
1198 if ( np->an_enable)
1199 cmd->autoneg = AUTONEG_ENABLE;
1200 else
1201 cmd->autoneg = AUTONEG_DISABLE;
1202
1203 cmd->phy_address = np->phy_addr;
1204 return 0;
1205 }
1206
1207 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1208 {
1209 struct netdev_private *np = netdev_priv(dev);
1210 netif_carrier_off(dev);
1211 if (cmd->autoneg == AUTONEG_ENABLE) {
1212 if (np->an_enable)
1213 return 0;
1214 else {
1215 np->an_enable = 1;
1216 mii_set_media(dev);
1217 return 0;
1218 }
1219 } else {
1220 np->an_enable = 0;
1221 if (np->speed == 1000) {
1222 cmd->speed = SPEED_100;
1223 cmd->duplex = DUPLEX_FULL;
1224 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1225 }
1226 switch(cmd->speed + cmd->duplex) {
1227
1228 case SPEED_10 + DUPLEX_HALF:
1229 np->speed = 10;
1230 np->full_duplex = 0;
1231 break;
1232
1233 case SPEED_10 + DUPLEX_FULL:
1234 np->speed = 10;
1235 np->full_duplex = 1;
1236 break;
1237 case SPEED_100 + DUPLEX_HALF:
1238 np->speed = 100;
1239 np->full_duplex = 0;
1240 break;
1241 case SPEED_100 + DUPLEX_FULL:
1242 np->speed = 100;
1243 np->full_duplex = 1;
1244 break;
1245 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1246 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1247 default:
1248 return -EINVAL;
1249 }
1250 mii_set_media(dev);
1251 }
1252 return 0;
1253 }
1254
1255 static u32 rio_get_link(struct net_device *dev)
1256 {
1257 struct netdev_private *np = netdev_priv(dev);
1258 return np->link_status;
1259 }
1260
1261 static const struct ethtool_ops ethtool_ops = {
1262 .get_drvinfo = rio_get_drvinfo,
1263 .get_settings = rio_get_settings,
1264 .set_settings = rio_set_settings,
1265 .get_link = rio_get_link,
1266 };
1267
1268 static int
1269 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1270 {
1271 int phy_addr;
1272 struct netdev_private *np = netdev_priv(dev);
1273 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1274
1275 struct netdev_desc *desc;
1276 int i;
1277
1278 phy_addr = np->phy_addr;
1279 switch (cmd) {
1280 case SIOCDEVPRIVATE:
1281 break;
1282
1283 case SIOCDEVPRIVATE + 1:
1284 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1285 break;
1286 case SIOCDEVPRIVATE + 2:
1287 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1288 break;
1289 case SIOCDEVPRIVATE + 3:
1290 break;
1291 case SIOCDEVPRIVATE + 4:
1292 break;
1293 case SIOCDEVPRIVATE + 5:
1294 netif_stop_queue (dev);
1295 break;
1296 case SIOCDEVPRIVATE + 6:
1297 netif_wake_queue (dev);
1298 break;
1299 case SIOCDEVPRIVATE + 7:
1300 printk
1301 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1302 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1303 np->old_rx);
1304 break;
1305 case SIOCDEVPRIVATE + 8:
1306 printk("TX ring:\n");
1307 for (i = 0; i < TX_RING_SIZE; i++) {
1308 desc = &np->tx_ring[i];
1309 printk
1310 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1311 i,
1312 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1313 (u32)le64_to_cpu(desc->next_desc),
1314 (u32)le64_to_cpu(desc->status),
1315 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1316 (u32)le64_to_cpu(desc->fraginfo));
1317 printk ("\n");
1318 }
1319 printk ("\n");
1320 break;
1321
1322 default:
1323 return -EOPNOTSUPP;
1324 }
1325 return 0;
1326 }
1327
1328 #define EEP_READ 0x0200
1329 #define EEP_BUSY 0x8000
1330 /* Read the EEPROM word */
1331 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1332 static int
1333 read_eeprom (long ioaddr, int eep_addr)
1334 {
1335 int i = 1000;
1336 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1337 while (i-- > 0) {
1338 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1339 return inw (ioaddr + EepromData);
1340 }
1341 }
1342 return 0;
1343 }
1344
1345 enum phy_ctrl_bits {
1346 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1347 MII_DUPLEX = 0x08,
1348 };
1349
1350 #define mii_delay() readb(ioaddr)
1351 static void
1352 mii_sendbit (struct net_device *dev, u32 data)
1353 {
1354 long ioaddr = dev->base_addr + PhyCtrl;
1355 data = (data) ? MII_DATA1 : 0;
1356 data |= MII_WRITE;
1357 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1358 writeb (data, ioaddr);
1359 mii_delay ();
1360 writeb (data | MII_CLK, ioaddr);
1361 mii_delay ();
1362 }
1363
1364 static int
1365 mii_getbit (struct net_device *dev)
1366 {
1367 long ioaddr = dev->base_addr + PhyCtrl;
1368 u8 data;
1369
1370 data = (readb (ioaddr) & 0xf8) | MII_READ;
1371 writeb (data, ioaddr);
1372 mii_delay ();
1373 writeb (data | MII_CLK, ioaddr);
1374 mii_delay ();
1375 return ((readb (ioaddr) >> 1) & 1);
1376 }
1377
1378 static void
1379 mii_send_bits (struct net_device *dev, u32 data, int len)
1380 {
1381 int i;
1382 for (i = len - 1; i >= 0; i--) {
1383 mii_sendbit (dev, data & (1 << i));
1384 }
1385 }
1386
1387 static int
1388 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1389 {
1390 u32 cmd;
1391 int i;
1392 u32 retval = 0;
1393
1394 /* Preamble */
1395 mii_send_bits (dev, 0xffffffff, 32);
1396 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1397 /* ST,OP = 0110'b for read operation */
1398 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1399 mii_send_bits (dev, cmd, 14);
1400 /* Turnaround */
1401 if (mii_getbit (dev))
1402 goto err_out;
1403 /* Read data */
1404 for (i = 0; i < 16; i++) {
1405 retval |= mii_getbit (dev);
1406 retval <<= 1;
1407 }
1408 /* End cycle */
1409 mii_getbit (dev);
1410 return (retval >> 1) & 0xffff;
1411
1412 err_out:
1413 return 0;
1414 }
1415 static int
1416 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1417 {
1418 u32 cmd;
1419
1420 /* Preamble */
1421 mii_send_bits (dev, 0xffffffff, 32);
1422 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1423 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1424 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1425 mii_send_bits (dev, cmd, 32);
1426 /* End cycle */
1427 mii_getbit (dev);
1428 return 0;
1429 }
1430 static int
1431 mii_wait_link (struct net_device *dev, int wait)
1432 {
1433 __u16 bmsr;
1434 int phy_addr;
1435 struct netdev_private *np;
1436
1437 np = netdev_priv(dev);
1438 phy_addr = np->phy_addr;
1439
1440 do {
1441 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1442 if (bmsr & MII_BMSR_LINK_STATUS)
1443 return 0;
1444 mdelay (1);
1445 } while (--wait > 0);
1446 return -1;
1447 }
1448 static int
1449 mii_get_media (struct net_device *dev)
1450 {
1451 __u16 negotiate;
1452 __u16 bmsr;
1453 __u16 mscr;
1454 __u16 mssr;
1455 int phy_addr;
1456 struct netdev_private *np;
1457
1458 np = netdev_priv(dev);
1459 phy_addr = np->phy_addr;
1460
1461 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1462 if (np->an_enable) {
1463 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1464 /* Auto-Negotiation not completed */
1465 return -1;
1466 }
1467 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1468 mii_read (dev, phy_addr, MII_ANLPAR);
1469 mscr = mii_read (dev, phy_addr, MII_MSCR);
1470 mssr = mii_read (dev, phy_addr, MII_MSSR);
1471 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1472 np->speed = 1000;
1473 np->full_duplex = 1;
1474 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1475 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1476 np->speed = 1000;
1477 np->full_duplex = 0;
1478 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1479 } else if (negotiate & MII_ANAR_100BX_FD) {
1480 np->speed = 100;
1481 np->full_duplex = 1;
1482 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1483 } else if (negotiate & MII_ANAR_100BX_HD) {
1484 np->speed = 100;
1485 np->full_duplex = 0;
1486 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1487 } else if (negotiate & MII_ANAR_10BT_FD) {
1488 np->speed = 10;
1489 np->full_duplex = 1;
1490 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1491 } else if (negotiate & MII_ANAR_10BT_HD) {
1492 np->speed = 10;
1493 np->full_duplex = 0;
1494 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1495 }
1496 if (negotiate & MII_ANAR_PAUSE) {
1497 np->tx_flow &= 1;
1498 np->rx_flow &= 1;
1499 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1500 np->tx_flow = 0;
1501 np->rx_flow &= 1;
1502 }
1503 /* else tx_flow, rx_flow = user select */
1504 } else {
1505 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1506 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1507 case MII_BMCR_SPEED_1000:
1508 printk (KERN_INFO "Operating at 1000 Mbps, ");
1509 break;
1510 case MII_BMCR_SPEED_100:
1511 printk (KERN_INFO "Operating at 100 Mbps, ");
1512 break;
1513 case 0:
1514 printk (KERN_INFO "Operating at 10 Mbps, ");
1515 }
1516 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1517 printk (KERN_CONT "Full duplex\n");
1518 } else {
1519 printk (KERN_CONT "Half duplex\n");
1520 }
1521 }
1522 if (np->tx_flow)
1523 printk(KERN_INFO "Enable Tx Flow Control\n");
1524 else
1525 printk(KERN_INFO "Disable Tx Flow Control\n");
1526 if (np->rx_flow)
1527 printk(KERN_INFO "Enable Rx Flow Control\n");
1528 else
1529 printk(KERN_INFO "Disable Rx Flow Control\n");
1530
1531 return 0;
1532 }
1533
1534 static int
1535 mii_set_media (struct net_device *dev)
1536 {
1537 __u16 pscr;
1538 __u16 bmcr;
1539 __u16 bmsr;
1540 __u16 anar;
1541 int phy_addr;
1542 struct netdev_private *np;
1543 np = netdev_priv(dev);
1544 phy_addr = np->phy_addr;
1545
1546 /* Does user set speed? */
1547 if (np->an_enable) {
1548 /* Advertise capabilities */
1549 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1550 anar = mii_read (dev, phy_addr, MII_ANAR) &
1551 ~MII_ANAR_100BX_FD &
1552 ~MII_ANAR_100BX_HD &
1553 ~MII_ANAR_100BT4 &
1554 ~MII_ANAR_10BT_FD &
1555 ~MII_ANAR_10BT_HD;
1556 if (bmsr & MII_BMSR_100BX_FD)
1557 anar |= MII_ANAR_100BX_FD;
1558 if (bmsr & MII_BMSR_100BX_HD)
1559 anar |= MII_ANAR_100BX_HD;
1560 if (bmsr & MII_BMSR_100BT4)
1561 anar |= MII_ANAR_100BT4;
1562 if (bmsr & MII_BMSR_10BT_FD)
1563 anar |= MII_ANAR_10BT_FD;
1564 if (bmsr & MII_BMSR_10BT_HD)
1565 anar |= MII_ANAR_10BT_HD;
1566 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1567 mii_write (dev, phy_addr, MII_ANAR, anar);
1568
1569 /* Enable Auto crossover */
1570 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1571 pscr |= 3 << 5; /* 11'b */
1572 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1573
1574 /* Soft reset PHY */
1575 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1576 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1577 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1578 mdelay(1);
1579 } else {
1580 /* Force speed setting */
1581 /* 1) Disable Auto crossover */
1582 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1583 pscr &= ~(3 << 5);
1584 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1585
1586 /* 2) PHY Reset */
1587 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1588 bmcr |= MII_BMCR_RESET;
1589 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1590
1591 /* 3) Power Down */
1592 bmcr = 0x1940; /* must be 0x1940 */
1593 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1594 mdelay (100); /* wait a certain time */
1595
1596 /* 4) Advertise nothing */
1597 mii_write (dev, phy_addr, MII_ANAR, 0);
1598
1599 /* 5) Set media and Power Up */
1600 bmcr = MII_BMCR_POWER_DOWN;
1601 if (np->speed == 100) {
1602 bmcr |= MII_BMCR_SPEED_100;
1603 printk (KERN_INFO "Manual 100 Mbps, ");
1604 } else if (np->speed == 10) {
1605 printk (KERN_INFO "Manual 10 Mbps, ");
1606 }
1607 if (np->full_duplex) {
1608 bmcr |= MII_BMCR_DUPLEX_MODE;
1609 printk (KERN_CONT "Full duplex\n");
1610 } else {
1611 printk (KERN_CONT "Half duplex\n");
1612 }
1613 #if 0
1614 /* Set 1000BaseT Master/Slave setting */
1615 mscr = mii_read (dev, phy_addr, MII_MSCR);
1616 mscr |= MII_MSCR_CFG_ENABLE;
1617 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1618 #endif
1619 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1620 mdelay(10);
1621 }
1622 return 0;
1623 }
1624
1625 static int
1626 mii_get_media_pcs (struct net_device *dev)
1627 {
1628 __u16 negotiate;
1629 __u16 bmsr;
1630 int phy_addr;
1631 struct netdev_private *np;
1632
1633 np = netdev_priv(dev);
1634 phy_addr = np->phy_addr;
1635
1636 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1637 if (np->an_enable) {
1638 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1639 /* Auto-Negotiation not completed */
1640 return -1;
1641 }
1642 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1643 mii_read (dev, phy_addr, PCS_ANLPAR);
1644 np->speed = 1000;
1645 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1646 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1647 np->full_duplex = 1;
1648 } else {
1649 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1650 np->full_duplex = 0;
1651 }
1652 if (negotiate & PCS_ANAR_PAUSE) {
1653 np->tx_flow &= 1;
1654 np->rx_flow &= 1;
1655 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1656 np->tx_flow = 0;
1657 np->rx_flow &= 1;
1658 }
1659 /* else tx_flow, rx_flow = user select */
1660 } else {
1661 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1662 printk (KERN_INFO "Operating at 1000 Mbps, ");
1663 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1664 printk (KERN_CONT "Full duplex\n");
1665 } else {
1666 printk (KERN_CONT "Half duplex\n");
1667 }
1668 }
1669 if (np->tx_flow)
1670 printk(KERN_INFO "Enable Tx Flow Control\n");
1671 else
1672 printk(KERN_INFO "Disable Tx Flow Control\n");
1673 if (np->rx_flow)
1674 printk(KERN_INFO "Enable Rx Flow Control\n");
1675 else
1676 printk(KERN_INFO "Disable Rx Flow Control\n");
1677
1678 return 0;
1679 }
1680
1681 static int
1682 mii_set_media_pcs (struct net_device *dev)
1683 {
1684 __u16 bmcr;
1685 __u16 esr;
1686 __u16 anar;
1687 int phy_addr;
1688 struct netdev_private *np;
1689 np = netdev_priv(dev);
1690 phy_addr = np->phy_addr;
1691
1692 /* Auto-Negotiation? */
1693 if (np->an_enable) {
1694 /* Advertise capabilities */
1695 esr = mii_read (dev, phy_addr, PCS_ESR);
1696 anar = mii_read (dev, phy_addr, MII_ANAR) &
1697 ~PCS_ANAR_HALF_DUPLEX &
1698 ~PCS_ANAR_FULL_DUPLEX;
1699 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1700 anar |= PCS_ANAR_HALF_DUPLEX;
1701 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1702 anar |= PCS_ANAR_FULL_DUPLEX;
1703 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1704 mii_write (dev, phy_addr, MII_ANAR, anar);
1705
1706 /* Soft reset PHY */
1707 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1708 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1709 MII_BMCR_RESET;
1710 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1711 mdelay(1);
1712 } else {
1713 /* Force speed setting */
1714 /* PHY Reset */
1715 bmcr = MII_BMCR_RESET;
1716 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1717 mdelay(10);
1718 if (np->full_duplex) {
1719 bmcr = MII_BMCR_DUPLEX_MODE;
1720 printk (KERN_INFO "Manual full duplex\n");
1721 } else {
1722 bmcr = 0;
1723 printk (KERN_INFO "Manual half duplex\n");
1724 }
1725 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1726 mdelay(10);
1727
1728 /* Advertise nothing */
1729 mii_write (dev, phy_addr, MII_ANAR, 0);
1730 }
1731 return 0;
1732 }
1733
1734
1735 static int
1736 rio_close (struct net_device *dev)
1737 {
1738 long ioaddr = dev->base_addr;
1739 struct netdev_private *np = netdev_priv(dev);
1740 struct sk_buff *skb;
1741 int i;
1742
1743 netif_stop_queue (dev);
1744
1745 /* Disable interrupts */
1746 writew (0, ioaddr + IntEnable);
1747
1748 /* Stop Tx and Rx logics */
1749 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1750
1751 free_irq (dev->irq, dev);
1752 del_timer_sync (&np->timer);
1753
1754 /* Free all the skbuffs in the queue. */
1755 for (i = 0; i < RX_RING_SIZE; i++) {
1756 skb = np->rx_skbuff[i];
1757 if (skb) {
1758 pci_unmap_single(np->pdev,
1759 desc_to_dma(&np->rx_ring[i]),
1760 skb->len, PCI_DMA_FROMDEVICE);
1761 dev_kfree_skb (skb);
1762 np->rx_skbuff[i] = NULL;
1763 }
1764 np->rx_ring[i].status = 0;
1765 np->rx_ring[i].fraginfo = 0;
1766 }
1767 for (i = 0; i < TX_RING_SIZE; i++) {
1768 skb = np->tx_skbuff[i];
1769 if (skb) {
1770 pci_unmap_single(np->pdev,
1771 desc_to_dma(&np->tx_ring[i]),
1772 skb->len, PCI_DMA_TODEVICE);
1773 dev_kfree_skb (skb);
1774 np->tx_skbuff[i] = NULL;
1775 }
1776 }
1777
1778 return 0;
1779 }
1780
1781 static void __devexit
1782 rio_remove1 (struct pci_dev *pdev)
1783 {
1784 struct net_device *dev = pci_get_drvdata (pdev);
1785
1786 if (dev) {
1787 struct netdev_private *np = netdev_priv(dev);
1788
1789 unregister_netdev (dev);
1790 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1791 np->rx_ring_dma);
1792 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1793 np->tx_ring_dma);
1794 #ifdef MEM_MAPPING
1795 iounmap ((char *) (dev->base_addr));
1796 #endif
1797 free_netdev (dev);
1798 pci_release_regions (pdev);
1799 pci_disable_device (pdev);
1800 }
1801 pci_set_drvdata (pdev, NULL);
1802 }
1803
1804 static struct pci_driver rio_driver = {
1805 .name = "dl2k",
1806 .id_table = rio_pci_tbl,
1807 .probe = rio_probe1,
1808 .remove = __devexit_p(rio_remove1),
1809 };
1810
1811 static int __init
1812 rio_init (void)
1813 {
1814 return pci_register_driver(&rio_driver);
1815 }
1816
1817 static void __exit
1818 rio_exit (void)
1819 {
1820 pci_unregister_driver (&rio_driver);
1821 }
1822
1823 module_init (rio_init);
1824 module_exit (rio_exit);
1825
1826 /*
1827
1828 Compile command:
1829
1830 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1831
1832 Read Documentation/networking/dl2k.txt for details.
1833
1834 */
1835
Mirror of the linux-mips.org kernel tree