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timerfd: Allow timers to be cancelled when clock was set
[linux-2.6/linux-mips.git] / drivers / net / sfc / siena.c
blobe4dd8986b1feaa6c5b848dc8f8c948c4305592d8
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
18 #include "bitfield.h"
19 #include "efx.h"
20 #include "nic.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "regs.h"
24 #include "io.h"
25 #include "phy.h"
26 #include "workarounds.h"
27 #include "mcdi.h"
28 #include "mcdi_pcol.h"
29
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32 static void siena_init_wol(struct efx_nic *efx);
33
34
35 static void siena_push_irq_moderation(struct efx_channel *channel)
36 {
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52 }
53
54 static void siena_push_multicast_hash(struct efx_nic *efx)
55 {
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
57
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
60 NULL, 0, NULL);
61 }
62
63 static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
65 {
66 struct efx_nic *efx = netdev_priv(net_dev);
67 uint32_t status;
68 int rc;
69
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
72 if (rc)
73 return rc;
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
75 return -EIO;
76
77 return 0;
78 }
79
80 static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
82 {
83 struct efx_nic *efx = netdev_priv(net_dev);
84 uint16_t value;
85 uint32_t status;
86 int rc;
87
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
90 if (rc)
91 return rc;
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
93 return -EIO;
94
95 return (int)value;
96 }
97
98 /* This call is responsible for hooking in the MAC and PHY operations */
99 static int siena_probe_port(struct efx_nic *efx)
100 {
101 int rc;
102
103 /* Hook in PHY operations table */
104 efx->phy_op = &efx_mcdi_phy_ops;
105
106 /* Set up MDIO structure for PHY */
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
110
111 /* Fill out MDIO structure, loopback modes, and initial link state */
112 rc = efx->phy_op->probe(efx);
113 if (rc != 0)
114 return rc;
115
116 /* Allocate buffer for stats */
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
119 if (rc)
120 return rc;
121 netif_dbg(efx, probe, efx->net_dev,
122 "stats buffer at %llx (virt %p phys %llx)\n",
123 (u64)efx->stats_buffer.dma_addr,
124 efx->stats_buffer.addr,
125 (u64)virt_to_phys(efx->stats_buffer.addr));
126
127 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
128
129 return 0;
130 }
131
132 static void siena_remove_port(struct efx_nic *efx)
133 {
134 efx->phy_op->remove(efx);
135 efx_nic_free_buffer(efx, &efx->stats_buffer);
136 }
137
138 static const struct efx_nic_register_test siena_register_tests[] = {
139 { FR_AZ_ADR_REGION,
140 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
141 { FR_CZ_USR_EV_CFG,
142 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_CFG,
144 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
145 { FR_AZ_TX_CFG,
146 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
147 { FR_AZ_TX_RESERVED,
148 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
149 { FR_AZ_SRM_TX_DC_CFG,
150 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
151 { FR_AZ_RX_DC_CFG,
152 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
153 { FR_AZ_RX_DC_PF_WM,
154 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
155 { FR_BZ_DP_CTRL,
156 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
157 { FR_BZ_RX_RSS_TKEY,
158 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
159 { FR_CZ_RX_RSS_IPV6_REG1,
160 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
161 { FR_CZ_RX_RSS_IPV6_REG2,
162 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
163 { FR_CZ_RX_RSS_IPV6_REG3,
164 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
165 };
166
167 static int siena_test_registers(struct efx_nic *efx)
168 {
169 return efx_nic_test_registers(efx, siena_register_tests,
170 ARRAY_SIZE(siena_register_tests));
171 }
172
173 /**************************************************************************
174 *
175 * Device reset
176 *
177 **************************************************************************
178 */
179
180 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
181 {
182 int rc;
183
184 /* Recover from a failed assertion pre-reset */
185 rc = efx_mcdi_handle_assertion(efx);
186 if (rc)
187 return rc;
188
189 if (method == RESET_TYPE_WORLD)
190 return efx_mcdi_reset_mc(efx);
191 else
192 return efx_mcdi_reset_port(efx);
193 }
194
195 static int siena_probe_nvconfig(struct efx_nic *efx)
196 {
197 return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
198 }
199
200 static int siena_probe_nic(struct efx_nic *efx)
201 {
202 struct siena_nic_data *nic_data;
203 bool already_attached = 0;
204 efx_oword_t reg;
205 int rc;
206
207 /* Allocate storage for hardware specific data */
208 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
209 if (!nic_data)
210 return -ENOMEM;
211 efx->nic_data = nic_data;
212
213 if (efx_nic_fpga_ver(efx) != 0) {
214 netif_err(efx, probe, efx->net_dev,
215 "Siena FPGA not supported\n");
216 rc = -ENODEV;
217 goto fail1;
218 }
219
220 efx_reado(efx, &reg, FR_AZ_CS_DEBUG);
221 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
222
223 efx_mcdi_init(efx);
224
225 /* Recover from a failed assertion before probing */
226 rc = efx_mcdi_handle_assertion(efx);
227 if (rc)
228 goto fail1;
229
230 /* Let the BMC know that the driver is now in charge of link and
231 * filter settings. We must do this before we reset the NIC */
232 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
233 if (rc) {
234 netif_err(efx, probe, efx->net_dev,
235 "Unable to register driver with MCPU\n");
236 goto fail2;
237 }
238 if (already_attached)
239 /* Not a fatal error */
240 netif_err(efx, probe, efx->net_dev,
241 "Host already registered with MCPU\n");
242
243 /* Now we can reset the NIC */
244 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
245 if (rc) {
246 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
247 goto fail3;
248 }
249
250 siena_init_wol(efx);
251
252 /* Allocate memory for INT_KER */
253 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
254 if (rc)
255 goto fail4;
256 BUG_ON(efx->irq_status.dma_addr & 0x0f);
257
258 netif_dbg(efx, probe, efx->net_dev,
259 "INT_KER at %llx (virt %p phys %llx)\n",
260 (unsigned long long)efx->irq_status.dma_addr,
261 efx->irq_status.addr,
262 (unsigned long long)virt_to_phys(efx->irq_status.addr));
263
264 /* Read in the non-volatile configuration */
265 rc = siena_probe_nvconfig(efx);
266 if (rc == -EINVAL) {
267 netif_err(efx, probe, efx->net_dev,
268 "NVRAM is invalid therefore using defaults\n");
269 efx->phy_type = PHY_TYPE_NONE;
270 efx->mdio.prtad = MDIO_PRTAD_NONE;
271 } else if (rc) {
272 goto fail5;
273 }
274
275 return 0;
276
277 fail5:
278 efx_nic_free_buffer(efx, &efx->irq_status);
279 fail4:
280 fail3:
281 efx_mcdi_drv_attach(efx, false, NULL);
282 fail2:
283 fail1:
284 kfree(efx->nic_data);
285 return rc;
286 }
287
288 /* This call performs hardware-specific global initialisation, such as
289 * defining the descriptor cache sizes and number of RSS channels.
290 * It does not set up any buffers, descriptor rings or event queues.
291 */
292 static int siena_init_nic(struct efx_nic *efx)
293 {
294 efx_oword_t temp;
295 int rc;
296
297 /* Recover from a failed assertion post-reset */
298 rc = efx_mcdi_handle_assertion(efx);
299 if (rc)
300 return rc;
301
302 /* Squash TX of packets of 16 bytes or less */
303 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
304 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
305 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
306
307 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
308 * descriptors (which is bad).
309 */
310 efx_reado(efx, &temp, FR_AZ_TX_CFG);
311 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
312 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
313 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
314
315 efx_reado(efx, &temp, FR_AZ_RX_CFG);
316 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
317 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
318 /* Enable hash insertion. This is broken for the 'Falcon' hash
319 * if IPv6 hashing is also enabled, so also select Toeplitz
320 * TCP/IPv4 and IPv4 hashes. */
321 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
322 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
323 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
324 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
325
326 /* Set hash key for IPv4 */
327 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
328 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
329
330 /* Enable IPv6 RSS */
331 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
332 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
333 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
334 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
335 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
336 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
337 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
338 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
339 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
340 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
341 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
342 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
343
344 /* Enable event logging */
345 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
346 if (rc)
347 return rc;
348
349 /* Set destination of both TX and RX Flush events */
350 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
351 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
352
353 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
354 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
355
356 efx_nic_init_common(efx);
357 return 0;
358 }
359
360 static void siena_remove_nic(struct efx_nic *efx)
361 {
362 efx_nic_free_buffer(efx, &efx->irq_status);
363
364 siena_reset_hw(efx, RESET_TYPE_ALL);
365
366 /* Relinquish the device back to the BMC */
367 if (efx_nic_has_mc(efx))
368 efx_mcdi_drv_attach(efx, false, NULL);
369
370 /* Tear down the private nic state */
371 kfree(efx->nic_data);
372 efx->nic_data = NULL;
373 }
374
375 #define STATS_GENERATION_INVALID ((u64)(-1))
376
377 static int siena_try_update_nic_stats(struct efx_nic *efx)
378 {
379 u64 *dma_stats;
380 struct efx_mac_stats *mac_stats;
381 u64 generation_start;
382 u64 generation_end;
383
384 mac_stats = &efx->mac_stats;
385 dma_stats = (u64 *)efx->stats_buffer.addr;
386
387 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
388 if (generation_end == STATS_GENERATION_INVALID)
389 return 0;
390 rmb();
391
392 #define MAC_STAT(M, D) \
393 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
394
395 MAC_STAT(tx_bytes, TX_BYTES);
396 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
397 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
398 mac_stats->tx_bad_bytes);
399 MAC_STAT(tx_packets, TX_PKTS);
400 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
401 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
402 MAC_STAT(tx_control, TX_CONTROL_PKTS);
403 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
404 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
405 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
406 MAC_STAT(tx_lt64, TX_LT64_PKTS);
407 MAC_STAT(tx_64, TX_64_PKTS);
408 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
409 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
410 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
411 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
412 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
413 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
414 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
415 mac_stats->tx_collision = 0;
416 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
417 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
418 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
419 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
420 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
421 mac_stats->tx_collision = (mac_stats->tx_single_collision +
422 mac_stats->tx_multiple_collision +
423 mac_stats->tx_excessive_collision +
424 mac_stats->tx_late_collision);
425 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
426 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
427 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
428 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
429 MAC_STAT(rx_bytes, RX_BYTES);
430 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
431 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
432 mac_stats->rx_bad_bytes);
433 MAC_STAT(rx_packets, RX_PKTS);
434 MAC_STAT(rx_good, RX_GOOD_PKTS);
435 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
436 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
437 MAC_STAT(rx_control, RX_CONTROL_PKTS);
438 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
439 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
440 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
441 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
442 MAC_STAT(rx_64, RX_64_PKTS);
443 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
444 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
445 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
446 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
447 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
448 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
449 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
450 mac_stats->rx_bad_lt64 = 0;
451 mac_stats->rx_bad_64_to_15xx = 0;
452 mac_stats->rx_bad_15xx_to_jumbo = 0;
453 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
454 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
455 mac_stats->rx_missed = 0;
456 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
457 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
458 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
459 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
460 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
461 mac_stats->rx_good_lt64 = 0;
462
463 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
464
465 #undef MAC_STAT
466
467 rmb();
468 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
469 if (generation_end != generation_start)
470 return -EAGAIN;
471
472 return 0;
473 }
474
475 static void siena_update_nic_stats(struct efx_nic *efx)
476 {
477 int retry;
478
479 /* If we're unlucky enough to read statistics wduring the DMA, wait
480 * up to 10ms for it to finish (typically takes <500us) */
481 for (retry = 0; retry < 100; ++retry) {
482 if (siena_try_update_nic_stats(efx) == 0)
483 return;
484 udelay(100);
485 }
486
487 /* Use the old values instead */
488 }
489
490 static void siena_start_nic_stats(struct efx_nic *efx)
491 {
492 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
493
494 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
495
496 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
497 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
498 }
499
500 static void siena_stop_nic_stats(struct efx_nic *efx)
501 {
502 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
503 }
504
505 /**************************************************************************
506 *
507 * Wake on LAN
508 *
509 **************************************************************************
510 */
511
512 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
513 {
514 struct siena_nic_data *nic_data = efx->nic_data;
515
516 wol->supported = WAKE_MAGIC;
517 if (nic_data->wol_filter_id != -1)
518 wol->wolopts = WAKE_MAGIC;
519 else
520 wol->wolopts = 0;
521 memset(&wol->sopass, 0, sizeof(wol->sopass));
522 }
523
524
525 static int siena_set_wol(struct efx_nic *efx, u32 type)
526 {
527 struct siena_nic_data *nic_data = efx->nic_data;
528 int rc;
529
530 if (type & ~WAKE_MAGIC)
531 return -EINVAL;
532
533 if (type & WAKE_MAGIC) {
534 if (nic_data->wol_filter_id != -1)
535 efx_mcdi_wol_filter_remove(efx,
536 nic_data->wol_filter_id);
537 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
538 &nic_data->wol_filter_id);
539 if (rc)
540 goto fail;
541
542 pci_wake_from_d3(efx->pci_dev, true);
543 } else {
544 rc = efx_mcdi_wol_filter_reset(efx);
545 nic_data->wol_filter_id = -1;
546 pci_wake_from_d3(efx->pci_dev, false);
547 if (rc)
548 goto fail;
549 }
550
551 return 0;
552 fail:
553 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
554 __func__, type, rc);
555 return rc;
556 }
557
558
559 static void siena_init_wol(struct efx_nic *efx)
560 {
561 struct siena_nic_data *nic_data = efx->nic_data;
562 int rc;
563
564 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
565
566 if (rc != 0) {
567 /* If it failed, attempt to get into a synchronised
568 * state with MC by resetting any set WoL filters */
569 efx_mcdi_wol_filter_reset(efx);
570 nic_data->wol_filter_id = -1;
571 } else if (nic_data->wol_filter_id != -1) {
572 pci_wake_from_d3(efx->pci_dev, true);
573 }
574 }
575
576
577 /**************************************************************************
578 *
579 * Revision-dependent attributes used by efx.c and nic.c
580 *
581 **************************************************************************
582 */
583
584 struct efx_nic_type siena_a0_nic_type = {
585 .probe = siena_probe_nic,
586 .remove = siena_remove_nic,
587 .init = siena_init_nic,
588 .fini = efx_port_dummy_op_void,
589 .monitor = NULL,
590 .reset = siena_reset_hw,
591 .probe_port = siena_probe_port,
592 .remove_port = siena_remove_port,
593 .prepare_flush = efx_port_dummy_op_void,
594 .update_stats = siena_update_nic_stats,
595 .start_stats = siena_start_nic_stats,
596 .stop_stats = siena_stop_nic_stats,
597 .set_id_led = efx_mcdi_set_id_led,
598 .push_irq_moderation = siena_push_irq_moderation,
599 .push_multicast_hash = siena_push_multicast_hash,
600 .reconfigure_port = efx_mcdi_phy_reconfigure,
601 .get_wol = siena_get_wol,
602 .set_wol = siena_set_wol,
603 .resume_wol = siena_init_wol,
604 .test_registers = siena_test_registers,
605 .test_nvram = efx_mcdi_nvram_test_all,
606 .default_mac_ops = &efx_mcdi_mac_operations,
607
608 .revision = EFX_REV_SIENA_A0,
609 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
610 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
611 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
612 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
613 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
614 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
615 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
616 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
617 .rx_buffer_hash_size = 0x10,
618 .rx_buffer_padding = 0,
619 .max_interrupt_mode = EFX_INT_MODE_MSIX,
620 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
621 * interrupt handler only supports 32
622 * channels */
623 .tx_dc_base = 0x88000,
624 .rx_dc_base = 0x68000,
625 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
626 NETIF_F_RXHASH | NETIF_F_NTUPLE),
627 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
628 };
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