MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / arch / arm / mach-davinci / board-mityomapl138.c
blob6efc84cceca093eff0299da9ddfae3b666c1eadd
1 /*
2 * Critical Link MityOMAP-L138 SoM
4 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/platform_device.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/regulator/machine.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h>
19 #include <linux/etherdevice.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/flash.h>
23 #include <asm/io.h>
24 #include <asm/mach-types.h>
25 #include <asm/mach/arch.h>
26 #include <mach/common.h>
27 #include <mach/cp_intc.h>
28 #include <mach/da8xx.h>
29 #include <mach/nand.h>
30 #include <mach/mux.h>
31 #include <mach/spi.h>
33 #define MITYOMAPL138_PHY_ID ""
35 #define FACTORY_CONFIG_MAGIC 0x012C0138
36 #define FACTORY_CONFIG_VERSION 0x00010001
38 /* Data Held in On-Board I2C device */
39 struct factory_config {
40 u32 magic;
41 u32 version;
42 u8 mac[6];
43 u32 fpga_type;
44 u32 spare;
45 u32 serialnumber;
46 char partnum[32];
49 static struct factory_config factory_config;
51 struct part_no_info {
52 const char *part_no; /* part number string of interest */
53 int max_freq; /* khz */
56 static struct part_no_info mityomapl138_pn_info[] = {
58 .part_no = "L138-C",
59 .max_freq = 300000,
62 .part_no = "L138-D",
63 .max_freq = 375000,
66 .part_no = "L138-F",
67 .max_freq = 456000,
70 .part_no = "1808-C",
71 .max_freq = 300000,
74 .part_no = "1808-D",
75 .max_freq = 375000,
78 .part_no = "1808-F",
79 .max_freq = 456000,
82 .part_no = "1810-D",
83 .max_freq = 375000,
87 #ifdef CONFIG_CPU_FREQ
88 static void mityomapl138_cpufreq_init(const char *partnum)
90 int i, ret;
92 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
94 * the part number has additional characters beyond what is
95 * stored in the table. This information is not needed for
96 * determining the speed grade, and would require several
97 * more table entries. Only check the first N characters
98 * for a match.
100 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
101 strlen(mityomapl138_pn_info[i].part_no))) {
102 da850_max_speed = mityomapl138_pn_info[i].max_freq;
103 break;
107 ret = da850_register_cpufreq("pll0_sysclk3");
108 if (ret)
109 pr_warning("cpufreq registration failed: %d\n", ret);
111 #else
112 static void mityomapl138_cpufreq_init(const char *partnum) { }
113 #endif
115 static void read_factory_config(struct memory_accessor *a, void *context)
117 int ret;
118 const char *partnum = NULL;
119 struct davinci_soc_info *soc_info = &davinci_soc_info;
121 ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
122 if (ret != sizeof(struct factory_config)) {
123 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
124 ret);
125 goto bad_config;
128 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
129 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
130 factory_config.magic);
131 goto bad_config;
134 if (factory_config.version != FACTORY_CONFIG_VERSION) {
135 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
136 factory_config.version);
137 goto bad_config;
140 pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
141 if (is_valid_ether_addr(factory_config.mac))
142 memcpy(soc_info->emac_pdata->mac_addr,
143 factory_config.mac, ETH_ALEN);
144 else
145 pr_warning("MityOMAPL138: Invalid MAC found "
146 "in factory config block\n");
148 partnum = factory_config.partnum;
149 pr_info("MityOMAPL138: Part Number = %s\n", partnum);
151 bad_config:
152 /* default maximum speed is valid for all platforms */
153 mityomapl138_cpufreq_init(partnum);
156 static struct at24_platform_data mityomapl138_fd_chip = {
157 .byte_len = 256,
158 .page_size = 8,
159 .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
160 .setup = read_factory_config,
161 .context = NULL,
164 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
165 .bus_freq = 100, /* kHz */
166 .bus_delay = 0, /* usec */
169 /* TPS65023 voltage regulator support */
170 /* 1.2V Core */
171 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
173 .supply = "cvdd",
177 /* 1.8V */
178 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
180 .supply = "usb0_vdda18",
183 .supply = "usb1_vdda18",
186 .supply = "ddr_dvdd18",
189 .supply = "sata_vddr",
193 /* 1.2V */
194 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
196 .supply = "sata_vdd",
199 .supply = "usb_cvdd",
202 .supply = "pll0_vdda",
205 .supply = "pll1_vdda",
209 /* 1.8V Aux LDO, not used */
210 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
212 .supply = "1.8v_aux",
216 /* FPGA VCC Aux (2.5 or 3.3) LDO */
217 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
219 .supply = "vccaux",
223 static struct regulator_init_data tps65023_regulator_data[] = {
224 /* dcdc1 */
226 .constraints = {
227 .min_uV = 1150000,
228 .max_uV = 1350000,
229 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
230 REGULATOR_CHANGE_STATUS,
231 .boot_on = 1,
233 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
234 .consumer_supplies = tps65023_dcdc1_consumers,
236 /* dcdc2 */
238 .constraints = {
239 .min_uV = 1800000,
240 .max_uV = 1800000,
241 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
242 .boot_on = 1,
244 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
245 .consumer_supplies = tps65023_dcdc2_consumers,
247 /* dcdc3 */
249 .constraints = {
250 .min_uV = 1200000,
251 .max_uV = 1200000,
252 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
253 .boot_on = 1,
255 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
256 .consumer_supplies = tps65023_dcdc3_consumers,
258 /* ldo1 */
260 .constraints = {
261 .min_uV = 1800000,
262 .max_uV = 1800000,
263 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
264 .boot_on = 1,
266 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
267 .consumer_supplies = tps65023_ldo1_consumers,
269 /* ldo2 */
271 .constraints = {
272 .min_uV = 2500000,
273 .max_uV = 3300000,
274 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
275 REGULATOR_CHANGE_STATUS,
276 .boot_on = 1,
278 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
279 .consumer_supplies = tps65023_ldo2_consumers,
283 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
285 I2C_BOARD_INFO("tps65023", 0x48),
286 .platform_data = &tps65023_regulator_data[0],
289 I2C_BOARD_INFO("24c02", 0x50),
290 .platform_data = &mityomapl138_fd_chip,
294 static int __init pmic_tps65023_init(void)
296 return i2c_register_board_info(1, mityomap_tps65023_info,
297 ARRAY_SIZE(mityomap_tps65023_info));
301 * SPI Devices:
302 * SPI1_CS0: 8M Flash ST-M25P64-VME6G
304 static struct mtd_partition spi_flash_partitions[] = {
305 [0] = {
306 .name = "ubl",
307 .offset = 0,
308 .size = SZ_64K,
309 .mask_flags = MTD_WRITEABLE,
311 [1] = {
312 .name = "u-boot",
313 .offset = MTDPART_OFS_APPEND,
314 .size = SZ_512K,
315 .mask_flags = MTD_WRITEABLE,
317 [2] = {
318 .name = "u-boot-env",
319 .offset = MTDPART_OFS_APPEND,
320 .size = SZ_64K,
321 .mask_flags = MTD_WRITEABLE,
323 [3] = {
324 .name = "periph-config",
325 .offset = MTDPART_OFS_APPEND,
326 .size = SZ_64K,
327 .mask_flags = MTD_WRITEABLE,
329 [4] = {
330 .name = "reserved",
331 .offset = MTDPART_OFS_APPEND,
332 .size = SZ_256K + SZ_64K,
334 [5] = {
335 .name = "kernel",
336 .offset = MTDPART_OFS_APPEND,
337 .size = SZ_2M + SZ_1M,
339 [6] = {
340 .name = "fpga",
341 .offset = MTDPART_OFS_APPEND,
342 .size = SZ_2M,
344 [7] = {
345 .name = "spare",
346 .offset = MTDPART_OFS_APPEND,
347 .size = MTDPART_SIZ_FULL,
351 static struct flash_platform_data mityomapl138_spi_flash_data = {
352 .name = "m25p80",
353 .parts = spi_flash_partitions,
354 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
355 .type = "m24p64",
358 static struct davinci_spi_config spi_eprom_config = {
359 .io_type = SPI_IO_TYPE_DMA,
360 .c2tdelay = 8,
361 .t2cdelay = 8,
364 static struct spi_board_info mityomapl138_spi_flash_info[] = {
366 .modalias = "m25p80",
367 .platform_data = &mityomapl138_spi_flash_data,
368 .controller_data = &spi_eprom_config,
369 .mode = SPI_MODE_0,
370 .max_speed_hz = 30000000,
371 .bus_num = 1,
372 .chip_select = 0,
377 * MityDSP-L138 includes a 256 MByte large-page NAND flash
378 * (128K blocks).
380 static struct mtd_partition mityomapl138_nandflash_partition[] = {
382 .name = "rootfs",
383 .offset = 0,
384 .size = SZ_128M,
385 .mask_flags = 0, /* MTD_WRITEABLE, */
388 .name = "homefs",
389 .offset = MTDPART_OFS_APPEND,
390 .size = MTDPART_SIZ_FULL,
391 .mask_flags = 0,
395 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
396 .parts = mityomapl138_nandflash_partition,
397 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
398 .ecc_mode = NAND_ECC_HW,
399 .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
400 .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
403 static struct resource mityomapl138_nandflash_resource[] = {
405 .start = DA8XX_AEMIF_CS3_BASE,
406 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
407 .flags = IORESOURCE_MEM,
410 .start = DA8XX_AEMIF_CTL_BASE,
411 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
412 .flags = IORESOURCE_MEM,
416 static struct platform_device mityomapl138_nandflash_device = {
417 .name = "davinci_nand",
418 .id = 1,
419 .dev = {
420 .platform_data = &mityomapl138_nandflash_data,
422 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
423 .resource = mityomapl138_nandflash_resource,
426 static struct platform_device *mityomapl138_devices[] __initdata = {
427 &mityomapl138_nandflash_device,
430 static void __init mityomapl138_setup_nand(void)
432 platform_add_devices(mityomapl138_devices,
433 ARRAY_SIZE(mityomapl138_devices));
436 static struct davinci_uart_config mityomapl138_uart_config __initdata = {
437 .enabled_uarts = 0x7,
440 static const short mityomap_mii_pins[] = {
441 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
442 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
443 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
444 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
445 DA850_MDIO_D,
449 static const short mityomap_rmii_pins[] = {
450 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
451 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
452 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
453 DA850_MDIO_D,
457 static void __init mityomapl138_config_emac(void)
459 void __iomem *cfg_chip3_base;
460 int ret;
461 u32 val;
462 struct davinci_soc_info *soc_info = &davinci_soc_info;
464 soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
466 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
467 val = __raw_readl(cfg_chip3_base);
469 if (soc_info->emac_pdata->rmii_en) {
470 val |= BIT(8);
471 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
472 pr_info("RMII PHY configured\n");
473 } else {
474 val &= ~BIT(8);
475 ret = davinci_cfg_reg_list(mityomap_mii_pins);
476 pr_info("MII PHY configured\n");
479 if (ret) {
480 pr_warning("mii/rmii mux setup failed: %d\n", ret);
481 return;
484 /* configure the CFGCHIP3 register for RMII or MII */
485 __raw_writel(val, cfg_chip3_base);
487 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
489 ret = da8xx_register_emac();
490 if (ret)
491 pr_warning("emac registration failed: %d\n", ret);
494 static struct davinci_pm_config da850_pm_pdata = {
495 .sleepcount = 128,
498 static struct platform_device da850_pm_device = {
499 .name = "pm-davinci",
500 .dev = {
501 .platform_data = &da850_pm_pdata,
503 .id = -1,
506 static void __init mityomapl138_init(void)
508 int ret;
510 /* for now, no special EDMA channels are reserved */
511 ret = da850_register_edma(NULL);
512 if (ret)
513 pr_warning("edma registration failed: %d\n", ret);
515 ret = da8xx_register_watchdog();
516 if (ret)
517 pr_warning("watchdog registration failed: %d\n", ret);
519 davinci_serial_init(&mityomapl138_uart_config);
521 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
522 if (ret)
523 pr_warning("i2c0 registration failed: %d\n", ret);
525 ret = pmic_tps65023_init();
526 if (ret)
527 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
529 mityomapl138_setup_nand();
531 ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
532 ARRAY_SIZE(mityomapl138_spi_flash_info));
533 if (ret)
534 pr_warning("spi 1 registration failed: %d\n", ret);
536 mityomapl138_config_emac();
538 ret = da8xx_register_rtc();
539 if (ret)
540 pr_warning("rtc setup failed: %d\n", ret);
542 ret = da8xx_register_cpuidle();
543 if (ret)
544 pr_warning("cpuidle registration failed: %d\n", ret);
546 ret = da850_register_pm(&da850_pm_device);
547 if (ret)
548 pr_warning("da850_evm_init: suspend registration failed: %d\n",
549 ret);
552 #ifdef CONFIG_SERIAL_8250_CONSOLE
553 static int __init mityomapl138_console_init(void)
555 if (!machine_is_mityomapl138())
556 return 0;
558 return add_preferred_console("ttyS", 1, "115200");
560 console_initcall(mityomapl138_console_init);
561 #endif
563 static void __init mityomapl138_map_io(void)
565 da850_init();
568 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
569 .atag_offset = 0x100,
570 .map_io = mityomapl138_map_io,
571 .init_irq = cp_intc_init,
572 .timer = &davinci_timer,
573 .init_machine = mityomapl138_init,
574 .dma_zone_size = SZ_128M,
575 MACHINE_END