arch/arm/mach-exynos4/clock-exynos4212.c

   1 /*
   2  * linux/arch/arm/mach-exynos4/clock-exynos4212.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4212 - Clock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <plat/cpu-freq.h>
  21 #include <plat/clock.h>
  22 #include <plat/cpu.h>
  23 #include <plat/pll.h>
  24 #include <plat/s5p-clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/exynos4.h>
  27 #include <plat/pm.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/map.h>
  31 #include <mach/regs-clock.h>
  32 #include <mach/exynos4-clock.h>
  33
  34 static struct sleep_save exynos4212_clock_save[] = {
  35         SAVE_ITEM(S5P_CLKSRC_IMAGE),
  36         SAVE_ITEM(S5P_CLKDIV_IMAGE),
  37         SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
  38         SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
  39 };
  40
  41 static struct clk *clk_src_mpll_user_list[] = {
  42         [0] = &clk_fin_mpll,
  43         [1] = &clk_mout_mpll.clk,
  44 };
  45
  46 static struct clksrc_sources clk_src_mpll_user = {
  47         .sources        = clk_src_mpll_user_list,
  48         .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
  49 };
  50
  51 static struct clksrc_clk clk_mout_mpll_user = {
  52         .clk = {
  53                 .name           = "mout_mpll_user",
  54         },
  55         .sources        = &clk_src_mpll_user,
  56         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
  57 };
  58
  59 static struct clksrc_clk *sysclks[] = {
  60         &clk_mout_mpll_user,
  61 };
  62
  63 static struct clksrc_clk clksrcs[] = {
  64         /* nothing here yet */
  65 };
  66
  67 static struct clk init_clocks_off[] = {
  68         /* nothing here yet */
  69 };
  70
  71 #ifdef CONFIG_PM_SLEEP
  72 static int exynos4212_clock_suspend(void)
  73 {
  74         s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
  75
  76         return 0;
  77 }
  78
  79 static void exynos4212_clock_resume(void)
  80 {
  81         s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
  82 }
  83
  84 #else
  85 #define exynos4212_clock_suspend NULL
  86 #define exynos4212_clock_resume NULL
  87 #endif
  88
  89 struct syscore_ops exynos4212_clock_syscore_ops = {
  90         .suspend        = exynos4212_clock_suspend,
  91         .resume         = exynos4212_clock_resume,
  92 };
  93
  94 void __init exynos4212_register_clocks(void)
  95 {
  96         int ptr;
  97
  98         /* usbphy1 is removed */
  99         clkset_group_list[4] = NULL;
 100
 101         /* mout_mpll_user is used */
 102         clkset_group_list[6] = &clk_mout_mpll_user.clk;
 103         clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 104
 105         clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
 106         clk_mout_mpll.reg_src.shift = 12;
 107         clk_mout_mpll.reg_src.size = 1;
 108
 109         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 110                 s3c_register_clksrc(sysclks[ptr], 1);
 111
 112         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 113
 114         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 115         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 116
 117         register_syscore_ops(&exynos4212_clock_syscore_ops);
 118 }