arch/arm/mach-ks8695/include/mach/regs-mem.h

   1 /*
   2  * arch/arm/mach-ks8695/include/mach/regs-mem.h
   3  *
   4  * Copyright (C) 2006 Andrew Victor
   5  *
   6  * KS8695 - Memory Controller registers and bit definitions
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #ifndef KS8695_MEM_H
  14 #define KS8695_MEM_H
  15
  16 #define KS8695_MEM_OFFSET       (0xF0000 + 0x4000)
  17 #define KS8695_MEM_VA           (KS8695_IO_VA + KS8695_MEM_OFFSET)
  18 #define KS8695_MEM_PA           (KS8695_IO_PA + KS8695_MEM_OFFSET)
  19
  20
  21 /*
  22  * Memory Controller Registers
  23  */
  24 #define KS8695_EXTACON0         (0x00)          /* External I/O 0 Access Control */
  25 #define KS8695_EXTACON1         (0x04)          /* External I/O 1 Access Control */
  26 #define KS8695_EXTACON2         (0x08)          /* External I/O 2 Access Control */
  27 #define KS8695_ROMCON0          (0x10)          /* ROM/SRAM/Flash 1 Control Register */
  28 #define KS8695_ROMCON1          (0x14)          /* ROM/SRAM/Flash 2 Control Register */
  29 #define KS8695_ERGCON           (0x20)          /* External I/O and ROM/SRAM/Flash General Register */
  30 #define KS8695_SDCON0           (0x30)          /* SDRAM Control Register 0 */
  31 #define KS8695_SDCON1           (0x34)          /* SDRAM Control Register 1 */
  32 #define KS8695_SDGCON           (0x38)          /* SDRAM General Control */
  33 #define KS8695_SDBCON           (0x3c)          /* SDRAM Buffer Control */
  34 #define KS8695_REFTIM           (0x40)          /* SDRAM Refresh Timer */
  35
  36
  37 /* External I/O Access Control Registers */
  38 #define EXTACON_EBNPTR          (0x3ff << 22)           /* Last Address Pointer */
  39 #define EXTACON_EBBPTR          (0x3ff << 12)           /* Base Pointer */
  40 #define EXTACON_EBTACT          (7     <<  9)           /* Write Enable/Output Enable Active Time */
  41 #define EXTACON_EBTCOH          (7     <<  6)           /* Chip Select Hold Time */
  42 #define EXTACON_EBTACS          (7     <<  3)           /* Address Setup Time before ECSN */
  43 #define EXTACON_EBTCOS          (7     <<  0)           /* Chip Select Time before OEN */
  44
  45 /* ROM/SRAM/Flash Control Register */
  46 #define ROMCON_RBNPTR           (0x3ff << 22)           /* Next Pointer */
  47 #define ROMCON_RBBPTR           (0x3ff << 12)           /* Base Pointer */
  48 #define ROMCON_RBTACC           (7     <<  4)           /* Access Cycle Time */
  49 #define ROMCON_RBTPA            (3     <<  2)           /* Page Address Access Time */
  50 #define ROMCON_PMC              (3     <<  0)           /* Page Mode Configuration */
  51 #define         PMC_NORMAL              (0 << 0)
  52 #define         PMC_4WORD               (1 << 0)
  53 #define         PMC_8WORD               (2 << 0)
  54 #define         PMC_16WORD              (3 << 0)
  55
  56 /* External I/O and ROM/SRAM/Flash General Register */
  57 #define ERGCON_TMULT            (3 << 28)               /* Time Multiplier */
  58 #define ERGCON_DSX2             (3 << 20)               /* Data Width (External I/O Bank 2) */
  59 #define ERGCON_DSX1             (3 << 18)               /* Data Width (External I/O Bank 1) */
  60 #define ERGCON_DSX0             (3 << 16)               /* Data Width (External I/O Bank 0) */
  61 #define ERGCON_DSR1             (3 <<  2)               /* Data Width (ROM/SRAM/Flash Bank 1) */
  62 #define ERGCON_DSR0             (3 <<  0)               /* Data Width (ROM/SRAM/Flash Bank 0) */
  63
  64 /* SDRAM Control Register */
  65 #define SDCON_DBNPTR            (0x3ff << 22)           /* Last Address Pointer */
  66 #define SDCON_DBBPTR            (0x3ff << 12)           /* Base Pointer */
  67 #define SDCON_DBCAB             (3     <<  8)           /* Column Address Bits */
  68 #define SDCON_DBBNUM            (1     <<  3)           /* Number of Banks */
  69 #define SDCON_DBDBW             (3     <<  1)           /* Data Bus Width */
  70
  71 /* SDRAM General Control Register */
  72 #define SDGCON_SDTRC            (3 << 2)                /* RAS to CAS latency */
  73 #define SDGCON_SDCAS            (3 << 0)                /* CAS latency */
  74
  75 /* SDRAM Buffer Control Register */
  76 #define SDBCON_SDESTA           (1 << 31)               /* SDRAM Engine Status */
  77 #define SDBCON_RBUFBDIS         (1 << 24)               /* Read Buffer Burst Enable */
  78 #define SDBCON_WFIFOEN          (1 << 23)               /* Write FIFO Enable */
  79 #define SDBCON_RBUFEN           (1 << 22)               /* Read Buffer Enable */
  80 #define SDBCON_FLUSHWFIFO       (1 << 21)               /* Flush Write FIFO */
  81 #define SDBCON_RBUFINV          (1 << 20)               /* Read Buffer Invalidate */
  82 #define SDBCON_SDINI            (3 << 16)               /* SDRAM Initialization Control */
  83 #define SDBCON_SDMODE           (0x3fff << 0)           /* SDRAM Mode Register Value Program */
  84
  85 /* SDRAM Refresh Timer Register */
  86 #define REFTIM_REFTIM           (0xffff << 0)           /* Refresh Timer Value */
  87
  88
  89 #endif