MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / arch / arm / mach-ks8695 / include / mach / regs-misc.h
blob2740c52494a0923554a0d6207510eca5841c1af9
1 /*
2 * arch/arm/mach-ks8695/include/mach/regs-misc.h
4 * Copyright (C) 2006 Andrew Victor
6 * KS8695 - Miscellaneous Registers
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #ifndef KS8695_MISC_H
14 #define KS8695_MISC_H
16 #define KS8695_MISC_OFFSET (0xF0000 + 0xEA00)
17 #define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET)
18 #define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET)
22 * Miscellaneous registers
24 #define KS8695_DID (0x00) /* Device ID */
25 #define KS8695_RID (0x04) /* Revision ID */
26 #define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */
27 #define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */
28 #define KS8695_WPPM (0x10) /* WAN PHY Power Management */
29 #define KS8695_PPS (0x1c) /* PHY PowerSave */
31 /* Device ID Register */
32 #define DID_ID (0xffff << 0) /* Device ID */
34 /* Revision ID Register */
35 #define RID_SUBID (0xf << 4) /* Sub-Device ID */
36 #define RID_REVISION (0xf << 0) /* Revision ID */
38 /* HPNA Miscellaneous Control Register */
39 #define HMC_HSS (1 << 1) /* Speed */
40 #define HMC_HDS (1 << 0) /* Duplex */
42 /* WAN Miscellaneous Control Register */
43 #define WMC_WANC (1 << 30) /* Auto-negotiation complete */
44 #define WMC_WANR (1 << 29) /* Auto-negotiation restart */
45 #define WMC_WANAP (1 << 28) /* Advertise Pause */
46 #define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */
47 #define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */
48 #define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */
49 #define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */
50 #define WMC_WLS (1 << 23) /* Link status */
51 #define WMC_WDS (1 << 22) /* Duplex status */
52 #define WMC_WSS (1 << 21) /* Speed status */
53 #define WMC_WLPP (1 << 20) /* Link Partner Pause */
54 #define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */
55 #define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */
56 #define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */
57 #define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */
58 #define WMC_WAND (1 << 15) /* Auto-negotiation disable */
59 #define WMC_WANF100 (1 << 14) /* Force 100 */
60 #define WMC_WANFF (1 << 13) /* Force FDX */
61 #define WMC_WLED1S (7 << 4) /* LED1 Select */
62 #define WLED1S_SPEED (0 << 4)
63 #define WLED1S_LINK (1 << 4)
64 #define WLED1S_DUPLEX (2 << 4)
65 #define WLED1S_COLLISION (3 << 4)
66 #define WLED1S_ACTIVITY (4 << 4)
67 #define WLED1S_FDX_COLLISION (5 << 4)
68 #define WLED1S_LINK_ACTIVITY (6 << 4)
69 #define WMC_WLED0S (7 << 0) /* LED0 Select */
70 #define WLED0S_SPEED (0 << 0)
71 #define WLED0S_LINK (1 << 0)
72 #define WLED0S_DUPLEX (2 << 0)
73 #define WLED0S_COLLISION (3 << 0)
74 #define WLED0S_ACTIVITY (4 << 0)
75 #define WLED0S_FDX_COLLISION (5 << 0)
76 #define WLED0S_LINK_ACTIVITY (6 << 0)
78 /* WAN PHY Power Management Register */
79 #define WPPM_WLPBK (1 << 14) /* Local Loopback */
80 #define WPPM_WRLPKB (1 << 13) /* Remove Loopback */
81 #define WPPM_WPI (1 << 12) /* PHY isolate */
82 #define WPPM_WFL (1 << 10) /* Force link */
83 #define WPPM_MDIXS (1 << 9) /* MDIX Status */
84 #define WPPM_FEF (1 << 8) /* Far End Fault */
85 #define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */
86 #define WPPM_TXDIS (1 << 6) /* Disable transmitter */
87 #define WPPM_DFEF (1 << 5) /* Disable Far End Fault */
88 #define WPPM_PD (1 << 4) /* Power Down */
89 #define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */
90 #define WPPM_FMDX (1 << 2) /* Force MDIX */
91 #define WPPM_LPBK (1 << 1) /* MAX Loopback */
93 /* PHY Power Save Register */
94 #define PPS_PPSM (1 << 0) /* PHY Power Save Mode */
97 #endif