arch/arm/mach-lpc32xx/common.c

   1 /*
   2  * arch/arm/mach-lpc32xx/common.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/err.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-pnx.h>
  26 #include <linux/io.h>
  27
  28 #include <asm/mach/map.h>
  29
  30 #include <mach/i2c.h>
  31 #include <mach/hardware.h>
  32 #include <mach/platform.h>
  33 #include "common.h"
  34
  35 /*
  36  * Watchdog timer
  37  */
  38 static struct resource watchdog_resources[] = {
  39         [0] = {
  40                 .start = LPC32XX_WDTIM_BASE,
  41                 .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
  42                 .flags = IORESOURCE_MEM,
  43         },
  44 };
  45
  46 struct platform_device lpc32xx_watchdog_device = {
  47         .name = "pnx4008-watchdog",
  48         .id = -1,
  49         .num_resources = ARRAY_SIZE(watchdog_resources),
  50         .resource = watchdog_resources,
  51 };
  52
  53 /*
  54  * I2C busses
  55  */
  56 static struct i2c_pnx_data i2c0_data = {
  57         .name = I2C_CHIP_NAME "1",
  58         .base = LPC32XX_I2C1_BASE,
  59         .irq = IRQ_LPC32XX_I2C_1,
  60 };
  61
  62 static struct i2c_pnx_data i2c1_data = {
  63         .name = I2C_CHIP_NAME "2",
  64         .base = LPC32XX_I2C2_BASE,
  65         .irq = IRQ_LPC32XX_I2C_2,
  66 };
  67
  68 static struct i2c_pnx_data i2c2_data = {
  69         .name = "USB-I2C",
  70         .base = LPC32XX_OTG_I2C_BASE,
  71         .irq = IRQ_LPC32XX_USB_I2C,
  72 };
  73
  74 struct platform_device lpc32xx_i2c0_device = {
  75         .name = "pnx-i2c",
  76         .id = 0,
  77         .dev = {
  78                 .platform_data = &i2c0_data,
  79         },
  80 };
  81
  82 struct platform_device lpc32xx_i2c1_device = {
  83         .name = "pnx-i2c",
  84         .id = 1,
  85         .dev = {
  86                 .platform_data = &i2c1_data,
  87         },
  88 };
  89
  90 struct platform_device lpc32xx_i2c2_device = {
  91         .name = "pnx-i2c",
  92         .id = 2,
  93         .dev = {
  94                 .platform_data = &i2c2_data,
  95         },
  96 };
  97
  98 /* TSC (Touch Screen Controller) */
  99
 100 static struct resource lpc32xx_tsc_resources[] = {
 101         {
 102                 .start = LPC32XX_ADC_BASE,
 103                 .end = LPC32XX_ADC_BASE + SZ_4K - 1,
 104                 .flags = IORESOURCE_MEM,
 105         }, {
 106                 .start = IRQ_LPC32XX_TS_IRQ,
 107                 .end = IRQ_LPC32XX_TS_IRQ,
 108                 .flags = IORESOURCE_IRQ,
 109         },
 110 };
 111
 112 struct platform_device lpc32xx_tsc_device = {
 113         .name =  "ts-lpc32xx",
 114         .id = -1,
 115         .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
 116         .resource = lpc32xx_tsc_resources,
 117 };
 118
 119 /* RTC */
 120
 121 static struct resource lpc32xx_rtc_resources[] = {
 122         {
 123                 .start = LPC32XX_RTC_BASE,
 124                 .end = LPC32XX_RTC_BASE + SZ_4K - 1,
 125                 .flags = IORESOURCE_MEM,
 126         },{
 127                 .start = IRQ_LPC32XX_RTC,
 128                 .end = IRQ_LPC32XX_RTC,
 129                 .flags = IORESOURCE_IRQ,
 130         },
 131 };
 132
 133 struct platform_device lpc32xx_rtc_device = {
 134         .name =  "rtc-lpc32xx",
 135         .id = -1,
 136         .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
 137         .resource = lpc32xx_rtc_resources,
 138 };
 139
 140 /*
 141  * Returns the unique ID for the device
 142  */
 143 void lpc32xx_get_uid(u32 devid[4])
 144 {
 145         int i;
 146
 147         for (i = 0; i < 4; i++)
 148                 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
 149 }
 150
 151 /*
 152  * Returns SYSCLK source
 153  * 0 = PLL397, 1 = main oscillator
 154  */
 155 int clk_is_sysclk_mainosc(void)
 156 {
 157         if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
 158                 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
 159                 return 1;
 160
 161         return 0;
 162 }
 163
 164 /*
 165  * System reset via the watchdog timer
 166  */
 167 void lpc32xx_watchdog_reset(void)
 168 {
 169         /* Make sure WDT clocks are enabled */
 170         __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
 171                 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
 172
 173         /* Instant assert of RESETOUT_N with pulse length 1mS */
 174         __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
 175         __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
 176 }
 177
 178 /*
 179  * Detects and returns IRAM size for the device variation
 180  */
 181 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
 182 static u32 iram_size;
 183 u32 lpc32xx_return_iram_size(void)
 184 {
 185         if (iram_size == 0) {
 186                 u32 savedval1, savedval2;
 187                 void __iomem *iramptr1, *iramptr2;
 188
 189                 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
 190                 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
 191                 savedval1 = __raw_readl(iramptr1);
 192                 savedval2 = __raw_readl(iramptr2);
 193
 194                 if (savedval1 == savedval2) {
 195                         __raw_writel(savedval2 + 1, iramptr2);
 196                         if (__raw_readl(iramptr1) == savedval2 + 1)
 197                                 iram_size = LPC32XX_IRAM_BANK_SIZE;
 198                         else
 199                                 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
 200                         __raw_writel(savedval2, iramptr2);
 201                 } else
 202                         iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
 203         }
 204
 205         return iram_size;
 206 }
 207
 208 /*
 209  * Computes PLL rate from PLL register and input clock
 210  */
 211 u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
 212 {
 213         u32 ilfreq, p, m, n, fcco, fref, cfreq;
 214         int mode;
 215
 216         /*
 217          * PLL requirements
 218          * ifreq must be >= 1MHz and <= 20MHz
 219          * FCCO must be >= 156MHz and <= 320MHz
 220          * FREF must be >= 1MHz and <= 27MHz
 221          * Assume the passed input data is not valid
 222          */
 223
 224         ilfreq = ifreq;
 225         m = pllsetup->pll_m;
 226         n = pllsetup->pll_n;
 227         p = pllsetup->pll_p;
 228
 229         mode = (pllsetup->cco_bypass_b15 << 2) |
 230                 (pllsetup->direct_output_b14 << 1) |
 231         pllsetup->fdbk_div_ctrl_b13;
 232
 233         switch (mode) {
 234         case 0x0: /* Non-integer mode */
 235                 cfreq = (m * ilfreq) / (2 * p * n);
 236                 fcco = (m * ilfreq) / n;
 237                 fref = ilfreq / n;
 238                 break;
 239
 240         case 0x1: /* integer mode */
 241                 cfreq = (m * ilfreq) / n;
 242                 fcco = (m * ilfreq) / (n * 2 * p);
 243                 fref = ilfreq / n;
 244                 break;
 245
 246         case 0x2:
 247         case 0x3: /* Direct mode */
 248                 cfreq = (m * ilfreq) / n;
 249                 fcco = cfreq;
 250                 fref = ilfreq / n;
 251                 break;
 252
 253         case 0x4:
 254         case 0x5: /* Bypass mode */
 255                 cfreq = ilfreq / (2 * p);
 256                 fcco = 156000000;
 257                 fref = 1000000;
 258                 break;
 259
 260         case 0x6:
 261         case 0x7: /* Direct bypass mode */
 262         default:
 263                 cfreq = ilfreq;
 264                 fcco = 156000000;
 265                 fref = 1000000;
 266                 break;
 267         }
 268
 269         if (fcco < 156000000 || fcco > 320000000)
 270                 cfreq = 0;
 271
 272         if (fref < 1000000 || fref > 27000000)
 273                 cfreq = 0;
 274
 275         return (u32) cfreq;
 276 }
 277
 278 u32 clk_get_pclk_div(void)
 279 {
 280         return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
 281 }
 282
 283 static struct map_desc lpc32xx_io_desc[] __initdata = {
 284         {
 285                 .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
 286                 .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
 287                 .length         = LPC32XX_AHB0_SIZE,
 288                 .type           = MT_DEVICE
 289         },
 290         {
 291                 .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
 292                 .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
 293                 .length         = LPC32XX_AHB1_SIZE,
 294                 .type           = MT_DEVICE
 295         },
 296         {
 297                 .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
 298                 .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
 299                 .length         = LPC32XX_FABAPB_SIZE,
 300                 .type           = MT_DEVICE
 301         },
 302         {
 303                 .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
 304                 .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
 305                 .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
 306                 .type           = MT_DEVICE
 307         },
 308 };
 309
 310 void __init lpc32xx_map_io(void)
 311 {
 312         iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 313 }