arch/arm/mach-mx5/board-cpuimx51.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/i2c.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25
  26 #include <mach/eukrea-baseboards.h>
  27 #include <mach/common.h>
  28 #include <mach/hardware.h>
  29 #include <mach/iomux-mx51.h>
  30
  31 #include <asm/setup.h>
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/time.h>
  35
  36 #include "devices-imx51.h"
  37
  38 #define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
  39 #define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
  40 #define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
  41 #define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
  42 #define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
  43 #define CPUIMX51_QUART_XTAL     14745600
  44 #define CPUIMX51_QUART_REGSHIFT 17
  45
  46 /* USB_CTRL_1 */
  47 #define MX51_USB_CTRL_1_OFFSET          0x10
  48 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  49
  50 #define MX51_USB_PLLDIV_12_MHZ          0x00
  51 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  52 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  53
  54 static struct plat_serial8250_port serial_platform_data[] = {
  55         {
  56                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
  57                 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
  58                 .irqflags = IRQF_TRIGGER_HIGH,
  59                 .uartclk = CPUIMX51_QUART_XTAL,
  60                 .regshift = CPUIMX51_QUART_REGSHIFT,
  61                 .iotype = UPIO_MEM,
  62                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  63         }, {
  64                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
  65                 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
  66                 .irqflags = IRQF_TRIGGER_HIGH,
  67                 .uartclk = CPUIMX51_QUART_XTAL,
  68                 .regshift = CPUIMX51_QUART_REGSHIFT,
  69                 .iotype = UPIO_MEM,
  70                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  71         }, {
  72                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
  73                 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
  74                 .irqflags = IRQF_TRIGGER_HIGH,
  75                 .uartclk = CPUIMX51_QUART_XTAL,
  76                 .regshift = CPUIMX51_QUART_REGSHIFT,
  77                 .iotype = UPIO_MEM,
  78                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  79         }, {
  80                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
  81                 .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
  82                 .irqflags = IRQF_TRIGGER_HIGH,
  83                 .uartclk = CPUIMX51_QUART_XTAL,
  84                 .regshift = CPUIMX51_QUART_REGSHIFT,
  85                 .iotype = UPIO_MEM,
  86                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  87         }, {
  88         }
  89 };
  90
  91 static struct platform_device serial_device = {
  92         .name = "serial8250",
  93         .id = 0,
  94         .dev = {
  95                 .platform_data = serial_platform_data,
  96         },
  97 };
  98
  99 static struct platform_device *devices[] __initdata = {
 100         &serial_device,
 101 };
 102
 103 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
 104         /* UART1 */
 105         MX51_PAD_UART1_RXD__UART1_RXD,
 106         MX51_PAD_UART1_TXD__UART1_TXD,
 107         MX51_PAD_UART1_RTS__UART1_RTS,
 108         MX51_PAD_UART1_CTS__UART1_CTS,
 109
 110         /* I2C2 */
 111         MX51_PAD_GPIO1_2__I2C2_SCL,
 112         MX51_PAD_GPIO1_3__I2C2_SDA,
 113         MX51_PAD_NANDF_D10__GPIO3_30,
 114
 115         /* QUART IRQ */
 116         MX51_PAD_NANDF_D15__GPIO3_25,
 117         MX51_PAD_NANDF_D14__GPIO3_26,
 118         MX51_PAD_NANDF_D13__GPIO3_27,
 119         MX51_PAD_NANDF_D12__GPIO3_28,
 120
 121         /* USB HOST1 */
 122         MX51_PAD_USBH1_CLK__USBH1_CLK,
 123         MX51_PAD_USBH1_DIR__USBH1_DIR,
 124         MX51_PAD_USBH1_NXT__USBH1_NXT,
 125         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 126         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 127         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 128         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 129         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 130         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 131         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 132         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 133         MX51_PAD_USBH1_STP__USBH1_STP,
 134 };
 135
 136 static const struct mxc_nand_platform_data
 137                 eukrea_cpuimx51_nand_board_info __initconst = {
 138         .width          = 1,
 139         .hw_ecc         = 1,
 140         .flash_bbt      = 1,
 141 };
 142
 143 static const struct imxuart_platform_data uart_pdata __initconst = {
 144         .flags = IMXUART_HAVE_RTSCTS,
 145 };
 146
 147 static const
 148 struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
 149         .bitrate = 100000,
 150 };
 151
 152 static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
 153         {
 154                 I2C_BOARD_INFO("pcf8563", 0x51),
 155         },
 156 };
 157
 158 /* This function is board specific as the bit mask for the plldiv will also
 159 be different for other Freescale SoCs, thus a common bitmask is not
 160 possible and cannot get place in /plat-mxc/ehci.c.*/
 161 static int initialize_otg_port(struct platform_device *pdev)
 162 {
 163         u32 v;
 164         void __iomem *usb_base;
 165         void __iomem *usbother_base;
 166
 167         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 168         if (!usb_base)
 169                 return -ENOMEM;
 170         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 171
 172         /* Set the PHY clock to 19.2MHz */
 173         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 174         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 175         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 176         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 177         iounmap(usb_base);
 178
 179         mdelay(10);
 180
 181         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 182 }
 183
 184 static int initialize_usbh1_port(struct platform_device *pdev)
 185 {
 186         u32 v;
 187         void __iomem *usb_base;
 188         void __iomem *usbother_base;
 189
 190         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 191         if (!usb_base)
 192                 return -ENOMEM;
 193         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 194
 195         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 196         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 197         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 198         iounmap(usb_base);
 199
 200         mdelay(10);
 201
 202         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 203                         MXC_EHCI_ITC_NO_THRESHOLD);
 204 }
 205
 206 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
 207         .init           = initialize_otg_port,
 208         .portsc = MXC_EHCI_UTMI_16BIT,
 209 };
 210
 211 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 212         .operating_mode = FSL_USB2_DR_DEVICE,
 213         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 214 };
 215
 216 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
 217         .init           = initialize_usbh1_port,
 218         .portsc = MXC_EHCI_MODE_ULPI,
 219 };
 220
 221 static int otg_mode_host;
 222
 223 static int __init eukrea_cpuimx51_otg_mode(char *options)
 224 {
 225         if (!strcmp(options, "host"))
 226                 otg_mode_host = 1;
 227         else if (!strcmp(options, "device"))
 228                 otg_mode_host = 0;
 229         else
 230                 pr_info("otg_mode neither \"host\" nor \"device\". "
 231                         "Defaulting to device\n");
 232         return 0;
 233 }
 234 __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
 235
 236 /*
 237  * Board specific initialization.
 238  */
 239 static void __init eukrea_cpuimx51_init(void)
 240 {
 241         imx51_soc_init();
 242
 243         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
 244                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 245
 246         imx51_add_imx_uart(0, &uart_pdata);
 247         imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
 248
 249         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
 250         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
 251         gpio_free(CPUIMX51_QUARTA_GPIO);
 252         gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
 253         gpio_direction_input(CPUIMX51_QUARTB_GPIO);
 254         gpio_free(CPUIMX51_QUARTB_GPIO);
 255         gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
 256         gpio_direction_input(CPUIMX51_QUARTC_GPIO);
 257         gpio_free(CPUIMX51_QUARTC_GPIO);
 258         gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
 259         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
 260         gpio_free(CPUIMX51_QUARTD_GPIO);
 261
 262         imx51_add_fec(NULL);
 263         platform_add_devices(devices, ARRAY_SIZE(devices));
 264
 265         imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
 266         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
 267                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 268
 269         if (otg_mode_host)
 270                 imx51_add_mxc_ehci_otg(&dr_utmi_config);
 271         else {
 272                 initialize_otg_port(NULL);
 273                 imx51_add_fsl_usb2_udc(&usb_pdata);
 274         }
 275         imx51_add_mxc_ehci_hs(1, &usbh1_config);
 276
 277 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
 278         eukrea_mbimx51_baseboard_init();
 279 #endif
 280 }
 281
 282 static void __init eukrea_cpuimx51_timer_init(void)
 283 {
 284         mx51_clocks_init(32768, 24000000, 22579200, 0);
 285 }
 286
 287 static struct sys_timer mxc_timer = {
 288         .init   = eukrea_cpuimx51_timer_init,
 289 };
 290
 291 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 292         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 293         .atag_offset = 0x100,
 294         .map_io = mx51_map_io,
 295         .init_early = imx51_init_early,
 296         .init_irq = mx51_init_irq,
 297         .handle_irq = imx51_handle_irq,
 298         .timer = &mxc_timer,
 299         .init_machine = eukrea_cpuimx51_init,
 300 MACHINE_END