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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / arch / arm / mach-tegra / tegra2_clocks.c
blob371869d8ea01f1c63a4125dc8cccd0a3022b577d
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra2_emc.h"
35
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
40
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
45
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
48
49 #define OSC_CTRL 0x50
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
59
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
76
77 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
78 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
79 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
80
81 #define PLL_BASE 0x0
82 #define PLL_BASE_BYPASS (1<<31)
83 #define PLL_BASE_ENABLE (1<<30)
84 #define PLL_BASE_REF_ENABLE (1<<29)
85 #define PLL_BASE_OVERRIDE (1<<28)
86 #define PLL_BASE_DIVP_MASK (0x7<<20)
87 #define PLL_BASE_DIVP_SHIFT 20
88 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
89 #define PLL_BASE_DIVN_SHIFT 8
90 #define PLL_BASE_DIVM_MASK (0x1F)
91 #define PLL_BASE_DIVM_SHIFT 0
92
93 #define PLL_OUT_RATIO_MASK (0xFF<<8)
94 #define PLL_OUT_RATIO_SHIFT 8
95 #define PLL_OUT_OVERRIDE (1<<2)
96 #define PLL_OUT_CLKEN (1<<1)
97 #define PLL_OUT_RESET_DISABLE (1<<0)
98
99 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
100
101 #define PLL_MISC_DCCON_SHIFT 20
102 #define PLL_MISC_CPCON_SHIFT 8
103 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
104 #define PLL_MISC_LFCON_SHIFT 4
105 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
106 #define PLL_MISC_VCOCON_SHIFT 0
107 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
108
109 #define PLLU_BASE_POST_DIV (1<<20)
110
111 #define PLLD_MISC_CLKENABLE (1<<30)
112 #define PLLD_MISC_DIV_RST (1<<23)
113 #define PLLD_MISC_DCCON_SHIFT 12
114
115 #define PLLE_MISC_READY (1 << 15)
116
117 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
118 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
119 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
120
121 #define SUPER_CLK_MUX 0x00
122 #define SUPER_STATE_SHIFT 28
123 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
129 #define SUPER_SOURCE_MASK 0xF
130 #define SUPER_FIQ_SOURCE_SHIFT 12
131 #define SUPER_IRQ_SOURCE_SHIFT 8
132 #define SUPER_RUN_SOURCE_SHIFT 4
133 #define SUPER_IDLE_SOURCE_SHIFT 0
134
135 #define SUPER_CLK_DIVIDER 0x04
136
137 #define BUS_CLK_DISABLE (1<<3)
138 #define BUS_CLK_DIV_MASK 0x3
139
140 #define PMC_CTRL 0x0
141 #define PMC_CTRL_BLINK_ENB (1 << 7)
142
143 #define PMC_DPD_PADS_ORIDE 0x1c
144 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
145
146 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
147 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
148 #define PMC_BLINK_TIMER_ENB (1 << 15)
149 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
150 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
151
152 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
153 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
154
155 /*
156 * Some clocks share a register with other clocks. Any clock op that
157 * non-atomically modifies a register used by another clock must lock
158 * clock_register_lock first.
159 */
160 static DEFINE_SPINLOCK(clock_register_lock);
161
162 /*
163 * Some peripheral clocks share an enable bit, so refcount the enable bits
164 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
165 */
166 static int tegra_periph_clk_enable_refcount[3 * 32];
167
168 #define clk_writel(value, reg) \
169 __raw_writel(value, reg_clk_base + (reg))
170 #define clk_readl(reg) \
171 __raw_readl(reg_clk_base + (reg))
172 #define pmc_writel(value, reg) \
173 __raw_writel(value, reg_pmc_base + (reg))
174 #define pmc_readl(reg) \
175 __raw_readl(reg_pmc_base + (reg))
176
177 unsigned long clk_measure_input_freq(void)
178 {
179 u32 clock_autodetect;
180 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
181 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
182 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
183 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
184 return 12000000;
185 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
186 return 13000000;
187 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
188 return 19200000;
189 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
190 return 26000000;
191 } else {
192 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
193 BUG();
194 return 0;
195 }
196 }
197
198 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
199 {
200 s64 divider_u71 = parent_rate * 2;
201 divider_u71 += rate - 1;
202 do_div(divider_u71, rate);
203
204 if (divider_u71 - 2 < 0)
205 return 0;
206
207 if (divider_u71 - 2 > 255)
208 return -EINVAL;
209
210 return divider_u71 - 2;
211 }
212
213 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
214 {
215 s64 divider_u16;
216
217 divider_u16 = parent_rate;
218 divider_u16 += rate - 1;
219 do_div(divider_u16, rate);
220
221 if (divider_u16 - 1 < 0)
222 return 0;
223
224 if (divider_u16 - 1 > 255)
225 return -EINVAL;
226
227 return divider_u16 - 1;
228 }
229
230 /* clk_m functions */
231 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
232 {
233 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
234
235 c->rate = clk_measure_input_freq();
236 switch (c->rate) {
237 case 12000000:
238 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
239 break;
240 case 13000000:
241 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
242 break;
243 case 19200000:
244 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
245 break;
246 case 26000000:
247 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
248 break;
249 default:
250 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
251 BUG();
252 }
253 clk_writel(auto_clock_control, OSC_CTRL);
254 return c->rate;
255 }
256
257 static void tegra2_clk_m_init(struct clk *c)
258 {
259 pr_debug("%s on clock %s\n", __func__, c->name);
260 tegra2_clk_m_autodetect_rate(c);
261 }
262
263 static int tegra2_clk_m_enable(struct clk *c)
264 {
265 pr_debug("%s on clock %s\n", __func__, c->name);
266 return 0;
267 }
268
269 static void tegra2_clk_m_disable(struct clk *c)
270 {
271 pr_debug("%s on clock %s\n", __func__, c->name);
272 BUG();
273 }
274
275 static struct clk_ops tegra_clk_m_ops = {
276 .init = tegra2_clk_m_init,
277 .enable = tegra2_clk_m_enable,
278 .disable = tegra2_clk_m_disable,
279 };
280
281 void tegra2_periph_reset_assert(struct clk *c)
282 {
283 BUG_ON(!c->ops->reset);
284 c->ops->reset(c, true);
285 }
286
287 void tegra2_periph_reset_deassert(struct clk *c)
288 {
289 BUG_ON(!c->ops->reset);
290 c->ops->reset(c, false);
291 }
292
293 /* super clock functions */
294 /* "super clocks" on tegra have two-stage muxes and a clock skipping
295 * super divider. We will ignore the clock skipping divider, since we
296 * can't lower the voltage when using the clock skip, but we can if we
297 * lower the PLL frequency.
298 */
299 static void tegra2_super_clk_init(struct clk *c)
300 {
301 u32 val;
302 int source;
303 int shift;
304 const struct clk_mux_sel *sel;
305 val = clk_readl(c->reg + SUPER_CLK_MUX);
306 c->state = ON;
307 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
308 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
309 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
310 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
311 source = (val >> shift) & SUPER_SOURCE_MASK;
312 for (sel = c->inputs; sel->input != NULL; sel++) {
313 if (sel->value == source)
314 break;
315 }
316 BUG_ON(sel->input == NULL);
317 c->parent = sel->input;
318 }
319
320 static int tegra2_super_clk_enable(struct clk *c)
321 {
322 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
323 return 0;
324 }
325
326 static void tegra2_super_clk_disable(struct clk *c)
327 {
328 pr_debug("%s on clock %s\n", __func__, c->name);
329
330 /* oops - don't disable the CPU clock! */
331 BUG();
332 }
333
334 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
335 {
336 u32 val;
337 const struct clk_mux_sel *sel;
338 int shift;
339
340 val = clk_readl(c->reg + SUPER_CLK_MUX);
341 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
342 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
343 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
344 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
345 for (sel = c->inputs; sel->input != NULL; sel++) {
346 if (sel->input == p) {
347 val &= ~(SUPER_SOURCE_MASK << shift);
348 val |= sel->value << shift;
349
350 if (c->refcnt)
351 clk_enable(p);
352
353 clk_writel(val, c->reg);
354
355 if (c->refcnt && c->parent)
356 clk_disable(c->parent);
357
358 clk_reparent(c, p);
359 return 0;
360 }
361 }
362 return -EINVAL;
363 }
364
365 /*
366 * Super clocks have "clock skippers" instead of dividers. Dividing using
367 * a clock skipper does not allow the voltage to be scaled down, so instead
368 * adjust the rate of the parent clock. This requires that the parent of a
369 * super clock have no other children, otherwise the rate will change
370 * underneath the other children.
371 */
372 static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
373 {
374 return clk_set_rate(c->parent, rate);
375 }
376
377 static struct clk_ops tegra_super_ops = {
378 .init = tegra2_super_clk_init,
379 .enable = tegra2_super_clk_enable,
380 .disable = tegra2_super_clk_disable,
381 .set_parent = tegra2_super_clk_set_parent,
382 .set_rate = tegra2_super_clk_set_rate,
383 };
384
385 /* virtual cpu clock functions */
386 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
387 To change the frequency of these clocks, the parent pll may need to be
388 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
389 and then the clock moved back to the pll. To hide this sequence, a virtual
390 clock handles it.
391 */
392 static void tegra2_cpu_clk_init(struct clk *c)
393 {
394 }
395
396 static int tegra2_cpu_clk_enable(struct clk *c)
397 {
398 return 0;
399 }
400
401 static void tegra2_cpu_clk_disable(struct clk *c)
402 {
403 pr_debug("%s on clock %s\n", __func__, c->name);
404
405 /* oops - don't disable the CPU clock! */
406 BUG();
407 }
408
409 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
410 {
411 int ret;
412 /*
413 * Take an extra reference to the main pll so it doesn't turn
414 * off when we move the cpu off of it
415 */
416 clk_enable(c->u.cpu.main);
417
418 ret = clk_set_parent(c->parent, c->u.cpu.backup);
419 if (ret) {
420 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
421 goto out;
422 }
423
424 if (rate == clk_get_rate(c->u.cpu.backup))
425 goto out;
426
427 ret = clk_set_rate(c->u.cpu.main, rate);
428 if (ret) {
429 pr_err("Failed to change cpu pll to %lu\n", rate);
430 goto out;
431 }
432
433 ret = clk_set_parent(c->parent, c->u.cpu.main);
434 if (ret) {
435 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
436 goto out;
437 }
438
439 out:
440 clk_disable(c->u.cpu.main);
441 return ret;
442 }
443
444 static struct clk_ops tegra_cpu_ops = {
445 .init = tegra2_cpu_clk_init,
446 .enable = tegra2_cpu_clk_enable,
447 .disable = tegra2_cpu_clk_disable,
448 .set_rate = tegra2_cpu_clk_set_rate,
449 };
450
451 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
452 * reset the COP block (i.e. AVP) */
453 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
454 {
455 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
456
457 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
458 clk_writel(1 << 1, reg);
459 }
460
461 static struct clk_ops tegra_cop_ops = {
462 .reset = tegra2_cop_clk_reset,
463 };
464
465 /* bus clock functions */
466 static void tegra2_bus_clk_init(struct clk *c)
467 {
468 u32 val = clk_readl(c->reg);
469 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
470 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
471 c->mul = 1;
472 }
473
474 static int tegra2_bus_clk_enable(struct clk *c)
475 {
476 u32 val;
477 unsigned long flags;
478
479 spin_lock_irqsave(&clock_register_lock, flags);
480
481 val = clk_readl(c->reg);
482 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
483 clk_writel(val, c->reg);
484
485 spin_unlock_irqrestore(&clock_register_lock, flags);
486
487 return 0;
488 }
489
490 static void tegra2_bus_clk_disable(struct clk *c)
491 {
492 u32 val;
493 unsigned long flags;
494
495 spin_lock_irqsave(&clock_register_lock, flags);
496
497 val = clk_readl(c->reg);
498 val |= BUS_CLK_DISABLE << c->reg_shift;
499 clk_writel(val, c->reg);
500
501 spin_unlock_irqrestore(&clock_register_lock, flags);
502 }
503
504 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
505 {
506 u32 val;
507 unsigned long parent_rate = clk_get_rate(c->parent);
508 unsigned long flags;
509 int ret = -EINVAL;
510 int i;
511
512 spin_lock_irqsave(&clock_register_lock, flags);
513
514 val = clk_readl(c->reg);
515 for (i = 1; i <= 4; i++) {
516 if (rate == parent_rate / i) {
517 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
518 val |= (i - 1) << c->reg_shift;
519 clk_writel(val, c->reg);
520 c->div = i;
521 c->mul = 1;
522 ret = 0;
523 break;
524 }
525 }
526
527 spin_unlock_irqrestore(&clock_register_lock, flags);
528
529 return ret;
530 }
531
532 static struct clk_ops tegra_bus_ops = {
533 .init = tegra2_bus_clk_init,
534 .enable = tegra2_bus_clk_enable,
535 .disable = tegra2_bus_clk_disable,
536 .set_rate = tegra2_bus_clk_set_rate,
537 };
538
539 /* Blink output functions */
540
541 static void tegra2_blink_clk_init(struct clk *c)
542 {
543 u32 val;
544
545 val = pmc_readl(PMC_CTRL);
546 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
547 c->mul = 1;
548 val = pmc_readl(c->reg);
549
550 if (val & PMC_BLINK_TIMER_ENB) {
551 unsigned int on_off;
552
553 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
554 PMC_BLINK_TIMER_DATA_ON_MASK;
555 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
556 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
557 on_off += val;
558 /* each tick in the blink timer is 4 32KHz clocks */
559 c->div = on_off * 4;
560 } else {
561 c->div = 1;
562 }
563 }
564
565 static int tegra2_blink_clk_enable(struct clk *c)
566 {
567 u32 val;
568
569 val = pmc_readl(PMC_DPD_PADS_ORIDE);
570 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
571
572 val = pmc_readl(PMC_CTRL);
573 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
574
575 return 0;
576 }
577
578 static void tegra2_blink_clk_disable(struct clk *c)
579 {
580 u32 val;
581
582 val = pmc_readl(PMC_CTRL);
583 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
584
585 val = pmc_readl(PMC_DPD_PADS_ORIDE);
586 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
587 }
588
589 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
590 {
591 unsigned long parent_rate = clk_get_rate(c->parent);
592 if (rate >= parent_rate) {
593 c->div = 1;
594 pmc_writel(0, c->reg);
595 } else {
596 unsigned int on_off;
597 u32 val;
598
599 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
600 c->div = on_off * 8;
601
602 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
603 PMC_BLINK_TIMER_DATA_ON_SHIFT;
604 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
605 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
606 val |= on_off;
607 val |= PMC_BLINK_TIMER_ENB;
608 pmc_writel(val, c->reg);
609 }
610
611 return 0;
612 }
613
614 static struct clk_ops tegra_blink_clk_ops = {
615 .init = &tegra2_blink_clk_init,
616 .enable = &tegra2_blink_clk_enable,
617 .disable = &tegra2_blink_clk_disable,
618 .set_rate = &tegra2_blink_clk_set_rate,
619 };
620
621 /* PLL Functions */
622 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
623 {
624 udelay(c->u.pll.lock_delay);
625
626 return 0;
627 }
628
629 static void tegra2_pll_clk_init(struct clk *c)
630 {
631 u32 val = clk_readl(c->reg + PLL_BASE);
632
633 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
634
635 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
636 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
637 c->mul = 1;
638 c->div = 1;
639 } else if (val & PLL_BASE_BYPASS) {
640 c->mul = 1;
641 c->div = 1;
642 } else {
643 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
644 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
645 if (c->flags & PLLU)
646 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
647 else
648 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
649 }
650 }
651
652 static int tegra2_pll_clk_enable(struct clk *c)
653 {
654 u32 val;
655 pr_debug("%s on clock %s\n", __func__, c->name);
656
657 val = clk_readl(c->reg + PLL_BASE);
658 val &= ~PLL_BASE_BYPASS;
659 val |= PLL_BASE_ENABLE;
660 clk_writel(val, c->reg + PLL_BASE);
661
662 tegra2_pll_clk_wait_for_lock(c);
663
664 return 0;
665 }
666
667 static void tegra2_pll_clk_disable(struct clk *c)
668 {
669 u32 val;
670 pr_debug("%s on clock %s\n", __func__, c->name);
671
672 val = clk_readl(c->reg);
673 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
674 clk_writel(val, c->reg);
675 }
676
677 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
678 {
679 u32 val;
680 unsigned long input_rate;
681 const struct clk_pll_freq_table *sel;
682
683 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
684
685 input_rate = clk_get_rate(c->parent);
686 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
687 if (sel->input_rate == input_rate && sel->output_rate == rate) {
688 c->mul = sel->n;
689 c->div = sel->m * sel->p;
690
691 val = clk_readl(c->reg + PLL_BASE);
692 if (c->flags & PLL_FIXED)
693 val |= PLL_BASE_OVERRIDE;
694 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
695 PLL_BASE_DIVM_MASK);
696 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
697 (sel->n << PLL_BASE_DIVN_SHIFT);
698 BUG_ON(sel->p < 1 || sel->p > 2);
699 if (c->flags & PLLU) {
700 if (sel->p == 1)
701 val |= PLLU_BASE_POST_DIV;
702 } else {
703 if (sel->p == 2)
704 val |= 1 << PLL_BASE_DIVP_SHIFT;
705 }
706 clk_writel(val, c->reg + PLL_BASE);
707
708 if (c->flags & PLL_HAS_CPCON) {
709 val = clk_readl(c->reg + PLL_MISC(c));
710 val &= ~PLL_MISC_CPCON_MASK;
711 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
712 clk_writel(val, c->reg + PLL_MISC(c));
713 }
714
715 if (c->state == ON)
716 tegra2_pll_clk_enable(c);
717
718 return 0;
719 }
720 }
721 return -EINVAL;
722 }
723
724 static struct clk_ops tegra_pll_ops = {
725 .init = tegra2_pll_clk_init,
726 .enable = tegra2_pll_clk_enable,
727 .disable = tegra2_pll_clk_disable,
728 .set_rate = tegra2_pll_clk_set_rate,
729 };
730
731 static void tegra2_pllx_clk_init(struct clk *c)
732 {
733 tegra2_pll_clk_init(c);
734
735 if (tegra_sku_id() == 7)
736 c->max_rate = 750000000;
737 }
738
739 static struct clk_ops tegra_pllx_ops = {
740 .init = tegra2_pllx_clk_init,
741 .enable = tegra2_pll_clk_enable,
742 .disable = tegra2_pll_clk_disable,
743 .set_rate = tegra2_pll_clk_set_rate,
744 };
745
746 static int tegra2_plle_clk_enable(struct clk *c)
747 {
748 u32 val;
749
750 pr_debug("%s on clock %s\n", __func__, c->name);
751
752 mdelay(1);
753
754 val = clk_readl(c->reg + PLL_BASE);
755 if (!(val & PLLE_MISC_READY))
756 return -EBUSY;
757
758 val = clk_readl(c->reg + PLL_BASE);
759 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
760 clk_writel(val, c->reg + PLL_BASE);
761
762 return 0;
763 }
764
765 static struct clk_ops tegra_plle_ops = {
766 .init = tegra2_pll_clk_init,
767 .enable = tegra2_plle_clk_enable,
768 .set_rate = tegra2_pll_clk_set_rate,
769 };
770
771 /* Clock divider ops */
772 static void tegra2_pll_div_clk_init(struct clk *c)
773 {
774 u32 val = clk_readl(c->reg);
775 u32 divu71;
776 val >>= c->reg_shift;
777 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
778 if (!(val & PLL_OUT_RESET_DISABLE))
779 c->state = OFF;
780
781 if (c->flags & DIV_U71) {
782 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
783 c->div = (divu71 + 2);
784 c->mul = 2;
785 } else if (c->flags & DIV_2) {
786 c->div = 2;
787 c->mul = 1;
788 } else {
789 c->div = 1;
790 c->mul = 1;
791 }
792 }
793
794 static int tegra2_pll_div_clk_enable(struct clk *c)
795 {
796 u32 val;
797 u32 new_val;
798 unsigned long flags;
799
800 pr_debug("%s: %s\n", __func__, c->name);
801 if (c->flags & DIV_U71) {
802 spin_lock_irqsave(&clock_register_lock, flags);
803 val = clk_readl(c->reg);
804 new_val = val >> c->reg_shift;
805 new_val &= 0xFFFF;
806
807 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
808
809 val &= ~(0xFFFF << c->reg_shift);
810 val |= new_val << c->reg_shift;
811 clk_writel(val, c->reg);
812 spin_unlock_irqrestore(&clock_register_lock, flags);
813 return 0;
814 } else if (c->flags & DIV_2) {
815 BUG_ON(!(c->flags & PLLD));
816 spin_lock_irqsave(&clock_register_lock, flags);
817 val = clk_readl(c->reg);
818 val &= ~PLLD_MISC_DIV_RST;
819 clk_writel(val, c->reg);
820 spin_unlock_irqrestore(&clock_register_lock, flags);
821 return 0;
822 }
823 return -EINVAL;
824 }
825
826 static void tegra2_pll_div_clk_disable(struct clk *c)
827 {
828 u32 val;
829 u32 new_val;
830 unsigned long flags;
831
832 pr_debug("%s: %s\n", __func__, c->name);
833 if (c->flags & DIV_U71) {
834 spin_lock_irqsave(&clock_register_lock, flags);
835 val = clk_readl(c->reg);
836 new_val = val >> c->reg_shift;
837 new_val &= 0xFFFF;
838
839 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
840
841 val &= ~(0xFFFF << c->reg_shift);
842 val |= new_val << c->reg_shift;
843 clk_writel(val, c->reg);
844 spin_unlock_irqrestore(&clock_register_lock, flags);
845 } else if (c->flags & DIV_2) {
846 BUG_ON(!(c->flags & PLLD));
847 spin_lock_irqsave(&clock_register_lock, flags);
848 val = clk_readl(c->reg);
849 val |= PLLD_MISC_DIV_RST;
850 clk_writel(val, c->reg);
851 spin_unlock_irqrestore(&clock_register_lock, flags);
852 }
853 }
854
855 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
856 {
857 u32 val;
858 u32 new_val;
859 int divider_u71;
860 unsigned long parent_rate = clk_get_rate(c->parent);
861 unsigned long flags;
862
863 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
864 if (c->flags & DIV_U71) {
865 divider_u71 = clk_div71_get_divider(parent_rate, rate);
866 if (divider_u71 >= 0) {
867 spin_lock_irqsave(&clock_register_lock, flags);
868 val = clk_readl(c->reg);
869 new_val = val >> c->reg_shift;
870 new_val &= 0xFFFF;
871 if (c->flags & DIV_U71_FIXED)
872 new_val |= PLL_OUT_OVERRIDE;
873 new_val &= ~PLL_OUT_RATIO_MASK;
874 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
875
876 val &= ~(0xFFFF << c->reg_shift);
877 val |= new_val << c->reg_shift;
878 clk_writel(val, c->reg);
879 c->div = divider_u71 + 2;
880 c->mul = 2;
881 spin_unlock_irqrestore(&clock_register_lock, flags);
882 return 0;
883 }
884 } else if (c->flags & DIV_2) {
885 if (parent_rate == rate * 2)
886 return 0;
887 }
888 return -EINVAL;
889 }
890
891 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
892 {
893 int divider;
894 unsigned long parent_rate = clk_get_rate(c->parent);
895 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
896
897 if (c->flags & DIV_U71) {
898 divider = clk_div71_get_divider(parent_rate, rate);
899 if (divider < 0)
900 return divider;
901 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
902 } else if (c->flags & DIV_2) {
903 return DIV_ROUND_UP(parent_rate, 2);
904 }
905 return -EINVAL;
906 }
907
908 static struct clk_ops tegra_pll_div_ops = {
909 .init = tegra2_pll_div_clk_init,
910 .enable = tegra2_pll_div_clk_enable,
911 .disable = tegra2_pll_div_clk_disable,
912 .set_rate = tegra2_pll_div_clk_set_rate,
913 .round_rate = tegra2_pll_div_clk_round_rate,
914 };
915
916 /* Periph clk ops */
917
918 static void tegra2_periph_clk_init(struct clk *c)
919 {
920 u32 val = clk_readl(c->reg);
921 const struct clk_mux_sel *mux = NULL;
922 const struct clk_mux_sel *sel;
923 if (c->flags & MUX) {
924 for (sel = c->inputs; sel->input != NULL; sel++) {
925 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
926 mux = sel;
927 }
928 BUG_ON(!mux);
929
930 c->parent = mux->input;
931 } else {
932 c->parent = c->inputs[0].input;
933 }
934
935 if (c->flags & DIV_U71) {
936 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
937 c->div = divu71 + 2;
938 c->mul = 2;
939 } else if (c->flags & DIV_U16) {
940 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
941 c->div = divu16 + 1;
942 c->mul = 1;
943 } else {
944 c->div = 1;
945 c->mul = 1;
946 }
947
948 c->state = ON;
949
950 if (!c->u.periph.clk_num)
951 return;
952
953 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
954 PERIPH_CLK_TO_ENB_BIT(c)))
955 c->state = OFF;
956
957 if (!(c->flags & PERIPH_NO_RESET))
958 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
959 PERIPH_CLK_TO_ENB_BIT(c))
960 c->state = OFF;
961 }
962
963 static int tegra2_periph_clk_enable(struct clk *c)
964 {
965 u32 val;
966 unsigned long flags;
967 int refcount;
968 pr_debug("%s on clock %s\n", __func__, c->name);
969
970 if (!c->u.periph.clk_num)
971 return 0;
972
973 spin_lock_irqsave(&clock_register_lock, flags);
974
975 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
976
977 if (refcount > 1)
978 goto out;
979
980 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
981 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
982 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
983 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
984 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
985 if (c->flags & PERIPH_EMC_ENB) {
986 /* The EMC peripheral clock has 2 extra enable bits */
987 /* FIXME: Do they need to be disabled? */
988 val = clk_readl(c->reg);
989 val |= 0x3 << 24;
990 clk_writel(val, c->reg);
991 }
992
993 out:
994 spin_unlock_irqrestore(&clock_register_lock, flags);
995
996 return 0;
997 }
998
999 static void tegra2_periph_clk_disable(struct clk *c)
1000 {
1001 unsigned long flags;
1002
1003 pr_debug("%s on clock %s\n", __func__, c->name);
1004
1005 if (!c->u.periph.clk_num)
1006 return;
1007
1008 spin_lock_irqsave(&clock_register_lock, flags);
1009
1010 if (c->refcnt)
1011 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1012
1013 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1014 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1015 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1016
1017 spin_unlock_irqrestore(&clock_register_lock, flags);
1018 }
1019
1020 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1021 {
1022 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1023
1024 pr_debug("%s %s on clock %s\n", __func__,
1025 assert ? "assert" : "deassert", c->name);
1026
1027 BUG_ON(!c->u.periph.clk_num);
1028
1029 if (!(c->flags & PERIPH_NO_RESET))
1030 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1031 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1032 }
1033
1034 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1035 {
1036 u32 val;
1037 const struct clk_mux_sel *sel;
1038 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1039 for (sel = c->inputs; sel->input != NULL; sel++) {
1040 if (sel->input == p) {
1041 val = clk_readl(c->reg);
1042 val &= ~PERIPH_CLK_SOURCE_MASK;
1043 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
1044
1045 if (c->refcnt)
1046 clk_enable(p);
1047
1048 clk_writel(val, c->reg);
1049
1050 if (c->refcnt && c->parent)
1051 clk_disable(c->parent);
1052
1053 clk_reparent(c, p);
1054 return 0;
1055 }
1056 }
1057
1058 return -EINVAL;
1059 }
1060
1061 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1062 {
1063 u32 val;
1064 int divider;
1065 unsigned long parent_rate = clk_get_rate(c->parent);
1066
1067 if (c->flags & DIV_U71) {
1068 divider = clk_div71_get_divider(parent_rate, rate);
1069 if (divider >= 0) {
1070 val = clk_readl(c->reg);
1071 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1072 val |= divider;
1073 clk_writel(val, c->reg);
1074 c->div = divider + 2;
1075 c->mul = 2;
1076 return 0;
1077 }
1078 } else if (c->flags & DIV_U16) {
1079 divider = clk_div16_get_divider(parent_rate, rate);
1080 if (divider >= 0) {
1081 val = clk_readl(c->reg);
1082 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1083 val |= divider;
1084 clk_writel(val, c->reg);
1085 c->div = divider + 1;
1086 c->mul = 1;
1087 return 0;
1088 }
1089 } else if (parent_rate <= rate) {
1090 c->div = 1;
1091 c->mul = 1;
1092 return 0;
1093 }
1094 return -EINVAL;
1095 }
1096
1097 static long tegra2_periph_clk_round_rate(struct clk *c,
1098 unsigned long rate)
1099 {
1100 int divider;
1101 unsigned long parent_rate = clk_get_rate(c->parent);
1102 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1103
1104 if (c->flags & DIV_U71) {
1105 divider = clk_div71_get_divider(parent_rate, rate);
1106 if (divider < 0)
1107 return divider;
1108
1109 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1110 } else if (c->flags & DIV_U16) {
1111 divider = clk_div16_get_divider(parent_rate, rate);
1112 if (divider < 0)
1113 return divider;
1114 return DIV_ROUND_UP(parent_rate, divider + 1);
1115 }
1116 return -EINVAL;
1117 }
1118
1119 static struct clk_ops tegra_periph_clk_ops = {
1120 .init = &tegra2_periph_clk_init,
1121 .enable = &tegra2_periph_clk_enable,
1122 .disable = &tegra2_periph_clk_disable,
1123 .set_parent = &tegra2_periph_clk_set_parent,
1124 .set_rate = &tegra2_periph_clk_set_rate,
1125 .round_rate = &tegra2_periph_clk_round_rate,
1126 .reset = &tegra2_periph_clk_reset,
1127 };
1128
1129 /* The SDMMC controllers have extra bits in the clock source register that
1130 * adjust the delay between the clock and data to compenstate for delays
1131 * on the PCB. */
1132 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1133 {
1134 u32 reg;
1135
1136 delay = clamp(delay, 0, 15);
1137 reg = clk_readl(c->reg);
1138 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1139 reg |= SDMMC_CLK_INT_FB_SEL;
1140 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1141 clk_writel(reg, c->reg);
1142 }
1143
1144 /* External memory controller clock ops */
1145 static void tegra2_emc_clk_init(struct clk *c)
1146 {
1147 tegra2_periph_clk_init(c);
1148 c->max_rate = clk_get_rate_locked(c);
1149 }
1150
1151 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1152 {
1153 long new_rate = rate;
1154
1155 new_rate = tegra_emc_round_rate(new_rate);
1156 if (new_rate < 0)
1157 return c->max_rate;
1158
1159 BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
1160
1161 return new_rate;
1162 }
1163
1164 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1165 {
1166 int ret;
1167 /*
1168 * The Tegra2 memory controller has an interlock with the clock
1169 * block that allows memory shadowed registers to be updated,
1170 * and then transfer them to the main registers at the same
1171 * time as the clock update without glitches.
1172 */
1173 ret = tegra_emc_set_rate(rate);
1174 if (ret < 0)
1175 return ret;
1176
1177 ret = tegra2_periph_clk_set_rate(c, rate);
1178 udelay(1);
1179
1180 return ret;
1181 }
1182
1183 static struct clk_ops tegra_emc_clk_ops = {
1184 .init = &tegra2_emc_clk_init,
1185 .enable = &tegra2_periph_clk_enable,
1186 .disable = &tegra2_periph_clk_disable,
1187 .set_parent = &tegra2_periph_clk_set_parent,
1188 .set_rate = &tegra2_emc_clk_set_rate,
1189 .round_rate = &tegra2_emc_clk_round_rate,
1190 .reset = &tegra2_periph_clk_reset,
1191 };
1192
1193 /* Clock doubler ops */
1194 static void tegra2_clk_double_init(struct clk *c)
1195 {
1196 c->mul = 2;
1197 c->div = 1;
1198 c->state = ON;
1199
1200 if (!c->u.periph.clk_num)
1201 return;
1202
1203 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1204 PERIPH_CLK_TO_ENB_BIT(c)))
1205 c->state = OFF;
1206 };
1207
1208 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1209 {
1210 if (rate != 2 * clk_get_rate(c->parent))
1211 return -EINVAL;
1212 c->mul = 2;
1213 c->div = 1;
1214 return 0;
1215 }
1216
1217 static struct clk_ops tegra_clk_double_ops = {
1218 .init = &tegra2_clk_double_init,
1219 .enable = &tegra2_periph_clk_enable,
1220 .disable = &tegra2_periph_clk_disable,
1221 .set_rate = &tegra2_clk_double_set_rate,
1222 };
1223
1224 /* Audio sync clock ops */
1225 static void tegra2_audio_sync_clk_init(struct clk *c)
1226 {
1227 int source;
1228 const struct clk_mux_sel *sel;
1229 u32 val = clk_readl(c->reg);
1230 c->state = (val & (1<<4)) ? OFF : ON;
1231 source = val & 0xf;
1232 for (sel = c->inputs; sel->input != NULL; sel++)
1233 if (sel->value == source)
1234 break;
1235 BUG_ON(sel->input == NULL);
1236 c->parent = sel->input;
1237 }
1238
1239 static int tegra2_audio_sync_clk_enable(struct clk *c)
1240 {
1241 clk_writel(0, c->reg);
1242 return 0;
1243 }
1244
1245 static void tegra2_audio_sync_clk_disable(struct clk *c)
1246 {
1247 clk_writel(1, c->reg);
1248 }
1249
1250 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1251 {
1252 u32 val;
1253 const struct clk_mux_sel *sel;
1254 for (sel = c->inputs; sel->input != NULL; sel++) {
1255 if (sel->input == p) {
1256 val = clk_readl(c->reg);
1257 val &= ~0xf;
1258 val |= sel->value;
1259
1260 if (c->refcnt)
1261 clk_enable(p);
1262
1263 clk_writel(val, c->reg);
1264
1265 if (c->refcnt && c->parent)
1266 clk_disable(c->parent);
1267
1268 clk_reparent(c, p);
1269 return 0;
1270 }
1271 }
1272
1273 return -EINVAL;
1274 }
1275
1276 static struct clk_ops tegra_audio_sync_clk_ops = {
1277 .init = tegra2_audio_sync_clk_init,
1278 .enable = tegra2_audio_sync_clk_enable,
1279 .disable = tegra2_audio_sync_clk_disable,
1280 .set_parent = tegra2_audio_sync_clk_set_parent,
1281 };
1282
1283 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1284
1285 static void tegra2_cdev_clk_init(struct clk *c)
1286 {
1287 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1288 * currently done in the pinmux code. */
1289 c->state = ON;
1290
1291 BUG_ON(!c->u.periph.clk_num);
1292
1293 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1294 PERIPH_CLK_TO_ENB_BIT(c)))
1295 c->state = OFF;
1296 }
1297
1298 static int tegra2_cdev_clk_enable(struct clk *c)
1299 {
1300 BUG_ON(!c->u.periph.clk_num);
1301
1302 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1303 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1304 return 0;
1305 }
1306
1307 static void tegra2_cdev_clk_disable(struct clk *c)
1308 {
1309 BUG_ON(!c->u.periph.clk_num);
1310
1311 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1312 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1313 }
1314
1315 static struct clk_ops tegra_cdev_clk_ops = {
1316 .init = &tegra2_cdev_clk_init,
1317 .enable = &tegra2_cdev_clk_enable,
1318 .disable = &tegra2_cdev_clk_disable,
1319 };
1320
1321 /* shared bus ops */
1322 /*
1323 * Some clocks may have multiple downstream users that need to request a
1324 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1325 * clock to each user. The frequency of the bus is set to the highest
1326 * enabled shared_bus_user clock, with a minimum value set by the
1327 * shared bus.
1328 */
1329 static int tegra_clk_shared_bus_update(struct clk *bus)
1330 {
1331 struct clk *c;
1332 unsigned long rate = bus->min_rate;
1333
1334 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1335 if (c->u.shared_bus_user.enabled)
1336 rate = max(c->u.shared_bus_user.rate, rate);
1337
1338 if (rate == clk_get_rate_locked(bus))
1339 return 0;
1340
1341 return clk_set_rate_locked(bus, rate);
1342 };
1343
1344 static void tegra_clk_shared_bus_init(struct clk *c)
1345 {
1346 unsigned long flags;
1347
1348 c->max_rate = c->parent->max_rate;
1349 c->u.shared_bus_user.rate = c->parent->max_rate;
1350 c->state = OFF;
1351 c->set = true;
1352
1353 spin_lock_irqsave(&c->parent->spinlock, flags);
1354
1355 list_add_tail(&c->u.shared_bus_user.node,
1356 &c->parent->shared_bus_list);
1357
1358 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1359 }
1360
1361 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1362 {
1363 unsigned long flags;
1364 int ret;
1365 long new_rate = rate;
1366
1367 new_rate = clk_round_rate(c->parent, new_rate);
1368 if (new_rate < 0)
1369 return new_rate;
1370
1371 spin_lock_irqsave(&c->parent->spinlock, flags);
1372
1373 c->u.shared_bus_user.rate = new_rate;
1374 ret = tegra_clk_shared_bus_update(c->parent);
1375
1376 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1377
1378 return ret;
1379 }
1380
1381 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1382 {
1383 return clk_round_rate(c->parent, rate);
1384 }
1385
1386 static int tegra_clk_shared_bus_enable(struct clk *c)
1387 {
1388 unsigned long flags;
1389 int ret;
1390
1391 spin_lock_irqsave(&c->parent->spinlock, flags);
1392
1393 c->u.shared_bus_user.enabled = true;
1394 ret = tegra_clk_shared_bus_update(c->parent);
1395
1396 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1397
1398 return ret;
1399 }
1400
1401 static void tegra_clk_shared_bus_disable(struct clk *c)
1402 {
1403 unsigned long flags;
1404 int ret;
1405
1406 spin_lock_irqsave(&c->parent->spinlock, flags);
1407
1408 c->u.shared_bus_user.enabled = false;
1409 ret = tegra_clk_shared_bus_update(c->parent);
1410 WARN_ON_ONCE(ret);
1411
1412 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1413 }
1414
1415 static struct clk_ops tegra_clk_shared_bus_ops = {
1416 .init = tegra_clk_shared_bus_init,
1417 .enable = tegra_clk_shared_bus_enable,
1418 .disable = tegra_clk_shared_bus_disable,
1419 .set_rate = tegra_clk_shared_bus_set_rate,
1420 .round_rate = tegra_clk_shared_bus_round_rate,
1421 };
1422
1423
1424 /* Clock definitions */
1425 static struct clk tegra_clk_32k = {
1426 .name = "clk_32k",
1427 .rate = 32768,
1428 .ops = NULL,
1429 .max_rate = 32768,
1430 };
1431
1432 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1433 {32768, 12000000, 366, 1, 1, 0},
1434 {32768, 13000000, 397, 1, 1, 0},
1435 {32768, 19200000, 586, 1, 1, 0},
1436 {32768, 26000000, 793, 1, 1, 0},
1437 {0, 0, 0, 0, 0, 0},
1438 };
1439
1440 static struct clk tegra_pll_s = {
1441 .name = "pll_s",
1442 .flags = PLL_ALT_MISC_REG,
1443 .ops = &tegra_pll_ops,
1444 .parent = &tegra_clk_32k,
1445 .max_rate = 26000000,
1446 .reg = 0xf0,
1447 .u.pll = {
1448 .input_min = 32768,
1449 .input_max = 32768,
1450 .cf_min = 0, /* FIXME */
1451 .cf_max = 0, /* FIXME */
1452 .vco_min = 12000000,
1453 .vco_max = 26000000,
1454 .freq_table = tegra_pll_s_freq_table,
1455 .lock_delay = 300,
1456 },
1457 };
1458
1459 static struct clk_mux_sel tegra_clk_m_sel[] = {
1460 { .input = &tegra_clk_32k, .value = 0},
1461 { .input = &tegra_pll_s, .value = 1},
1462 { NULL , 0},
1463 };
1464
1465 static struct clk tegra_clk_m = {
1466 .name = "clk_m",
1467 .flags = ENABLE_ON_INIT,
1468 .ops = &tegra_clk_m_ops,
1469 .inputs = tegra_clk_m_sel,
1470 .reg = 0x1fc,
1471 .reg_shift = 28,
1472 .max_rate = 26000000,
1473 };
1474
1475 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1476 { 0, 0, 0, 0, 0, 0 },
1477 };
1478
1479 static struct clk tegra_pll_c = {
1480 .name = "pll_c",
1481 .flags = PLL_HAS_CPCON,
1482 .ops = &tegra_pll_ops,
1483 .reg = 0x80,
1484 .parent = &tegra_clk_m,
1485 .max_rate = 600000000,
1486 .u.pll = {
1487 .input_min = 2000000,
1488 .input_max = 31000000,
1489 .cf_min = 1000000,
1490 .cf_max = 6000000,
1491 .vco_min = 20000000,
1492 .vco_max = 1400000000,
1493 .freq_table = tegra_pll_c_freq_table,
1494 .lock_delay = 300,
1495 },
1496 };
1497
1498 static struct clk tegra_pll_c_out1 = {
1499 .name = "pll_c_out1",
1500 .ops = &tegra_pll_div_ops,
1501 .flags = DIV_U71,
1502 .parent = &tegra_pll_c,
1503 .reg = 0x84,
1504 .reg_shift = 0,
1505 .max_rate = 600000000,
1506 };
1507
1508 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1509 { 12000000, 666000000, 666, 12, 1, 8},
1510 { 13000000, 666000000, 666, 13, 1, 8},
1511 { 19200000, 666000000, 555, 16, 1, 8},
1512 { 26000000, 666000000, 666, 26, 1, 8},
1513 { 12000000, 600000000, 600, 12, 1, 8},
1514 { 13000000, 600000000, 600, 13, 1, 8},
1515 { 19200000, 600000000, 375, 12, 1, 6},
1516 { 26000000, 600000000, 600, 26, 1, 8},
1517 { 0, 0, 0, 0, 0, 0 },
1518 };
1519
1520 static struct clk tegra_pll_m = {
1521 .name = "pll_m",
1522 .flags = PLL_HAS_CPCON,
1523 .ops = &tegra_pll_ops,
1524 .reg = 0x90,
1525 .parent = &tegra_clk_m,
1526 .max_rate = 800000000,
1527 .u.pll = {
1528 .input_min = 2000000,
1529 .input_max = 31000000,
1530 .cf_min = 1000000,
1531 .cf_max = 6000000,
1532 .vco_min = 20000000,
1533 .vco_max = 1200000000,
1534 .freq_table = tegra_pll_m_freq_table,
1535 .lock_delay = 300,
1536 },
1537 };
1538
1539 static struct clk tegra_pll_m_out1 = {
1540 .name = "pll_m_out1",
1541 .ops = &tegra_pll_div_ops,
1542 .flags = DIV_U71,
1543 .parent = &tegra_pll_m,
1544 .reg = 0x94,
1545 .reg_shift = 0,
1546 .max_rate = 600000000,
1547 };
1548
1549 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1550 { 12000000, 216000000, 432, 12, 2, 8},
1551 { 13000000, 216000000, 432, 13, 2, 8},
1552 { 19200000, 216000000, 90, 4, 2, 1},
1553 { 26000000, 216000000, 432, 26, 2, 8},
1554 { 12000000, 432000000, 432, 12, 1, 8},
1555 { 13000000, 432000000, 432, 13, 1, 8},
1556 { 19200000, 432000000, 90, 4, 1, 1},
1557 { 26000000, 432000000, 432, 26, 1, 8},
1558 { 0, 0, 0, 0, 0, 0 },
1559 };
1560
1561 static struct clk tegra_pll_p = {
1562 .name = "pll_p",
1563 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1564 .ops = &tegra_pll_ops,
1565 .reg = 0xa0,
1566 .parent = &tegra_clk_m,
1567 .max_rate = 432000000,
1568 .u.pll = {
1569 .input_min = 2000000,
1570 .input_max = 31000000,
1571 .cf_min = 1000000,
1572 .cf_max = 6000000,
1573 .vco_min = 20000000,
1574 .vco_max = 1400000000,
1575 .freq_table = tegra_pll_p_freq_table,
1576 .lock_delay = 300,
1577 },
1578 };
1579
1580 static struct clk tegra_pll_p_out1 = {
1581 .name = "pll_p_out1",
1582 .ops = &tegra_pll_div_ops,
1583 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1584 .parent = &tegra_pll_p,
1585 .reg = 0xa4,
1586 .reg_shift = 0,
1587 .max_rate = 432000000,
1588 };
1589
1590 static struct clk tegra_pll_p_out2 = {
1591 .name = "pll_p_out2",
1592 .ops = &tegra_pll_div_ops,
1593 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1594 .parent = &tegra_pll_p,
1595 .reg = 0xa4,
1596 .reg_shift = 16,
1597 .max_rate = 432000000,
1598 };
1599
1600 static struct clk tegra_pll_p_out3 = {
1601 .name = "pll_p_out3",
1602 .ops = &tegra_pll_div_ops,
1603 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1604 .parent = &tegra_pll_p,
1605 .reg = 0xa8,
1606 .reg_shift = 0,
1607 .max_rate = 432000000,
1608 };
1609
1610 static struct clk tegra_pll_p_out4 = {
1611 .name = "pll_p_out4",
1612 .ops = &tegra_pll_div_ops,
1613 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1614 .parent = &tegra_pll_p,
1615 .reg = 0xa8,
1616 .reg_shift = 16,
1617 .max_rate = 432000000,
1618 };
1619
1620 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1621 { 28800000, 56448000, 49, 25, 1, 1},
1622 { 28800000, 73728000, 64, 25, 1, 1},
1623 { 28800000, 24000000, 5, 6, 1, 1},
1624 { 0, 0, 0, 0, 0, 0 },
1625 };
1626
1627 static struct clk tegra_pll_a = {
1628 .name = "pll_a",
1629 .flags = PLL_HAS_CPCON,
1630 .ops = &tegra_pll_ops,
1631 .reg = 0xb0,
1632 .parent = &tegra_pll_p_out1,
1633 .max_rate = 73728000,
1634 .u.pll = {
1635 .input_min = 2000000,
1636 .input_max = 31000000,
1637 .cf_min = 1000000,
1638 .cf_max = 6000000,
1639 .vco_min = 20000000,
1640 .vco_max = 1400000000,
1641 .freq_table = tegra_pll_a_freq_table,
1642 .lock_delay = 300,
1643 },
1644 };
1645
1646 static struct clk tegra_pll_a_out0 = {
1647 .name = "pll_a_out0",
1648 .ops = &tegra_pll_div_ops,
1649 .flags = DIV_U71,
1650 .parent = &tegra_pll_a,
1651 .reg = 0xb4,
1652 .reg_shift = 0,
1653 .max_rate = 73728000,
1654 };
1655
1656 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1657 { 12000000, 216000000, 216, 12, 1, 4},
1658 { 13000000, 216000000, 216, 13, 1, 4},
1659 { 19200000, 216000000, 135, 12, 1, 3},
1660 { 26000000, 216000000, 216, 26, 1, 4},
1661
1662 { 12000000, 594000000, 594, 12, 1, 8},
1663 { 13000000, 594000000, 594, 13, 1, 8},
1664 { 19200000, 594000000, 495, 16, 1, 8},
1665 { 26000000, 594000000, 594, 26, 1, 8},
1666
1667 { 12000000, 1000000000, 1000, 12, 1, 12},
1668 { 13000000, 1000000000, 1000, 13, 1, 12},
1669 { 19200000, 1000000000, 625, 12, 1, 8},
1670 { 26000000, 1000000000, 1000, 26, 1, 12},
1671
1672 { 0, 0, 0, 0, 0, 0 },
1673 };
1674
1675 static struct clk tegra_pll_d = {
1676 .name = "pll_d",
1677 .flags = PLL_HAS_CPCON | PLLD,
1678 .ops = &tegra_pll_ops,
1679 .reg = 0xd0,
1680 .parent = &tegra_clk_m,
1681 .max_rate = 1000000000,
1682 .u.pll = {
1683 .input_min = 2000000,
1684 .input_max = 40000000,
1685 .cf_min = 1000000,
1686 .cf_max = 6000000,
1687 .vco_min = 40000000,
1688 .vco_max = 1000000000,
1689 .freq_table = tegra_pll_d_freq_table,
1690 .lock_delay = 1000,
1691 },
1692 };
1693
1694 static struct clk tegra_pll_d_out0 = {
1695 .name = "pll_d_out0",
1696 .ops = &tegra_pll_div_ops,
1697 .flags = DIV_2 | PLLD,
1698 .parent = &tegra_pll_d,
1699 .max_rate = 500000000,
1700 };
1701
1702 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1703 { 12000000, 480000000, 960, 12, 2, 0},
1704 { 13000000, 480000000, 960, 13, 2, 0},
1705 { 19200000, 480000000, 200, 4, 2, 0},
1706 { 26000000, 480000000, 960, 26, 2, 0},
1707 { 0, 0, 0, 0, 0, 0 },
1708 };
1709
1710 static struct clk tegra_pll_u = {
1711 .name = "pll_u",
1712 .flags = PLLU,
1713 .ops = &tegra_pll_ops,
1714 .reg = 0xc0,
1715 .parent = &tegra_clk_m,
1716 .max_rate = 480000000,
1717 .u.pll = {
1718 .input_min = 2000000,
1719 .input_max = 40000000,
1720 .cf_min = 1000000,
1721 .cf_max = 6000000,
1722 .vco_min = 480000000,
1723 .vco_max = 960000000,
1724 .freq_table = tegra_pll_u_freq_table,
1725 .lock_delay = 1000,
1726 },
1727 };
1728
1729 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1730 /* 1 GHz */
1731 { 12000000, 1000000000, 1000, 12, 1, 12},
1732 { 13000000, 1000000000, 1000, 13, 1, 12},
1733 { 19200000, 1000000000, 625, 12, 1, 8},
1734 { 26000000, 1000000000, 1000, 26, 1, 12},
1735
1736 /* 912 MHz */
1737 { 12000000, 912000000, 912, 12, 1, 12},
1738 { 13000000, 912000000, 912, 13, 1, 12},
1739 { 19200000, 912000000, 760, 16, 1, 8},
1740 { 26000000, 912000000, 912, 26, 1, 12},
1741
1742 /* 816 MHz */
1743 { 12000000, 816000000, 816, 12, 1, 12},
1744 { 13000000, 816000000, 816, 13, 1, 12},
1745 { 19200000, 816000000, 680, 16, 1, 8},
1746 { 26000000, 816000000, 816, 26, 1, 12},
1747
1748 /* 760 MHz */
1749 { 12000000, 760000000, 760, 12, 1, 12},
1750 { 13000000, 760000000, 760, 13, 1, 12},
1751 { 19200000, 760000000, 950, 24, 1, 8},
1752 { 26000000, 760000000, 760, 26, 1, 12},
1753
1754 /* 608 MHz */
1755 { 12000000, 608000000, 608, 12, 1, 12},
1756 { 13000000, 608000000, 608, 13, 1, 12},
1757 { 19200000, 608000000, 380, 12, 1, 8},
1758 { 26000000, 608000000, 608, 26, 1, 12},
1759
1760 /* 456 MHz */
1761 { 12000000, 456000000, 456, 12, 1, 12},
1762 { 13000000, 456000000, 456, 13, 1, 12},
1763 { 19200000, 456000000, 380, 16, 1, 8},
1764 { 26000000, 456000000, 456, 26, 1, 12},
1765
1766 /* 312 MHz */
1767 { 12000000, 312000000, 312, 12, 1, 12},
1768 { 13000000, 312000000, 312, 13, 1, 12},
1769 { 19200000, 312000000, 260, 16, 1, 8},
1770 { 26000000, 312000000, 312, 26, 1, 12},
1771
1772 { 0, 0, 0, 0, 0, 0 },
1773 };
1774
1775 static struct clk tegra_pll_x = {
1776 .name = "pll_x",
1777 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1778 .ops = &tegra_pllx_ops,
1779 .reg = 0xe0,
1780 .parent = &tegra_clk_m,
1781 .max_rate = 1000000000,
1782 .u.pll = {
1783 .input_min = 2000000,
1784 .input_max = 31000000,
1785 .cf_min = 1000000,
1786 .cf_max = 6000000,
1787 .vco_min = 20000000,
1788 .vco_max = 1200000000,
1789 .freq_table = tegra_pll_x_freq_table,
1790 .lock_delay = 300,
1791 },
1792 };
1793
1794 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1795 { 12000000, 100000000, 200, 24, 1, 0 },
1796 { 0, 0, 0, 0, 0, 0 },
1797 };
1798
1799 static struct clk tegra_pll_e = {
1800 .name = "pll_e",
1801 .flags = PLL_ALT_MISC_REG,
1802 .ops = &tegra_plle_ops,
1803 .parent = &tegra_clk_m,
1804 .reg = 0xe8,
1805 .max_rate = 100000000,
1806 .u.pll = {
1807 .input_min = 12000000,
1808 .input_max = 12000000,
1809 .freq_table = tegra_pll_e_freq_table,
1810 },
1811 };
1812
1813 static struct clk tegra_clk_d = {
1814 .name = "clk_d",
1815 .flags = PERIPH_NO_RESET,
1816 .ops = &tegra_clk_double_ops,
1817 .reg = 0x34,
1818 .reg_shift = 12,
1819 .parent = &tegra_clk_m,
1820 .max_rate = 52000000,
1821 .u.periph = {
1822 .clk_num = 90,
1823 },
1824 };
1825
1826 /* dap_mclk1, belongs to the cdev1 pingroup. */
1827 static struct clk tegra_clk_cdev1 = {
1828 .name = "cdev1",
1829 .ops = &tegra_cdev_clk_ops,
1830 .rate = 26000000,
1831 .max_rate = 26000000,
1832 .u.periph = {
1833 .clk_num = 94,
1834 },
1835 };
1836
1837 /* dap_mclk2, belongs to the cdev2 pingroup. */
1838 static struct clk tegra_clk_cdev2 = {
1839 .name = "cdev2",
1840 .ops = &tegra_cdev_clk_ops,
1841 .rate = 26000000,
1842 .max_rate = 26000000,
1843 .u.periph = {
1844 .clk_num = 93,
1845 },
1846 };
1847
1848 /* initialized before peripheral clocks */
1849 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1850 static const struct audio_sources {
1851 const char *name;
1852 int value;
1853 } mux_audio_sync_clk_sources[] = {
1854 { .name = "spdif_in", .value = 0 },
1855 { .name = "i2s1", .value = 1 },
1856 { .name = "i2s2", .value = 2 },
1857 { .name = "pll_a_out0", .value = 4 },
1858 #if 0 /* FIXME: not implemented */
1859 { .name = "ac97", .value = 3 },
1860 { .name = "ext_audio_clk2", .value = 5 },
1861 { .name = "ext_audio_clk1", .value = 6 },
1862 { .name = "ext_vimclk", .value = 7 },
1863 #endif
1864 { NULL, 0 }
1865 };
1866
1867 static struct clk tegra_clk_audio = {
1868 .name = "audio",
1869 .inputs = mux_audio_sync_clk,
1870 .reg = 0x38,
1871 .max_rate = 73728000,
1872 .ops = &tegra_audio_sync_clk_ops
1873 };
1874
1875 static struct clk tegra_clk_audio_2x = {
1876 .name = "audio_2x",
1877 .flags = PERIPH_NO_RESET,
1878 .max_rate = 48000000,
1879 .ops = &tegra_clk_double_ops,
1880 .reg = 0x34,
1881 .reg_shift = 8,
1882 .parent = &tegra_clk_audio,
1883 .u.periph = {
1884 .clk_num = 89,
1885 },
1886 };
1887
1888 static struct clk_lookup tegra_audio_clk_lookups[] = {
1889 { .con_id = "audio", .clk = &tegra_clk_audio },
1890 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1891 };
1892
1893 /* This is called after peripheral clocks are initialized, as the
1894 * audio_sync clock depends on some of the peripheral clocks.
1895 */
1896
1897 static void init_audio_sync_clock_mux(void)
1898 {
1899 int i;
1900 struct clk_mux_sel *sel = mux_audio_sync_clk;
1901 const struct audio_sources *src = mux_audio_sync_clk_sources;
1902 struct clk_lookup *lookup;
1903
1904 for (i = 0; src->name; i++, sel++, src++) {
1905 sel->input = tegra_get_clock_by_name(src->name);
1906 if (!sel->input)
1907 pr_err("%s: could not find clk %s\n", __func__,
1908 src->name);
1909 sel->value = src->value;
1910 }
1911
1912 lookup = tegra_audio_clk_lookups;
1913 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1914 clk_init(lookup->clk);
1915 clkdev_add(lookup);
1916 }
1917 }
1918
1919 static struct clk_mux_sel mux_cclk[] = {
1920 { .input = &tegra_clk_m, .value = 0},
1921 { .input = &tegra_pll_c, .value = 1},
1922 { .input = &tegra_clk_32k, .value = 2},
1923 { .input = &tegra_pll_m, .value = 3},
1924 { .input = &tegra_pll_p, .value = 4},
1925 { .input = &tegra_pll_p_out4, .value = 5},
1926 { .input = &tegra_pll_p_out3, .value = 6},
1927 { .input = &tegra_clk_d, .value = 7},
1928 { .input = &tegra_pll_x, .value = 8},
1929 { NULL, 0},
1930 };
1931
1932 static struct clk_mux_sel mux_sclk[] = {
1933 { .input = &tegra_clk_m, .value = 0},
1934 { .input = &tegra_pll_c_out1, .value = 1},
1935 { .input = &tegra_pll_p_out4, .value = 2},
1936 { .input = &tegra_pll_p_out3, .value = 3},
1937 { .input = &tegra_pll_p_out2, .value = 4},
1938 { .input = &tegra_clk_d, .value = 5},
1939 { .input = &tegra_clk_32k, .value = 6},
1940 { .input = &tegra_pll_m_out1, .value = 7},
1941 { NULL, 0},
1942 };
1943
1944 static struct clk tegra_clk_cclk = {
1945 .name = "cclk",
1946 .inputs = mux_cclk,
1947 .reg = 0x20,
1948 .ops = &tegra_super_ops,
1949 .max_rate = 1000000000,
1950 };
1951
1952 static struct clk tegra_clk_sclk = {
1953 .name = "sclk",
1954 .inputs = mux_sclk,
1955 .reg = 0x28,
1956 .ops = &tegra_super_ops,
1957 .max_rate = 240000000,
1958 .min_rate = 120000000,
1959 };
1960
1961 static struct clk tegra_clk_virtual_cpu = {
1962 .name = "cpu",
1963 .parent = &tegra_clk_cclk,
1964 .ops = &tegra_cpu_ops,
1965 .max_rate = 1000000000,
1966 .u.cpu = {
1967 .main = &tegra_pll_x,
1968 .backup = &tegra_pll_p,
1969 },
1970 };
1971
1972 static struct clk tegra_clk_cop = {
1973 .name = "cop",
1974 .parent = &tegra_clk_sclk,
1975 .ops = &tegra_cop_ops,
1976 .max_rate = 240000000,
1977 };
1978
1979 static struct clk tegra_clk_hclk = {
1980 .name = "hclk",
1981 .flags = DIV_BUS,
1982 .parent = &tegra_clk_sclk,
1983 .reg = 0x30,
1984 .reg_shift = 4,
1985 .ops = &tegra_bus_ops,
1986 .max_rate = 240000000,
1987 };
1988
1989 static struct clk tegra_clk_pclk = {
1990 .name = "pclk",
1991 .flags = DIV_BUS,
1992 .parent = &tegra_clk_hclk,
1993 .reg = 0x30,
1994 .reg_shift = 0,
1995 .ops = &tegra_bus_ops,
1996 .max_rate = 120000000,
1997 };
1998
1999 static struct clk tegra_clk_blink = {
2000 .name = "blink",
2001 .parent = &tegra_clk_32k,
2002 .reg = 0x40,
2003 .ops = &tegra_blink_clk_ops,
2004 .max_rate = 32768,
2005 };
2006
2007 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2008 { .input = &tegra_pll_m, .value = 0},
2009 { .input = &tegra_pll_c, .value = 1},
2010 { .input = &tegra_pll_p, .value = 2},
2011 { .input = &tegra_pll_a_out0, .value = 3},
2012 { NULL, 0},
2013 };
2014
2015 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2016 { .input = &tegra_pll_m, .value = 0},
2017 { .input = &tegra_pll_c, .value = 1},
2018 { .input = &tegra_pll_p, .value = 2},
2019 { .input = &tegra_clk_m, .value = 3},
2020 { NULL, 0},
2021 };
2022
2023 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2024 { .input = &tegra_pll_p, .value = 0},
2025 { .input = &tegra_pll_c, .value = 1},
2026 { .input = &tegra_pll_m, .value = 2},
2027 { .input = &tegra_clk_m, .value = 3},
2028 { NULL, 0},
2029 };
2030
2031 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2032 {.input = &tegra_pll_a_out0, .value = 0},
2033 {.input = &tegra_clk_audio_2x, .value = 1},
2034 {.input = &tegra_pll_p, .value = 2},
2035 {.input = &tegra_clk_m, .value = 3},
2036 { NULL, 0},
2037 };
2038
2039 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2040 {.input = &tegra_pll_p, .value = 0},
2041 {.input = &tegra_pll_d_out0, .value = 1},
2042 {.input = &tegra_pll_c, .value = 2},
2043 {.input = &tegra_clk_m, .value = 3},
2044 { NULL, 0},
2045 };
2046
2047 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2048 {.input = &tegra_pll_p, .value = 0},
2049 {.input = &tegra_pll_c, .value = 1},
2050 {.input = &tegra_clk_audio, .value = 2},
2051 {.input = &tegra_clk_m, .value = 3},
2052 {.input = &tegra_clk_32k, .value = 4},
2053 { NULL, 0},
2054 };
2055
2056 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2057 {.input = &tegra_pll_p, .value = 0},
2058 {.input = &tegra_pll_c, .value = 1},
2059 {.input = &tegra_pll_m, .value = 2},
2060 { NULL, 0},
2061 };
2062
2063 static struct clk_mux_sel mux_clk_m[] = {
2064 { .input = &tegra_clk_m, .value = 0},
2065 { NULL, 0},
2066 };
2067
2068 static struct clk_mux_sel mux_pllp_out3[] = {
2069 { .input = &tegra_pll_p_out3, .value = 0},
2070 { NULL, 0},
2071 };
2072
2073 static struct clk_mux_sel mux_plld[] = {
2074 { .input = &tegra_pll_d, .value = 0},
2075 { NULL, 0},
2076 };
2077
2078 static struct clk_mux_sel mux_clk_32k[] = {
2079 { .input = &tegra_clk_32k, .value = 0},
2080 { NULL, 0},
2081 };
2082
2083 static struct clk_mux_sel mux_pclk[] = {
2084 { .input = &tegra_clk_pclk, .value = 0},
2085 { NULL, 0},
2086 };
2087
2088 static struct clk tegra_clk_emc = {
2089 .name = "emc",
2090 .ops = &tegra_emc_clk_ops,
2091 .reg = 0x19c,
2092 .max_rate = 800000000,
2093 .inputs = mux_pllm_pllc_pllp_clkm,
2094 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2095 .u.periph = {
2096 .clk_num = 57,
2097 },
2098 };
2099
2100 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2101 { \
2102 .name = _name, \
2103 .lookup = { \
2104 .dev_id = _dev, \
2105 .con_id = _con, \
2106 }, \
2107 .ops = &tegra_periph_clk_ops, \
2108 .reg = _reg, \
2109 .inputs = _inputs, \
2110 .flags = _flags, \
2111 .max_rate = _max, \
2112 .u.periph = { \
2113 .clk_num = _clk_num, \
2114 }, \
2115 }
2116
2117 #define SHARED_CLK(_name, _dev, _con, _parent) \
2118 { \
2119 .name = _name, \
2120 .lookup = { \
2121 .dev_id = _dev, \
2122 .con_id = _con, \
2123 }, \
2124 .ops = &tegra_clk_shared_bus_ops, \
2125 .parent = _parent, \
2126 }
2127
2128 static struct clk tegra_list_clks[] = {
2129 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
2130 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2131 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2132 PERIPH_CLK("i2s1", "tegra-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2133 PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2134 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2135 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2136 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
2137 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2138 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2139 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2140 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2141 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2142 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2143 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2144 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2145 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2146 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2147 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2148 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2149 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2150 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2151 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2152 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2153 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2154 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2155 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2156 /* FIXME: what is la? */
2157 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2158 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2159 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2160 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2161 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2162 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2163 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2164 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2165 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2166 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2167 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2168 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2169 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2170 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2171 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2172 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2173 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2174 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2175 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2176 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2177 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2178 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2179 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2180 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2181 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2182 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2183 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2184 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2185 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2186 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2187 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2188 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2189 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2190 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2191 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2192 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2193 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2194 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2195 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2196 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2197
2198 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2199 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2200 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2201 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2202 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2203 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2204 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2205 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2206 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2207 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2208 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2209 };
2210
2211 #define CLK_DUPLICATE(_name, _dev, _con) \
2212 { \
2213 .name = _name, \
2214 .lookup = { \
2215 .dev_id = _dev, \
2216 .con_id = _con, \
2217 }, \
2218 }
2219
2220 /* Some clocks may be used by different drivers depending on the board
2221 * configuration. List those here to register them twice in the clock lookup
2222 * table under two names.
2223 */
2224 static struct clk_duplicate tegra_clk_duplicates[] = {
2225 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
2226 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
2227 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
2228 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
2229 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
2230 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2231 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2232 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2233 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2234 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2235 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2236 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2237 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2238 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2239 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2240 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2241 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2242 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2243 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2244 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2245 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2246 };
2247
2248 #define CLK(dev, con, ck) \
2249 { \
2250 .dev_id = dev, \
2251 .con_id = con, \
2252 .clk = ck, \
2253 }
2254
2255 static struct clk *tegra_ptr_clks[] = {
2256 &tegra_clk_32k,
2257 &tegra_pll_s,
2258 &tegra_clk_m,
2259 &tegra_pll_m,
2260 &tegra_pll_m_out1,
2261 &tegra_pll_c,
2262 &tegra_pll_c_out1,
2263 &tegra_pll_p,
2264 &tegra_pll_p_out1,
2265 &tegra_pll_p_out2,
2266 &tegra_pll_p_out3,
2267 &tegra_pll_p_out4,
2268 &tegra_pll_a,
2269 &tegra_pll_a_out0,
2270 &tegra_pll_d,
2271 &tegra_pll_d_out0,
2272 &tegra_pll_u,
2273 &tegra_pll_x,
2274 &tegra_pll_e,
2275 &tegra_clk_cclk,
2276 &tegra_clk_sclk,
2277 &tegra_clk_hclk,
2278 &tegra_clk_pclk,
2279 &tegra_clk_d,
2280 &tegra_clk_cdev1,
2281 &tegra_clk_cdev2,
2282 &tegra_clk_virtual_cpu,
2283 &tegra_clk_blink,
2284 &tegra_clk_cop,
2285 &tegra_clk_emc,
2286 };
2287
2288 static void tegra2_init_one_clock(struct clk *c)
2289 {
2290 clk_init(c);
2291 INIT_LIST_HEAD(&c->shared_bus_list);
2292 if (!c->lookup.dev_id && !c->lookup.con_id)
2293 c->lookup.con_id = c->name;
2294 c->lookup.clk = c;
2295 clkdev_add(&c->lookup);
2296 }
2297
2298 void __init tegra2_init_clocks(void)
2299 {
2300 int i;
2301 struct clk *c;
2302
2303 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2304 tegra2_init_one_clock(tegra_ptr_clks[i]);
2305
2306 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2307 tegra2_init_one_clock(&tegra_list_clks[i]);
2308
2309 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2310 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2311 if (!c) {
2312 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2313 tegra_clk_duplicates[i].name);
2314 continue;
2315 }
2316
2317 tegra_clk_duplicates[i].lookup.clk = c;
2318 clkdev_add(&tegra_clk_duplicates[i].lookup);
2319 }
2320
2321 init_audio_sync_clock_mux();
2322 }
2323
2324 #ifdef CONFIG_PM
2325 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2326 PERIPH_CLK_SOURCE_NUM + 22];
2327
2328 void tegra_clk_suspend(void)
2329 {
2330 unsigned long off, i;
2331 u32 *ctx = clk_rst_suspend;
2332
2333 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2334 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2335 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2336 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2337 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2338 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2339 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2340 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2341 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2342 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2343 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2344
2345 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2346 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2347 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2348
2349 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2350 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2351
2352 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2353 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2354 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2355
2356 *ctx++ = clk_readl(tegra_clk_audio.reg);
2357
2358 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2359 off += 4) {
2360 if (off == PERIPH_CLK_SOURCE_EMC)
2361 continue;
2362 *ctx++ = clk_readl(off);
2363 }
2364
2365 off = RST_DEVICES;
2366 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2367 *ctx++ = clk_readl(off);
2368
2369 off = CLK_OUT_ENB;
2370 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2371 *ctx++ = clk_readl(off);
2372
2373 *ctx++ = clk_readl(MISC_CLK_ENB);
2374 *ctx++ = clk_readl(CLK_MASK_ARM);
2375
2376 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2377 }
2378
2379 void tegra_clk_resume(void)
2380 {
2381 unsigned long off, i;
2382 const u32 *ctx = clk_rst_suspend;
2383 u32 val;
2384
2385 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2386 val |= *ctx++;
2387 clk_writel(val, OSC_CTRL);
2388
2389 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2390 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2391 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2392 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2393 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2394 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2395 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2396 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2397 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2398 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2399 udelay(1000);
2400
2401 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2402 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2403 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2404
2405 clk_writel(*ctx++, tegra_clk_cclk.reg);
2406 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2407
2408 clk_writel(*ctx++, tegra_clk_sclk.reg);
2409 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2410 clk_writel(*ctx++, tegra_clk_pclk.reg);
2411
2412 clk_writel(*ctx++, tegra_clk_audio.reg);
2413
2414 /* enable all clocks before configuring clock sources */
2415 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2416 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2417 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2418 wmb();
2419
2420 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2421 off += 4) {
2422 if (off == PERIPH_CLK_SOURCE_EMC)
2423 continue;
2424 clk_writel(*ctx++, off);
2425 }
2426 wmb();
2427
2428 off = RST_DEVICES;
2429 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2430 clk_writel(*ctx++, off);
2431 wmb();
2432
2433 off = CLK_OUT_ENB;
2434 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2435 clk_writel(*ctx++, off);
2436 wmb();
2437
2438 clk_writel(*ctx++, MISC_CLK_ENB);
2439 clk_writel(*ctx++, CLK_MASK_ARM);
2440 }
2441 #endif
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