arch/arm/plat-mxc/avic.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <mach/common.h>
  24 #include <asm/mach/irq.h>
  25 #include <mach/hardware.h>
  26
  27 #include "irq-common.h"
  28
  29 #define AVIC_INTCNTL            0x00    /* int control reg */
  30 #define AVIC_NIMASK             0x04    /* int mask reg */
  31 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  32 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  33 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  34 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  35 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  36 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  37 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  38 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  39 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  40 #define AVIC_INTSRCH            0x48    /* int source reg high */
  41 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  42 #define AVIC_INTFRCH            0x50    /* int force reg high */
  43 #define AVIC_INTFRCL            0x54    /* int force reg low */
  44 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  45 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  46 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  47 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  48
  49 #define AVIC_NUM_IRQS 64
  50
  51 void __iomem *avic_base;
  52
  53 static u32 avic_saved_mask_reg[2];
  54
  55 #ifdef CONFIG_MXC_IRQ_PRIOR
  56 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
  57 {
  58         unsigned int temp;
  59         unsigned int mask = 0x0F << irq % 8 * 4;
  60
  61         if (irq >= AVIC_NUM_IRQS)
  62                 return -EINVAL;;
  63
  64         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
  65         temp &= ~mask;
  66         temp |= prio & mask;
  67
  68         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
  69
  70         return 0;
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_FIQ
  75 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
  76 {
  77         unsigned int irqt;
  78
  79         if (irq >= AVIC_NUM_IRQS)
  80                 return -EINVAL;
  81
  82         if (irq < AVIC_NUM_IRQS / 2) {
  83                 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
  84                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
  85         } else {
  86                 irq -= AVIC_NUM_IRQS / 2;
  87                 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
  88                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
  89         }
  90
  91         return 0;
  92 }
  93 #endif /* CONFIG_FIQ */
  94
  95
  96 static struct mxc_extra_irq avic_extra_irq = {
  97 #ifdef CONFIG_MXC_IRQ_PRIOR
  98         .set_priority = avic_irq_set_priority,
  99 #endif
 100 #ifdef CONFIG_FIQ
 101         .set_irq_fiq = avic_set_irq_fiq,
 102 #endif
 103 };
 104
 105 #ifdef CONFIG_PM
 106 static void avic_irq_suspend(struct irq_data *d)
 107 {
 108         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 109         struct irq_chip_type *ct = gc->chip_types;
 110         int idx = gc->irq_base >> 5;
 111
 112         avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
 113         __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
 114 }
 115
 116 static void avic_irq_resume(struct irq_data *d)
 117 {
 118         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 119         struct irq_chip_type *ct = gc->chip_types;
 120         int idx = gc->irq_base >> 5;
 121
 122         __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 123 }
 124
 125 #else
 126 #define avic_irq_suspend NULL
 127 #define avic_irq_resume NULL
 128 #endif
 129
 130 static __init void avic_init_gc(unsigned int irq_start)
 131 {
 132         struct irq_chip_generic *gc;
 133         struct irq_chip_type *ct;
 134         int idx = irq_start >> 5;
 135
 136         gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
 137                                     handle_level_irq);
 138         gc->private = &avic_extra_irq;
 139         gc->wake_enabled = IRQ_MSK(32);
 140
 141         ct = gc->chip_types;
 142         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 143         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 144         ct->chip.irq_ack = irq_gc_mask_clr_bit;
 145         ct->chip.irq_set_wake = irq_gc_set_wake;
 146         ct->chip.irq_suspend = avic_irq_suspend;
 147         ct->chip.irq_resume = avic_irq_resume;
 148         ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
 149         ct->regs.ack = ct->regs.mask;
 150
 151         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 152 }
 153
 154 asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
 155 {
 156         u32 nivector;
 157
 158         do {
 159                 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
 160                 if (nivector == 0xffff)
 161                         break;
 162
 163                 handle_IRQ(nivector, regs);
 164         } while (1);
 165 }
 166
 167 /*
 168  * This function initializes the AVIC hardware and disables all the
 169  * interrupts. It registers the interrupt enable and disable functions
 170  * to the kernel for each interrupt source.
 171  */
 172 void __init mxc_init_irq(void __iomem *irqbase)
 173 {
 174         int i;
 175
 176         avic_base = irqbase;
 177
 178         /* put the AVIC into the reset value with
 179          * all interrupts disabled
 180          */
 181         __raw_writel(0, avic_base + AVIC_INTCNTL);
 182         __raw_writel(0x1f, avic_base + AVIC_NIMASK);
 183
 184         /* disable all interrupts */
 185         __raw_writel(0, avic_base + AVIC_INTENABLEH);
 186         __raw_writel(0, avic_base + AVIC_INTENABLEL);
 187
 188         /* all IRQ no FIQ */
 189         __raw_writel(0, avic_base + AVIC_INTTYPEH);
 190         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 191
 192         for (i = 0; i < AVIC_NUM_IRQS; i += 32)
 193                 avic_init_gc(i);
 194
 195         /* Set default priority value (0) for all IRQ's */
 196         for (i = 0; i < 8; i++)
 197                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 198
 199 #ifdef CONFIG_FIQ
 200         /* Initialize FIQ */
 201         init_FIQ();
 202 #endif
 203
 204         printk(KERN_INFO "MXC IRQ initialized\n");
 205 }