arch/arm/plat-mxc/system.c

   1 /*
   2  * Copyright (C) 1999 ARM Limited
   3  * Copyright (C) 2000 Deep Blue Solutions Ltd
   4  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   6  * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/err.h>
  23 #include <linux/delay.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/common.h>
  27 #include <asm/proc-fns.h>
  28 #include <asm/system.h>
  29 #include <asm/mach-types.h>
  30
  31 void (*imx_idle)(void) = NULL;
  32 void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
  33
  34 static void __iomem *wdog_base;
  35
  36 /*
  37  * Reset the system. It is called by machine_restart().
  38  */
  39 void arch_reset(char mode, const char *cmd)
  40 {
  41         unsigned int wcr_enable;
  42
  43 #ifdef CONFIG_MACH_MX51_EFIKAMX
  44         if (machine_is_mx51_efikamx()) {
  45                 mx51_efikamx_reset();
  46                 return;
  47         }
  48 #endif
  49
  50         if (cpu_is_mx1()) {
  51                 wcr_enable = (1 << 0);
  52         } else {
  53                 struct clk *clk;
  54
  55                 clk = clk_get_sys("imx2-wdt.0", NULL);
  56                 if (!IS_ERR(clk))
  57                         clk_enable(clk);
  58                 wcr_enable = (1 << 2);
  59         }
  60
  61         /* Assert SRS signal */
  62         __raw_writew(wcr_enable, wdog_base);
  63
  64         /* wait for reset to assert... */
  65         mdelay(500);
  66
  67         printk(KERN_ERR "Watchdog reset failed to assert reset\n");
  68
  69         /* delay to allow the serial port to show the message */
  70         mdelay(50);
  71
  72         /* we'll take a jump through zero as a poor second */
  73         cpu_reset(0);
  74 }
  75
  76 void mxc_arch_reset_init(void __iomem *base)
  77 {
  78         wdog_base = base;
  79 }