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MIPS: Yosemite, Emma: Fix off-by-two in arcs_cmdline buffer size check
[linux-2.6/linux-mips.git] / arch / x86 / kernel / cpu / perf_event_intel.c
blobe09ca20e86eeaeba463b6e42b8bcf1c7a0adb78b
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #include <linux/stddef.h>
9 #include <linux/types.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12
13 #include <asm/hardirq.h>
14 #include <asm/apic.h>
15
16 #include "perf_event.h"
17
18 /*
19 * Intel PerfMon, used on Core and later.
20 */
21 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
22 {
23 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
24 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
25 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
26 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
27 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
28 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
29 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
30 };
31
32 static struct event_constraint intel_core_event_constraints[] __read_mostly =
33 {
34 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
35 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
36 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
37 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
38 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
39 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
40 EVENT_CONSTRAINT_END
41 };
42
43 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
44 {
45 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
46 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
47 /*
48 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
49 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
50 * ratio between these counters.
51 */
52 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64 };
65
66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
67 {
68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
70 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80 };
81
82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
83 {
84 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
85 EVENT_EXTRA_END
86 };
87
88 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
89 {
90 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
91 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
92 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
93 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
94 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
95 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
96 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
97 EVENT_CONSTRAINT_END
98 };
99
100 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
101 {
102 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
103 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
104 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
105 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
106 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
107 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
108 EVENT_CONSTRAINT_END
109 };
110
111 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
112 {
113 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
114 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
115 EVENT_EXTRA_END
116 };
117
118 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
119 {
120 EVENT_CONSTRAINT_END
121 };
122
123 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
124 {
125 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
126 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
127 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
128 EVENT_CONSTRAINT_END
129 };
130
131 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
132 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
133 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
134 EVENT_EXTRA_END
135 };
136
137 static u64 intel_pmu_event_map(int hw_event)
138 {
139 return intel_perfmon_event_map[hw_event];
140 }
141
142 static __initconst const u64 snb_hw_cache_event_ids
143 [PERF_COUNT_HW_CACHE_MAX]
144 [PERF_COUNT_HW_CACHE_OP_MAX]
145 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
146 {
147 [ C(L1D) ] = {
148 [ C(OP_READ) ] = {
149 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
150 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
151 },
152 [ C(OP_WRITE) ] = {
153 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
154 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
155 },
156 [ C(OP_PREFETCH) ] = {
157 [ C(RESULT_ACCESS) ] = 0x0,
158 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
159 },
160 },
161 [ C(L1I ) ] = {
162 [ C(OP_READ) ] = {
163 [ C(RESULT_ACCESS) ] = 0x0,
164 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
165 },
166 [ C(OP_WRITE) ] = {
167 [ C(RESULT_ACCESS) ] = -1,
168 [ C(RESULT_MISS) ] = -1,
169 },
170 [ C(OP_PREFETCH) ] = {
171 [ C(RESULT_ACCESS) ] = 0x0,
172 [ C(RESULT_MISS) ] = 0x0,
173 },
174 },
175 [ C(LL ) ] = {
176 [ C(OP_READ) ] = {
177 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
178 [ C(RESULT_ACCESS) ] = 0x01b7,
179 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
180 [ C(RESULT_MISS) ] = 0x01b7,
181 },
182 [ C(OP_WRITE) ] = {
183 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
184 [ C(RESULT_ACCESS) ] = 0x01b7,
185 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
186 [ C(RESULT_MISS) ] = 0x01b7,
187 },
188 [ C(OP_PREFETCH) ] = {
189 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
190 [ C(RESULT_ACCESS) ] = 0x01b7,
191 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
192 [ C(RESULT_MISS) ] = 0x01b7,
193 },
194 },
195 [ C(DTLB) ] = {
196 [ C(OP_READ) ] = {
197 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
198 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
199 },
200 [ C(OP_WRITE) ] = {
201 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
202 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
203 },
204 [ C(OP_PREFETCH) ] = {
205 [ C(RESULT_ACCESS) ] = 0x0,
206 [ C(RESULT_MISS) ] = 0x0,
207 },
208 },
209 [ C(ITLB) ] = {
210 [ C(OP_READ) ] = {
211 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
212 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
213 },
214 [ C(OP_WRITE) ] = {
215 [ C(RESULT_ACCESS) ] = -1,
216 [ C(RESULT_MISS) ] = -1,
217 },
218 [ C(OP_PREFETCH) ] = {
219 [ C(RESULT_ACCESS) ] = -1,
220 [ C(RESULT_MISS) ] = -1,
221 },
222 },
223 [ C(BPU ) ] = {
224 [ C(OP_READ) ] = {
225 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
226 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
227 },
228 [ C(OP_WRITE) ] = {
229 [ C(RESULT_ACCESS) ] = -1,
230 [ C(RESULT_MISS) ] = -1,
231 },
232 [ C(OP_PREFETCH) ] = {
233 [ C(RESULT_ACCESS) ] = -1,
234 [ C(RESULT_MISS) ] = -1,
235 },
236 },
237 [ C(NODE) ] = {
238 [ C(OP_READ) ] = {
239 [ C(RESULT_ACCESS) ] = -1,
240 [ C(RESULT_MISS) ] = -1,
241 },
242 [ C(OP_WRITE) ] = {
243 [ C(RESULT_ACCESS) ] = -1,
244 [ C(RESULT_MISS) ] = -1,
245 },
246 [ C(OP_PREFETCH) ] = {
247 [ C(RESULT_ACCESS) ] = -1,
248 [ C(RESULT_MISS) ] = -1,
249 },
250 },
251
252 };
253
254 static __initconst const u64 westmere_hw_cache_event_ids
255 [PERF_COUNT_HW_CACHE_MAX]
256 [PERF_COUNT_HW_CACHE_OP_MAX]
257 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
258 {
259 [ C(L1D) ] = {
260 [ C(OP_READ) ] = {
261 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
262 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
263 },
264 [ C(OP_WRITE) ] = {
265 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
266 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
267 },
268 [ C(OP_PREFETCH) ] = {
269 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
270 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
271 },
272 },
273 [ C(L1I ) ] = {
274 [ C(OP_READ) ] = {
275 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
276 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
277 },
278 [ C(OP_WRITE) ] = {
279 [ C(RESULT_ACCESS) ] = -1,
280 [ C(RESULT_MISS) ] = -1,
281 },
282 [ C(OP_PREFETCH) ] = {
283 [ C(RESULT_ACCESS) ] = 0x0,
284 [ C(RESULT_MISS) ] = 0x0,
285 },
286 },
287 [ C(LL ) ] = {
288 [ C(OP_READ) ] = {
289 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
290 [ C(RESULT_ACCESS) ] = 0x01b7,
291 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
292 [ C(RESULT_MISS) ] = 0x01b7,
293 },
294 /*
295 * Use RFO, not WRITEBACK, because a write miss would typically occur
296 * on RFO.
297 */
298 [ C(OP_WRITE) ] = {
299 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
300 [ C(RESULT_ACCESS) ] = 0x01b7,
301 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
302 [ C(RESULT_MISS) ] = 0x01b7,
303 },
304 [ C(OP_PREFETCH) ] = {
305 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
306 [ C(RESULT_ACCESS) ] = 0x01b7,
307 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
308 [ C(RESULT_MISS) ] = 0x01b7,
309 },
310 },
311 [ C(DTLB) ] = {
312 [ C(OP_READ) ] = {
313 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
314 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
315 },
316 [ C(OP_WRITE) ] = {
317 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
318 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
319 },
320 [ C(OP_PREFETCH) ] = {
321 [ C(RESULT_ACCESS) ] = 0x0,
322 [ C(RESULT_MISS) ] = 0x0,
323 },
324 },
325 [ C(ITLB) ] = {
326 [ C(OP_READ) ] = {
327 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
328 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
329 },
330 [ C(OP_WRITE) ] = {
331 [ C(RESULT_ACCESS) ] = -1,
332 [ C(RESULT_MISS) ] = -1,
333 },
334 [ C(OP_PREFETCH) ] = {
335 [ C(RESULT_ACCESS) ] = -1,
336 [ C(RESULT_MISS) ] = -1,
337 },
338 },
339 [ C(BPU ) ] = {
340 [ C(OP_READ) ] = {
341 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
342 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
343 },
344 [ C(OP_WRITE) ] = {
345 [ C(RESULT_ACCESS) ] = -1,
346 [ C(RESULT_MISS) ] = -1,
347 },
348 [ C(OP_PREFETCH) ] = {
349 [ C(RESULT_ACCESS) ] = -1,
350 [ C(RESULT_MISS) ] = -1,
351 },
352 },
353 [ C(NODE) ] = {
354 [ C(OP_READ) ] = {
355 [ C(RESULT_ACCESS) ] = 0x01b7,
356 [ C(RESULT_MISS) ] = 0x01b7,
357 },
358 [ C(OP_WRITE) ] = {
359 [ C(RESULT_ACCESS) ] = 0x01b7,
360 [ C(RESULT_MISS) ] = 0x01b7,
361 },
362 [ C(OP_PREFETCH) ] = {
363 [ C(RESULT_ACCESS) ] = 0x01b7,
364 [ C(RESULT_MISS) ] = 0x01b7,
365 },
366 },
367 };
368
369 /*
370 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
371 * See IA32 SDM Vol 3B 30.6.1.3
372 */
373
374 #define NHM_DMND_DATA_RD (1 << 0)
375 #define NHM_DMND_RFO (1 << 1)
376 #define NHM_DMND_IFETCH (1 << 2)
377 #define NHM_DMND_WB (1 << 3)
378 #define NHM_PF_DATA_RD (1 << 4)
379 #define NHM_PF_DATA_RFO (1 << 5)
380 #define NHM_PF_IFETCH (1 << 6)
381 #define NHM_OFFCORE_OTHER (1 << 7)
382 #define NHM_UNCORE_HIT (1 << 8)
383 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
384 #define NHM_OTHER_CORE_HITM (1 << 10)
385 /* reserved */
386 #define NHM_REMOTE_CACHE_FWD (1 << 12)
387 #define NHM_REMOTE_DRAM (1 << 13)
388 #define NHM_LOCAL_DRAM (1 << 14)
389 #define NHM_NON_DRAM (1 << 15)
390
391 #define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
392
393 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
394 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
395 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
396
397 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
398 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
399 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
400
401 static __initconst const u64 nehalem_hw_cache_extra_regs
402 [PERF_COUNT_HW_CACHE_MAX]
403 [PERF_COUNT_HW_CACHE_OP_MAX]
404 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
405 {
406 [ C(LL ) ] = {
407 [ C(OP_READ) ] = {
408 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
409 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
410 },
411 [ C(OP_WRITE) ] = {
412 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
413 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
414 },
415 [ C(OP_PREFETCH) ] = {
416 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
417 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
418 },
419 },
420 [ C(NODE) ] = {
421 [ C(OP_READ) ] = {
422 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
423 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
424 },
425 [ C(OP_WRITE) ] = {
426 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
427 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
428 },
429 [ C(OP_PREFETCH) ] = {
430 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
431 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
432 },
433 },
434 };
435
436 static __initconst const u64 nehalem_hw_cache_event_ids
437 [PERF_COUNT_HW_CACHE_MAX]
438 [PERF_COUNT_HW_CACHE_OP_MAX]
439 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
440 {
441 [ C(L1D) ] = {
442 [ C(OP_READ) ] = {
443 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
444 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
445 },
446 [ C(OP_WRITE) ] = {
447 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
448 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
449 },
450 [ C(OP_PREFETCH) ] = {
451 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
452 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
453 },
454 },
455 [ C(L1I ) ] = {
456 [ C(OP_READ) ] = {
457 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
458 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
459 },
460 [ C(OP_WRITE) ] = {
461 [ C(RESULT_ACCESS) ] = -1,
462 [ C(RESULT_MISS) ] = -1,
463 },
464 [ C(OP_PREFETCH) ] = {
465 [ C(RESULT_ACCESS) ] = 0x0,
466 [ C(RESULT_MISS) ] = 0x0,
467 },
468 },
469 [ C(LL ) ] = {
470 [ C(OP_READ) ] = {
471 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
472 [ C(RESULT_ACCESS) ] = 0x01b7,
473 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
474 [ C(RESULT_MISS) ] = 0x01b7,
475 },
476 /*
477 * Use RFO, not WRITEBACK, because a write miss would typically occur
478 * on RFO.
479 */
480 [ C(OP_WRITE) ] = {
481 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
482 [ C(RESULT_ACCESS) ] = 0x01b7,
483 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
484 [ C(RESULT_MISS) ] = 0x01b7,
485 },
486 [ C(OP_PREFETCH) ] = {
487 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
488 [ C(RESULT_ACCESS) ] = 0x01b7,
489 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
490 [ C(RESULT_MISS) ] = 0x01b7,
491 },
492 },
493 [ C(DTLB) ] = {
494 [ C(OP_READ) ] = {
495 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
496 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
497 },
498 [ C(OP_WRITE) ] = {
499 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
500 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
501 },
502 [ C(OP_PREFETCH) ] = {
503 [ C(RESULT_ACCESS) ] = 0x0,
504 [ C(RESULT_MISS) ] = 0x0,
505 },
506 },
507 [ C(ITLB) ] = {
508 [ C(OP_READ) ] = {
509 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
510 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
511 },
512 [ C(OP_WRITE) ] = {
513 [ C(RESULT_ACCESS) ] = -1,
514 [ C(RESULT_MISS) ] = -1,
515 },
516 [ C(OP_PREFETCH) ] = {
517 [ C(RESULT_ACCESS) ] = -1,
518 [ C(RESULT_MISS) ] = -1,
519 },
520 },
521 [ C(BPU ) ] = {
522 [ C(OP_READ) ] = {
523 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
524 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
525 },
526 [ C(OP_WRITE) ] = {
527 [ C(RESULT_ACCESS) ] = -1,
528 [ C(RESULT_MISS) ] = -1,
529 },
530 [ C(OP_PREFETCH) ] = {
531 [ C(RESULT_ACCESS) ] = -1,
532 [ C(RESULT_MISS) ] = -1,
533 },
534 },
535 [ C(NODE) ] = {
536 [ C(OP_READ) ] = {
537 [ C(RESULT_ACCESS) ] = 0x01b7,
538 [ C(RESULT_MISS) ] = 0x01b7,
539 },
540 [ C(OP_WRITE) ] = {
541 [ C(RESULT_ACCESS) ] = 0x01b7,
542 [ C(RESULT_MISS) ] = 0x01b7,
543 },
544 [ C(OP_PREFETCH) ] = {
545 [ C(RESULT_ACCESS) ] = 0x01b7,
546 [ C(RESULT_MISS) ] = 0x01b7,
547 },
548 },
549 };
550
551 static __initconst const u64 core2_hw_cache_event_ids
552 [PERF_COUNT_HW_CACHE_MAX]
553 [PERF_COUNT_HW_CACHE_OP_MAX]
554 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
555 {
556 [ C(L1D) ] = {
557 [ C(OP_READ) ] = {
558 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
559 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
560 },
561 [ C(OP_WRITE) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
563 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
564 },
565 [ C(OP_PREFETCH) ] = {
566 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
567 [ C(RESULT_MISS) ] = 0,
568 },
569 },
570 [ C(L1I ) ] = {
571 [ C(OP_READ) ] = {
572 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
573 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
574 },
575 [ C(OP_WRITE) ] = {
576 [ C(RESULT_ACCESS) ] = -1,
577 [ C(RESULT_MISS) ] = -1,
578 },
579 [ C(OP_PREFETCH) ] = {
580 [ C(RESULT_ACCESS) ] = 0,
581 [ C(RESULT_MISS) ] = 0,
582 },
583 },
584 [ C(LL ) ] = {
585 [ C(OP_READ) ] = {
586 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
587 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
588 },
589 [ C(OP_WRITE) ] = {
590 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
591 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
592 },
593 [ C(OP_PREFETCH) ] = {
594 [ C(RESULT_ACCESS) ] = 0,
595 [ C(RESULT_MISS) ] = 0,
596 },
597 },
598 [ C(DTLB) ] = {
599 [ C(OP_READ) ] = {
600 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
601 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
602 },
603 [ C(OP_WRITE) ] = {
604 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
605 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
606 },
607 [ C(OP_PREFETCH) ] = {
608 [ C(RESULT_ACCESS) ] = 0,
609 [ C(RESULT_MISS) ] = 0,
610 },
611 },
612 [ C(ITLB) ] = {
613 [ C(OP_READ) ] = {
614 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
615 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
616 },
617 [ C(OP_WRITE) ] = {
618 [ C(RESULT_ACCESS) ] = -1,
619 [ C(RESULT_MISS) ] = -1,
620 },
621 [ C(OP_PREFETCH) ] = {
622 [ C(RESULT_ACCESS) ] = -1,
623 [ C(RESULT_MISS) ] = -1,
624 },
625 },
626 [ C(BPU ) ] = {
627 [ C(OP_READ) ] = {
628 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
629 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
630 },
631 [ C(OP_WRITE) ] = {
632 [ C(RESULT_ACCESS) ] = -1,
633 [ C(RESULT_MISS) ] = -1,
634 },
635 [ C(OP_PREFETCH) ] = {
636 [ C(RESULT_ACCESS) ] = -1,
637 [ C(RESULT_MISS) ] = -1,
638 },
639 },
640 };
641
642 static __initconst const u64 atom_hw_cache_event_ids
643 [PERF_COUNT_HW_CACHE_MAX]
644 [PERF_COUNT_HW_CACHE_OP_MAX]
645 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
646 {
647 [ C(L1D) ] = {
648 [ C(OP_READ) ] = {
649 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
650 [ C(RESULT_MISS) ] = 0,
651 },
652 [ C(OP_WRITE) ] = {
653 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
654 [ C(RESULT_MISS) ] = 0,
655 },
656 [ C(OP_PREFETCH) ] = {
657 [ C(RESULT_ACCESS) ] = 0x0,
658 [ C(RESULT_MISS) ] = 0,
659 },
660 },
661 [ C(L1I ) ] = {
662 [ C(OP_READ) ] = {
663 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
664 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
665 },
666 [ C(OP_WRITE) ] = {
667 [ C(RESULT_ACCESS) ] = -1,
668 [ C(RESULT_MISS) ] = -1,
669 },
670 [ C(OP_PREFETCH) ] = {
671 [ C(RESULT_ACCESS) ] = 0,
672 [ C(RESULT_MISS) ] = 0,
673 },
674 },
675 [ C(LL ) ] = {
676 [ C(OP_READ) ] = {
677 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
678 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
679 },
680 [ C(OP_WRITE) ] = {
681 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
682 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
683 },
684 [ C(OP_PREFETCH) ] = {
685 [ C(RESULT_ACCESS) ] = 0,
686 [ C(RESULT_MISS) ] = 0,
687 },
688 },
689 [ C(DTLB) ] = {
690 [ C(OP_READ) ] = {
691 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
692 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
693 },
694 [ C(OP_WRITE) ] = {
695 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
696 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
697 },
698 [ C(OP_PREFETCH) ] = {
699 [ C(RESULT_ACCESS) ] = 0,
700 [ C(RESULT_MISS) ] = 0,
701 },
702 },
703 [ C(ITLB) ] = {
704 [ C(OP_READ) ] = {
705 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
706 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
707 },
708 [ C(OP_WRITE) ] = {
709 [ C(RESULT_ACCESS) ] = -1,
710 [ C(RESULT_MISS) ] = -1,
711 },
712 [ C(OP_PREFETCH) ] = {
713 [ C(RESULT_ACCESS) ] = -1,
714 [ C(RESULT_MISS) ] = -1,
715 },
716 },
717 [ C(BPU ) ] = {
718 [ C(OP_READ) ] = {
719 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
720 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
721 },
722 [ C(OP_WRITE) ] = {
723 [ C(RESULT_ACCESS) ] = -1,
724 [ C(RESULT_MISS) ] = -1,
725 },
726 [ C(OP_PREFETCH) ] = {
727 [ C(RESULT_ACCESS) ] = -1,
728 [ C(RESULT_MISS) ] = -1,
729 },
730 },
731 };
732
733 static void intel_pmu_disable_all(void)
734 {
735 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
736
737 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
738
739 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
740 intel_pmu_disable_bts();
741
742 intel_pmu_pebs_disable_all();
743 intel_pmu_lbr_disable_all();
744 }
745
746 static void intel_pmu_enable_all(int added)
747 {
748 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
749
750 intel_pmu_pebs_enable_all();
751 intel_pmu_lbr_enable_all();
752 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
753 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
754
755 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
756 struct perf_event *event =
757 cpuc->events[X86_PMC_IDX_FIXED_BTS];
758
759 if (WARN_ON_ONCE(!event))
760 return;
761
762 intel_pmu_enable_bts(event->hw.config);
763 }
764 }
765
766 /*
767 * Workaround for:
768 * Intel Errata AAK100 (model 26)
769 * Intel Errata AAP53 (model 30)
770 * Intel Errata BD53 (model 44)
771 *
772 * The official story:
773 * These chips need to be 'reset' when adding counters by programming the
774 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
775 * in sequence on the same PMC or on different PMCs.
776 *
777 * In practise it appears some of these events do in fact count, and
778 * we need to programm all 4 events.
779 */
780 static void intel_pmu_nhm_workaround(void)
781 {
782 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
783 static const unsigned long nhm_magic[4] = {
784 0x4300B5,
785 0x4300D2,
786 0x4300B1,
787 0x4300B1
788 };
789 struct perf_event *event;
790 int i;
791
792 /*
793 * The Errata requires below steps:
794 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
795 * 2) Configure 4 PERFEVTSELx with the magic events and clear
796 * the corresponding PMCx;
797 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
798 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
799 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
800 */
801
802 /*
803 * The real steps we choose are a little different from above.
804 * A) To reduce MSR operations, we don't run step 1) as they
805 * are already cleared before this function is called;
806 * B) Call x86_perf_event_update to save PMCx before configuring
807 * PERFEVTSELx with magic number;
808 * C) With step 5), we do clear only when the PERFEVTSELx is
809 * not used currently.
810 * D) Call x86_perf_event_set_period to restore PMCx;
811 */
812
813 /* We always operate 4 pairs of PERF Counters */
814 for (i = 0; i < 4; i++) {
815 event = cpuc->events[i];
816 if (event)
817 x86_perf_event_update(event);
818 }
819
820 for (i = 0; i < 4; i++) {
821 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
822 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
823 }
824
825 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
826 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
827
828 for (i = 0; i < 4; i++) {
829 event = cpuc->events[i];
830
831 if (event) {
832 x86_perf_event_set_period(event);
833 __x86_pmu_enable_event(&event->hw,
834 ARCH_PERFMON_EVENTSEL_ENABLE);
835 } else
836 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
837 }
838 }
839
840 static void intel_pmu_nhm_enable_all(int added)
841 {
842 if (added)
843 intel_pmu_nhm_workaround();
844 intel_pmu_enable_all(added);
845 }
846
847 static inline u64 intel_pmu_get_status(void)
848 {
849 u64 status;
850
851 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
852
853 return status;
854 }
855
856 static inline void intel_pmu_ack_status(u64 ack)
857 {
858 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
859 }
860
861 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
862 {
863 int idx = hwc->idx - X86_PMC_IDX_FIXED;
864 u64 ctrl_val, mask;
865
866 mask = 0xfULL << (idx * 4);
867
868 rdmsrl(hwc->config_base, ctrl_val);
869 ctrl_val &= ~mask;
870 wrmsrl(hwc->config_base, ctrl_val);
871 }
872
873 static void intel_pmu_disable_event(struct perf_event *event)
874 {
875 struct hw_perf_event *hwc = &event->hw;
876 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
877
878 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
879 intel_pmu_disable_bts();
880 intel_pmu_drain_bts_buffer();
881 return;
882 }
883
884 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
885 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
886
887 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
888 intel_pmu_disable_fixed(hwc);
889 return;
890 }
891
892 x86_pmu_disable_event(event);
893
894 if (unlikely(event->attr.precise_ip))
895 intel_pmu_pebs_disable(event);
896 }
897
898 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
899 {
900 int idx = hwc->idx - X86_PMC_IDX_FIXED;
901 u64 ctrl_val, bits, mask;
902
903 /*
904 * Enable IRQ generation (0x8),
905 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
906 * if requested:
907 */
908 bits = 0x8ULL;
909 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
910 bits |= 0x2;
911 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
912 bits |= 0x1;
913
914 /*
915 * ANY bit is supported in v3 and up
916 */
917 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
918 bits |= 0x4;
919
920 bits <<= (idx * 4);
921 mask = 0xfULL << (idx * 4);
922
923 rdmsrl(hwc->config_base, ctrl_val);
924 ctrl_val &= ~mask;
925 ctrl_val |= bits;
926 wrmsrl(hwc->config_base, ctrl_val);
927 }
928
929 static void intel_pmu_enable_event(struct perf_event *event)
930 {
931 struct hw_perf_event *hwc = &event->hw;
932 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
933
934 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
935 if (!__this_cpu_read(cpu_hw_events.enabled))
936 return;
937
938 intel_pmu_enable_bts(hwc->config);
939 return;
940 }
941
942 if (event->attr.exclude_host)
943 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
944 if (event->attr.exclude_guest)
945 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
946
947 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
948 intel_pmu_enable_fixed(hwc);
949 return;
950 }
951
952 if (unlikely(event->attr.precise_ip))
953 intel_pmu_pebs_enable(event);
954
955 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
956 }
957
958 /*
959 * Save and restart an expired event. Called by NMI contexts,
960 * so it has to be careful about preempting normal event ops:
961 */
962 int intel_pmu_save_and_restart(struct perf_event *event)
963 {
964 x86_perf_event_update(event);
965 return x86_perf_event_set_period(event);
966 }
967
968 static void intel_pmu_reset(void)
969 {
970 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
971 unsigned long flags;
972 int idx;
973
974 if (!x86_pmu.num_counters)
975 return;
976
977 local_irq_save(flags);
978
979 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
980
981 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
982 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
983 checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
984 }
985 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
986 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
987
988 if (ds)
989 ds->bts_index = ds->bts_buffer_base;
990
991 local_irq_restore(flags);
992 }
993
994 /*
995 * This handler is triggered by the local APIC, so the APIC IRQ handling
996 * rules apply:
997 */
998 static int intel_pmu_handle_irq(struct pt_regs *regs)
999 {
1000 struct perf_sample_data data;
1001 struct cpu_hw_events *cpuc;
1002 int bit, loops;
1003 u64 status;
1004 int handled;
1005
1006 perf_sample_data_init(&data, 0);
1007
1008 cpuc = &__get_cpu_var(cpu_hw_events);
1009
1010 /*
1011 * Some chipsets need to unmask the LVTPC in a particular spot
1012 * inside the nmi handler. As a result, the unmasking was pushed
1013 * into all the nmi handlers.
1014 *
1015 * This handler doesn't seem to have any issues with the unmasking
1016 * so it was left at the top.
1017 */
1018 apic_write(APIC_LVTPC, APIC_DM_NMI);
1019
1020 intel_pmu_disable_all();
1021 handled = intel_pmu_drain_bts_buffer();
1022 status = intel_pmu_get_status();
1023 if (!status) {
1024 intel_pmu_enable_all(0);
1025 return handled;
1026 }
1027
1028 loops = 0;
1029 again:
1030 intel_pmu_ack_status(status);
1031 if (++loops > 100) {
1032 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1033 perf_event_print_debug();
1034 intel_pmu_reset();
1035 goto done;
1036 }
1037
1038 inc_irq_stat(apic_perf_irqs);
1039
1040 intel_pmu_lbr_read();
1041
1042 /*
1043 * PEBS overflow sets bit 62 in the global status register
1044 */
1045 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1046 handled++;
1047 x86_pmu.drain_pebs(regs);
1048 }
1049
1050 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1051 struct perf_event *event = cpuc->events[bit];
1052
1053 handled++;
1054
1055 if (!test_bit(bit, cpuc->active_mask))
1056 continue;
1057
1058 if (!intel_pmu_save_and_restart(event))
1059 continue;
1060
1061 data.period = event->hw.last_period;
1062
1063 if (perf_event_overflow(event, &data, regs))
1064 x86_pmu_stop(event, 0);
1065 }
1066
1067 /*
1068 * Repeat if there is more work to be done:
1069 */
1070 status = intel_pmu_get_status();
1071 if (status)
1072 goto again;
1073
1074 done:
1075 intel_pmu_enable_all(0);
1076 return handled;
1077 }
1078
1079 static struct event_constraint *
1080 intel_bts_constraints(struct perf_event *event)
1081 {
1082 struct hw_perf_event *hwc = &event->hw;
1083 unsigned int hw_event, bts_event;
1084
1085 if (event->attr.freq)
1086 return NULL;
1087
1088 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1089 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1090
1091 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1092 return &bts_constraint;
1093
1094 return NULL;
1095 }
1096
1097 static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
1098 {
1099 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1100 return false;
1101
1102 if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
1103 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1104 event->hw.config |= 0x01bb;
1105 event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
1106 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1107 } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
1108 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1109 event->hw.config |= 0x01b7;
1110 event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
1111 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1112 }
1113
1114 if (event->hw.extra_reg.idx == orig_idx)
1115 return false;
1116
1117 return true;
1118 }
1119
1120 /*
1121 * manage allocation of shared extra msr for certain events
1122 *
1123 * sharing can be:
1124 * per-cpu: to be shared between the various events on a single PMU
1125 * per-core: per-cpu + shared by HT threads
1126 */
1127 static struct event_constraint *
1128 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1129 struct perf_event *event)
1130 {
1131 struct event_constraint *c = &emptyconstraint;
1132 struct hw_perf_event_extra *reg = &event->hw.extra_reg;
1133 struct er_account *era;
1134 unsigned long flags;
1135 int orig_idx = reg->idx;
1136
1137 /* already allocated shared msr */
1138 if (reg->alloc)
1139 return &unconstrained;
1140
1141 again:
1142 era = &cpuc->shared_regs->regs[reg->idx];
1143 /*
1144 * we use spin_lock_irqsave() to avoid lockdep issues when
1145 * passing a fake cpuc
1146 */
1147 raw_spin_lock_irqsave(&era->lock, flags);
1148
1149 if (!atomic_read(&era->ref) || era->config == reg->config) {
1150
1151 /* lock in msr value */
1152 era->config = reg->config;
1153 era->reg = reg->reg;
1154
1155 /* one more user */
1156 atomic_inc(&era->ref);
1157
1158 /* no need to reallocate during incremental event scheduling */
1159 reg->alloc = 1;
1160
1161 /*
1162 * All events using extra_reg are unconstrained.
1163 * Avoids calling x86_get_event_constraints()
1164 *
1165 * Must revisit if extra_reg controlling events
1166 * ever have constraints. Worst case we go through
1167 * the regular event constraint table.
1168 */
1169 c = &unconstrained;
1170 } else if (intel_try_alt_er(event, orig_idx)) {
1171 raw_spin_unlock(&era->lock);
1172 goto again;
1173 }
1174 raw_spin_unlock_irqrestore(&era->lock, flags);
1175
1176 return c;
1177 }
1178
1179 static void
1180 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1181 struct hw_perf_event_extra *reg)
1182 {
1183 struct er_account *era;
1184
1185 /*
1186 * only put constraint if extra reg was actually
1187 * allocated. Also takes care of event which do
1188 * not use an extra shared reg
1189 */
1190 if (!reg->alloc)
1191 return;
1192
1193 era = &cpuc->shared_regs->regs[reg->idx];
1194
1195 /* one fewer user */
1196 atomic_dec(&era->ref);
1197
1198 /* allocate again next time */
1199 reg->alloc = 0;
1200 }
1201
1202 static struct event_constraint *
1203 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1204 struct perf_event *event)
1205 {
1206 struct event_constraint *c = NULL;
1207
1208 if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
1209 c = __intel_shared_reg_get_constraints(cpuc, event);
1210
1211 return c;
1212 }
1213
1214 struct event_constraint *
1215 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1216 {
1217 struct event_constraint *c;
1218
1219 if (x86_pmu.event_constraints) {
1220 for_each_event_constraint(c, x86_pmu.event_constraints) {
1221 if ((event->hw.config & c->cmask) == c->code)
1222 return c;
1223 }
1224 }
1225
1226 return &unconstrained;
1227 }
1228
1229 static struct event_constraint *
1230 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1231 {
1232 struct event_constraint *c;
1233
1234 c = intel_bts_constraints(event);
1235 if (c)
1236 return c;
1237
1238 c = intel_pebs_constraints(event);
1239 if (c)
1240 return c;
1241
1242 c = intel_shared_regs_constraints(cpuc, event);
1243 if (c)
1244 return c;
1245
1246 return x86_get_event_constraints(cpuc, event);
1247 }
1248
1249 static void
1250 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1251 struct perf_event *event)
1252 {
1253 struct hw_perf_event_extra *reg;
1254
1255 reg = &event->hw.extra_reg;
1256 if (reg->idx != EXTRA_REG_NONE)
1257 __intel_shared_reg_put_constraints(cpuc, reg);
1258 }
1259
1260 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1261 struct perf_event *event)
1262 {
1263 intel_put_shared_regs_event_constraints(cpuc, event);
1264 }
1265
1266 static int intel_pmu_hw_config(struct perf_event *event)
1267 {
1268 int ret = x86_pmu_hw_config(event);
1269
1270 if (ret)
1271 return ret;
1272
1273 if (event->attr.precise_ip &&
1274 (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1275 /*
1276 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1277 * (0x003c) so that we can use it with PEBS.
1278 *
1279 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1280 * PEBS capable. However we can use INST_RETIRED.ANY_P
1281 * (0x00c0), which is a PEBS capable event, to get the same
1282 * count.
1283 *
1284 * INST_RETIRED.ANY_P counts the number of cycles that retires
1285 * CNTMASK instructions. By setting CNTMASK to a value (16)
1286 * larger than the maximum number of instructions that can be
1287 * retired per cycle (4) and then inverting the condition, we
1288 * count all cycles that retire 16 or less instructions, which
1289 * is every cycle.
1290 *
1291 * Thereby we gain a PEBS capable cycle counter.
1292 */
1293 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
1294
1295 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1296 event->hw.config = alt_config;
1297 }
1298
1299 if (event->attr.type != PERF_TYPE_RAW)
1300 return 0;
1301
1302 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1303 return 0;
1304
1305 if (x86_pmu.version < 3)
1306 return -EINVAL;
1307
1308 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1309 return -EACCES;
1310
1311 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1312
1313 return 0;
1314 }
1315
1316 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1317 {
1318 if (x86_pmu.guest_get_msrs)
1319 return x86_pmu.guest_get_msrs(nr);
1320 *nr = 0;
1321 return NULL;
1322 }
1323 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1324
1325 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1326 {
1327 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1328 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1329
1330 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1331 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1332 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1333
1334 *nr = 1;
1335 return arr;
1336 }
1337
1338 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1339 {
1340 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1341 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1342 int idx;
1343
1344 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1345 struct perf_event *event = cpuc->events[idx];
1346
1347 arr[idx].msr = x86_pmu_config_addr(idx);
1348 arr[idx].host = arr[idx].guest = 0;
1349
1350 if (!test_bit(idx, cpuc->active_mask))
1351 continue;
1352
1353 arr[idx].host = arr[idx].guest =
1354 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1355
1356 if (event->attr.exclude_host)
1357 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1358 else if (event->attr.exclude_guest)
1359 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1360 }
1361
1362 *nr = x86_pmu.num_counters;
1363 return arr;
1364 }
1365
1366 static void core_pmu_enable_event(struct perf_event *event)
1367 {
1368 if (!event->attr.exclude_host)
1369 x86_pmu_enable_event(event);
1370 }
1371
1372 static void core_pmu_enable_all(int added)
1373 {
1374 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1375 int idx;
1376
1377 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1378 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1379
1380 if (!test_bit(idx, cpuc->active_mask) ||
1381 cpuc->events[idx]->attr.exclude_host)
1382 continue;
1383
1384 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1385 }
1386 }
1387
1388 static __initconst const struct x86_pmu core_pmu = {
1389 .name = "core",
1390 .handle_irq = x86_pmu_handle_irq,
1391 .disable_all = x86_pmu_disable_all,
1392 .enable_all = core_pmu_enable_all,
1393 .enable = core_pmu_enable_event,
1394 .disable = x86_pmu_disable_event,
1395 .hw_config = x86_pmu_hw_config,
1396 .schedule_events = x86_schedule_events,
1397 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1398 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1399 .event_map = intel_pmu_event_map,
1400 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1401 .apic = 1,
1402 /*
1403 * Intel PMCs cannot be accessed sanely above 32 bit width,
1404 * so we install an artificial 1<<31 period regardless of
1405 * the generic event period:
1406 */
1407 .max_period = (1ULL << 31) - 1,
1408 .get_event_constraints = intel_get_event_constraints,
1409 .put_event_constraints = intel_put_event_constraints,
1410 .event_constraints = intel_core_event_constraints,
1411 .guest_get_msrs = core_guest_get_msrs,
1412 };
1413
1414 struct intel_shared_regs *allocate_shared_regs(int cpu)
1415 {
1416 struct intel_shared_regs *regs;
1417 int i;
1418
1419 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1420 GFP_KERNEL, cpu_to_node(cpu));
1421 if (regs) {
1422 /*
1423 * initialize the locks to keep lockdep happy
1424 */
1425 for (i = 0; i < EXTRA_REG_MAX; i++)
1426 raw_spin_lock_init(&regs->regs[i].lock);
1427
1428 regs->core_id = -1;
1429 }
1430 return regs;
1431 }
1432
1433 static int intel_pmu_cpu_prepare(int cpu)
1434 {
1435 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1436
1437 if (!x86_pmu.extra_regs)
1438 return NOTIFY_OK;
1439
1440 cpuc->shared_regs = allocate_shared_regs(cpu);
1441 if (!cpuc->shared_regs)
1442 return NOTIFY_BAD;
1443
1444 return NOTIFY_OK;
1445 }
1446
1447 static void intel_pmu_cpu_starting(int cpu)
1448 {
1449 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1450 int core_id = topology_core_id(cpu);
1451 int i;
1452
1453 init_debug_store_on_cpu(cpu);
1454 /*
1455 * Deal with CPUs that don't clear their LBRs on power-up.
1456 */
1457 intel_pmu_lbr_reset();
1458
1459 if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
1460 return;
1461
1462 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1463 struct intel_shared_regs *pc;
1464
1465 pc = per_cpu(cpu_hw_events, i).shared_regs;
1466 if (pc && pc->core_id == core_id) {
1467 cpuc->kfree_on_online = cpuc->shared_regs;
1468 cpuc->shared_regs = pc;
1469 break;
1470 }
1471 }
1472
1473 cpuc->shared_regs->core_id = core_id;
1474 cpuc->shared_regs->refcnt++;
1475 }
1476
1477 static void intel_pmu_cpu_dying(int cpu)
1478 {
1479 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1480 struct intel_shared_regs *pc;
1481
1482 pc = cpuc->shared_regs;
1483 if (pc) {
1484 if (pc->core_id == -1 || --pc->refcnt == 0)
1485 kfree(pc);
1486 cpuc->shared_regs = NULL;
1487 }
1488
1489 fini_debug_store_on_cpu(cpu);
1490 }
1491
1492 static __initconst const struct x86_pmu intel_pmu = {
1493 .name = "Intel",
1494 .handle_irq = intel_pmu_handle_irq,
1495 .disable_all = intel_pmu_disable_all,
1496 .enable_all = intel_pmu_enable_all,
1497 .enable = intel_pmu_enable_event,
1498 .disable = intel_pmu_disable_event,
1499 .hw_config = intel_pmu_hw_config,
1500 .schedule_events = x86_schedule_events,
1501 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1502 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1503 .event_map = intel_pmu_event_map,
1504 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1505 .apic = 1,
1506 /*
1507 * Intel PMCs cannot be accessed sanely above 32 bit width,
1508 * so we install an artificial 1<<31 period regardless of
1509 * the generic event period:
1510 */
1511 .max_period = (1ULL << 31) - 1,
1512 .get_event_constraints = intel_get_event_constraints,
1513 .put_event_constraints = intel_put_event_constraints,
1514
1515 .cpu_prepare = intel_pmu_cpu_prepare,
1516 .cpu_starting = intel_pmu_cpu_starting,
1517 .cpu_dying = intel_pmu_cpu_dying,
1518 .guest_get_msrs = intel_guest_get_msrs,
1519 };
1520
1521 static void intel_clovertown_quirks(void)
1522 {
1523 /*
1524 * PEBS is unreliable due to:
1525 *
1526 * AJ67 - PEBS may experience CPL leaks
1527 * AJ68 - PEBS PMI may be delayed by one event
1528 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1529 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1530 *
1531 * AJ67 could be worked around by restricting the OS/USR flags.
1532 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1533 *
1534 * AJ106 could possibly be worked around by not allowing LBR
1535 * usage from PEBS, including the fixup.
1536 * AJ68 could possibly be worked around by always programming
1537 * a pebs_event_reset[0] value and coping with the lost events.
1538 *
1539 * But taken together it might just make sense to not enable PEBS on
1540 * these chips.
1541 */
1542 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1543 x86_pmu.pebs = 0;
1544 x86_pmu.pebs_constraints = NULL;
1545 }
1546
1547 __init int intel_pmu_init(void)
1548 {
1549 union cpuid10_edx edx;
1550 union cpuid10_eax eax;
1551 unsigned int unused;
1552 unsigned int ebx;
1553 int version;
1554
1555 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1556 switch (boot_cpu_data.x86) {
1557 case 0x6:
1558 return p6_pmu_init();
1559 case 0xf:
1560 return p4_pmu_init();
1561 }
1562 return -ENODEV;
1563 }
1564
1565 /*
1566 * Check whether the Architectural PerfMon supports
1567 * Branch Misses Retired hw_event or not.
1568 */
1569 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1570 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1571 return -ENODEV;
1572
1573 version = eax.split.version_id;
1574 if (version < 2)
1575 x86_pmu = core_pmu;
1576 else
1577 x86_pmu = intel_pmu;
1578
1579 x86_pmu.version = version;
1580 x86_pmu.num_counters = eax.split.num_counters;
1581 x86_pmu.cntval_bits = eax.split.bit_width;
1582 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
1583
1584 /*
1585 * Quirk: v2 perfmon does not report fixed-purpose events, so
1586 * assume at least 3 events:
1587 */
1588 if (version > 1)
1589 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1590
1591 /*
1592 * v2 and above have a perf capabilities MSR
1593 */
1594 if (version > 1) {
1595 u64 capabilities;
1596
1597 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1598 x86_pmu.intel_cap.capabilities = capabilities;
1599 }
1600
1601 intel_ds_init();
1602
1603 /*
1604 * Install the hw-cache-events table:
1605 */
1606 switch (boot_cpu_data.x86_model) {
1607 case 14: /* 65 nm core solo/duo, "Yonah" */
1608 pr_cont("Core events, ");
1609 break;
1610
1611 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1612 x86_pmu.quirks = intel_clovertown_quirks;
1613 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1614 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1615 case 29: /* six-core 45 nm xeon "Dunnington" */
1616 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1617 sizeof(hw_cache_event_ids));
1618
1619 intel_pmu_lbr_init_core();
1620
1621 x86_pmu.event_constraints = intel_core2_event_constraints;
1622 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
1623 pr_cont("Core2 events, ");
1624 break;
1625
1626 case 26: /* 45 nm nehalem, "Bloomfield" */
1627 case 30: /* 45 nm nehalem, "Lynnfield" */
1628 case 46: /* 45 nm nehalem-ex, "Beckton" */
1629 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1630 sizeof(hw_cache_event_ids));
1631 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1632 sizeof(hw_cache_extra_regs));
1633
1634 intel_pmu_lbr_init_nhm();
1635
1636 x86_pmu.event_constraints = intel_nehalem_event_constraints;
1637 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
1638 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1639 x86_pmu.extra_regs = intel_nehalem_extra_regs;
1640
1641 /* UOPS_ISSUED.STALLED_CYCLES */
1642 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1643 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1644 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1645
1646 if (ebx & 0x40) {
1647 /*
1648 * Erratum AAJ80 detected, we work it around by using
1649 * the BR_MISP_EXEC.ANY event. This will over-count
1650 * branch-misses, but it's still much better than the
1651 * architectural event which is often completely bogus:
1652 */
1653 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1654
1655 pr_cont("erratum AAJ80 worked around, ");
1656 }
1657 pr_cont("Nehalem events, ");
1658 break;
1659
1660 case 28: /* Atom */
1661 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1662 sizeof(hw_cache_event_ids));
1663
1664 intel_pmu_lbr_init_atom();
1665
1666 x86_pmu.event_constraints = intel_gen_event_constraints;
1667 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
1668 pr_cont("Atom events, ");
1669 break;
1670
1671 case 37: /* 32 nm nehalem, "Clarkdale" */
1672 case 44: /* 32 nm nehalem, "Gulftown" */
1673 case 47: /* 32 nm Xeon E7 */
1674 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1675 sizeof(hw_cache_event_ids));
1676 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1677 sizeof(hw_cache_extra_regs));
1678
1679 intel_pmu_lbr_init_nhm();
1680
1681 x86_pmu.event_constraints = intel_westmere_event_constraints;
1682 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1683 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
1684 x86_pmu.extra_regs = intel_westmere_extra_regs;
1685 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1686
1687 /* UOPS_ISSUED.STALLED_CYCLES */
1688 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1689 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1690 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1691
1692 pr_cont("Westmere events, ");
1693 break;
1694
1695 case 42: /* SandyBridge */
1696 case 45: /* SandyBridge, "Romely-EP" */
1697 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1698 sizeof(hw_cache_event_ids));
1699
1700 intel_pmu_lbr_init_nhm();
1701
1702 x86_pmu.event_constraints = intel_snb_event_constraints;
1703 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
1704 x86_pmu.extra_regs = intel_snb_extra_regs;
1705 /* all extra regs are per-cpu when HT is on */
1706 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1707 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
1708
1709 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1710 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1711 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1712 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
1713
1714 pr_cont("SandyBridge events, ");
1715 break;
1716
1717 default:
1718 switch (x86_pmu.version) {
1719 case 1:
1720 x86_pmu.event_constraints = intel_v1_event_constraints;
1721 pr_cont("generic architected perfmon v1, ");
1722 break;
1723 default:
1724 /*
1725 * default constraints for v2 and up
1726 */
1727 x86_pmu.event_constraints = intel_gen_event_constraints;
1728 pr_cont("generic architected perfmon, ");
1729 break;
1730 }
1731 }
1732 return 0;
1733 }
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