arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 #define pr_pic_unimpl(fmt, ...) \
  38         pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
  39
  40 static void pic_irq_request(struct kvm *kvm, int level);
  41
  42 static void pic_lock(struct kvm_pic *s)
  43         __acquires(&s->lock)
  44 {
  45         spin_lock(&s->lock);
  46 }
  47
  48 static void pic_unlock(struct kvm_pic *s)
  49         __releases(&s->lock)
  50 {
  51         bool wakeup = s->wakeup_needed;
  52         struct kvm_vcpu *vcpu, *found = NULL;
  53         int i;
  54
  55         s->wakeup_needed = false;
  56
  57         spin_unlock(&s->lock);
  58
  59         if (wakeup) {
  60                 kvm_for_each_vcpu(i, vcpu, s->kvm) {
  61                         if (kvm_apic_accept_pic_intr(vcpu)) {
  62                                 found = vcpu;
  63                                 break;
  64                         }
  65                 }
  66
  67                 if (!found)
  68                         return;
  69
  70                 kvm_make_request(KVM_REQ_EVENT, found);
  71                 kvm_vcpu_kick(found);
  72         }
  73 }
  74
  75 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  76 {
  77         s->isr &= ~(1 << irq);
  78         if (s != &s->pics_state->pics[0])
  79                 irq += 8;
  80         /*
  81          * We are dropping lock while calling ack notifiers since ack
  82          * notifier callbacks for assigned devices call into PIC recursively.
  83          * Other interrupt may be delivered to PIC while lock is dropped but
  84          * it should be safe since PIC state is already updated at this stage.
  85          */
  86         pic_unlock(s->pics_state);
  87         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  88         pic_lock(s->pics_state);
  89 }
  90
  91 /*
  92  * set irq level. If an edge is detected, then the IRR is set to 1
  93  */
  94 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  95 {
  96         int mask, ret = 1;
  97         mask = 1 << irq;
  98         if (s->elcr & mask)     /* level triggered */
  99                 if (level) {
 100                         ret = !(s->irr & mask);
 101                         s->irr |= mask;
 102                         s->last_irr |= mask;
 103                 } else {
 104                         s->irr &= ~mask;
 105                         s->last_irr &= ~mask;
 106                 }
 107         else    /* edge triggered */
 108                 if (level) {
 109                         if ((s->last_irr & mask) == 0) {
 110                                 ret = !(s->irr & mask);
 111                                 s->irr |= mask;
 112                         }
 113                         s->last_irr |= mask;
 114                 } else
 115                         s->last_irr &= ~mask;
 116
 117         return (s->imr & mask) ? -1 : ret;
 118 }
 119
 120 /*
 121  * return the highest priority found in mask (highest = smallest
 122  * number). Return 8 if no irq
 123  */
 124 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 125 {
 126         int priority;
 127         if (mask == 0)
 128                 return 8;
 129         priority = 0;
 130         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 131                 priority++;
 132         return priority;
 133 }
 134
 135 /*
 136  * return the pic wanted interrupt. return -1 if none
 137  */
 138 static int pic_get_irq(struct kvm_kpic_state *s)
 139 {
 140         int mask, cur_priority, priority;
 141
 142         mask = s->irr & ~s->imr;
 143         priority = get_priority(s, mask);
 144         if (priority == 8)
 145                 return -1;
 146         /*
 147          * compute current priority. If special fully nested mode on the
 148          * master, the IRQ coming from the slave is not taken into account
 149          * for the priority computation.
 150          */
 151         mask = s->isr;
 152         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 153                 mask &= ~(1 << 2);
 154         cur_priority = get_priority(s, mask);
 155         if (priority < cur_priority)
 156                 /*
 157                  * higher priority found: an irq should be generated
 158                  */
 159                 return (priority + s->priority_add) & 7;
 160         else
 161                 return -1;
 162 }
 163
 164 /*
 165  * raise irq to CPU if necessary. must be called every time the active
 166  * irq may change
 167  */
 168 static void pic_update_irq(struct kvm_pic *s)
 169 {
 170         int irq2, irq;
 171
 172         irq2 = pic_get_irq(&s->pics[1]);
 173         if (irq2 >= 0) {
 174                 /*
 175                  * if irq request by slave pic, signal master PIC
 176                  */
 177                 pic_set_irq1(&s->pics[0], 2, 1);
 178                 pic_set_irq1(&s->pics[0], 2, 0);
 179         }
 180         irq = pic_get_irq(&s->pics[0]);
 181         pic_irq_request(s->kvm, irq >= 0);
 182 }
 183
 184 void kvm_pic_update_irq(struct kvm_pic *s)
 185 {
 186         pic_lock(s);
 187         pic_update_irq(s);
 188         pic_unlock(s);
 189 }
 190
 191 int kvm_pic_set_irq(void *opaque, int irq, int level)
 192 {
 193         struct kvm_pic *s = opaque;
 194         int ret = -1;
 195
 196         pic_lock(s);
 197         if (irq >= 0 && irq < PIC_NUM_PINS) {
 198                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 199                 pic_update_irq(s);
 200                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 201                                       s->pics[irq >> 3].imr, ret == 0);
 202         }
 203         pic_unlock(s);
 204
 205         return ret;
 206 }
 207
 208 /*
 209  * acknowledge interrupt 'irq'
 210  */
 211 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 212 {
 213         s->isr |= 1 << irq;
 214         /*
 215          * We don't clear a level sensitive interrupt here
 216          */
 217         if (!(s->elcr & (1 << irq)))
 218                 s->irr &= ~(1 << irq);
 219
 220         if (s->auto_eoi) {
 221                 if (s->rotate_on_auto_eoi)
 222                         s->priority_add = (irq + 1) & 7;
 223                 pic_clear_isr(s, irq);
 224         }
 225
 226 }
 227
 228 int kvm_pic_read_irq(struct kvm *kvm)
 229 {
 230         int irq, irq2, intno;
 231         struct kvm_pic *s = pic_irqchip(kvm);
 232
 233         pic_lock(s);
 234         irq = pic_get_irq(&s->pics[0]);
 235         if (irq >= 0) {
 236                 pic_intack(&s->pics[0], irq);
 237                 if (irq == 2) {
 238                         irq2 = pic_get_irq(&s->pics[1]);
 239                         if (irq2 >= 0)
 240                                 pic_intack(&s->pics[1], irq2);
 241                         else
 242                                 /*
 243                                  * spurious IRQ on slave controller
 244                                  */
 245                                 irq2 = 7;
 246                         intno = s->pics[1].irq_base + irq2;
 247                         irq = irq2 + 8;
 248                 } else
 249                         intno = s->pics[0].irq_base + irq;
 250         } else {
 251                 /*
 252                  * spurious IRQ on host controller
 253                  */
 254                 irq = 7;
 255                 intno = s->pics[0].irq_base + irq;
 256         }
 257         pic_update_irq(s);
 258         pic_unlock(s);
 259
 260         return intno;
 261 }
 262
 263 void kvm_pic_reset(struct kvm_kpic_state *s)
 264 {
 265         int irq;
 266         struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
 267         u8 irr = s->irr, isr = s->imr;
 268
 269         s->last_irr = 0;
 270         s->irr = 0;
 271         s->imr = 0;
 272         s->isr = 0;
 273         s->priority_add = 0;
 274         s->irq_base = 0;
 275         s->read_reg_select = 0;
 276         s->poll = 0;
 277         s->special_mask = 0;
 278         s->init_state = 0;
 279         s->auto_eoi = 0;
 280         s->rotate_on_auto_eoi = 0;
 281         s->special_fully_nested_mode = 0;
 282         s->init4 = 0;
 283
 284         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 285                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 286                         if (irr & (1 << irq) || isr & (1 << irq)) {
 287                                 pic_clear_isr(s, irq);
 288                         }
 289         }
 290 }
 291
 292 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 293 {
 294         struct kvm_kpic_state *s = opaque;
 295         int priority, cmd, irq;
 296
 297         addr &= 1;
 298         if (addr == 0) {
 299                 if (val & 0x10) {
 300                         s->init4 = val & 1;
 301                         s->last_irr = 0;
 302                         s->imr = 0;
 303                         s->priority_add = 0;
 304                         s->special_mask = 0;
 305                         s->read_reg_select = 0;
 306                         if (!s->init4) {
 307                                 s->special_fully_nested_mode = 0;
 308                                 s->auto_eoi = 0;
 309                         }
 310                         s->init_state = 1;
 311                         if (val & 0x02)
 312                                 pr_pic_unimpl("single mode not supported");
 313                         if (val & 0x08)
 314                                 pr_pic_unimpl(
 315                                         "level sensitive irq not supported");
 316                 } else if (val & 0x08) {
 317                         if (val & 0x04)
 318                                 s->poll = 1;
 319                         if (val & 0x02)
 320                                 s->read_reg_select = val & 1;
 321                         if (val & 0x40)
 322                                 s->special_mask = (val >> 5) & 1;
 323                 } else {
 324                         cmd = val >> 5;
 325                         switch (cmd) {
 326                         case 0:
 327                         case 4:
 328                                 s->rotate_on_auto_eoi = cmd >> 2;
 329                                 break;
 330                         case 1: /* end of interrupt */
 331                         case 5:
 332                                 priority = get_priority(s, s->isr);
 333                                 if (priority != 8) {
 334                                         irq = (priority + s->priority_add) & 7;
 335                                         if (cmd == 5)
 336                                                 s->priority_add = (irq + 1) & 7;
 337                                         pic_clear_isr(s, irq);
 338                                         pic_update_irq(s->pics_state);
 339                                 }
 340                                 break;
 341                         case 3:
 342                                 irq = val & 7;
 343                                 pic_clear_isr(s, irq);
 344                                 pic_update_irq(s->pics_state);
 345                                 break;
 346                         case 6:
 347                                 s->priority_add = (val + 1) & 7;
 348                                 pic_update_irq(s->pics_state);
 349                                 break;
 350                         case 7:
 351                                 irq = val & 7;
 352                                 s->priority_add = (irq + 1) & 7;
 353                                 pic_clear_isr(s, irq);
 354                                 pic_update_irq(s->pics_state);
 355                                 break;
 356                         default:
 357                                 break;  /* no operation */
 358                         }
 359                 }
 360         } else
 361                 switch (s->init_state) {
 362                 case 0: { /* normal mode */
 363                         u8 imr_diff = s->imr ^ val,
 364                                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
 365                         s->imr = val;
 366                         for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
 367                                 if (imr_diff & (1 << irq))
 368                                         kvm_fire_mask_notifiers(
 369                                                 s->pics_state->kvm,
 370                                                 SELECT_PIC(irq + off),
 371                                                 irq + off,
 372                                                 !!(s->imr & (1 << irq)));
 373                         pic_update_irq(s->pics_state);
 374                         break;
 375                 }
 376                 case 1:
 377                         s->irq_base = val & 0xf8;
 378                         s->init_state = 2;
 379                         break;
 380                 case 2:
 381                         if (s->init4)
 382                                 s->init_state = 3;
 383                         else
 384                                 s->init_state = 0;
 385                         break;
 386                 case 3:
 387                         s->special_fully_nested_mode = (val >> 4) & 1;
 388                         s->auto_eoi = (val >> 1) & 1;
 389                         s->init_state = 0;
 390                         break;
 391                 }
 392 }
 393
 394 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 395 {
 396         int ret;
 397
 398         ret = pic_get_irq(s);
 399         if (ret >= 0) {
 400                 if (addr1 >> 7) {
 401                         s->pics_state->pics[0].isr &= ~(1 << 2);
 402                         s->pics_state->pics[0].irr &= ~(1 << 2);
 403                 }
 404                 s->irr &= ~(1 << ret);
 405                 pic_clear_isr(s, ret);
 406                 if (addr1 >> 7 || ret != 2)
 407                         pic_update_irq(s->pics_state);
 408         } else {
 409                 ret = 0x07;
 410                 pic_update_irq(s->pics_state);
 411         }
 412
 413         return ret;
 414 }
 415
 416 static u32 pic_ioport_read(void *opaque, u32 addr1)
 417 {
 418         struct kvm_kpic_state *s = opaque;
 419         unsigned int addr;
 420         int ret;
 421
 422         addr = addr1;
 423         addr &= 1;
 424         if (s->poll) {
 425                 ret = pic_poll_read(s, addr1);
 426                 s->poll = 0;
 427         } else
 428                 if (addr == 0)
 429                         if (s->read_reg_select)
 430                                 ret = s->isr;
 431                         else
 432                                 ret = s->irr;
 433                 else
 434                         ret = s->imr;
 435         return ret;
 436 }
 437
 438 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 439 {
 440         struct kvm_kpic_state *s = opaque;
 441         s->elcr = val & s->elcr_mask;
 442 }
 443
 444 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 445 {
 446         struct kvm_kpic_state *s = opaque;
 447         return s->elcr;
 448 }
 449
 450 static int picdev_in_range(gpa_t addr)
 451 {
 452         switch (addr) {
 453         case 0x20:
 454         case 0x21:
 455         case 0xa0:
 456         case 0xa1:
 457         case 0x4d0:
 458         case 0x4d1:
 459                 return 1;
 460         default:
 461                 return 0;
 462         }
 463 }
 464
 465 static int picdev_write(struct kvm_pic *s,
 466                          gpa_t addr, int len, const void *val)
 467 {
 468         unsigned char data = *(unsigned char *)val;
 469         if (!picdev_in_range(addr))
 470                 return -EOPNOTSUPP;
 471
 472         if (len != 1) {
 473                 pr_pic_unimpl("non byte write\n");
 474                 return 0;
 475         }
 476         pic_lock(s);
 477         switch (addr) {
 478         case 0x20:
 479         case 0x21:
 480         case 0xa0:
 481         case 0xa1:
 482                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 483                 break;
 484         case 0x4d0:
 485         case 0x4d1:
 486                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 487                 break;
 488         }
 489         pic_unlock(s);
 490         return 0;
 491 }
 492
 493 static int picdev_read(struct kvm_pic *s,
 494                        gpa_t addr, int len, void *val)
 495 {
 496         unsigned char data = 0;
 497         if (!picdev_in_range(addr))
 498                 return -EOPNOTSUPP;
 499
 500         if (len != 1) {
 501                 pr_pic_unimpl("non byte read\n");
 502                 return 0;
 503         }
 504         pic_lock(s);
 505         switch (addr) {
 506         case 0x20:
 507         case 0x21:
 508         case 0xa0:
 509         case 0xa1:
 510                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 511                 break;
 512         case 0x4d0:
 513         case 0x4d1:
 514                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 515                 break;
 516         }
 517         *(unsigned char *)val = data;
 518         pic_unlock(s);
 519         return 0;
 520 }
 521
 522 static int picdev_master_write(struct kvm_io_device *dev,
 523                                gpa_t addr, int len, const void *val)
 524 {
 525         return picdev_write(container_of(dev, struct kvm_pic, dev_master),
 526                             addr, len, val);
 527 }
 528
 529 static int picdev_master_read(struct kvm_io_device *dev,
 530                               gpa_t addr, int len, void *val)
 531 {
 532         return picdev_read(container_of(dev, struct kvm_pic, dev_master),
 533                             addr, len, val);
 534 }
 535
 536 static int picdev_slave_write(struct kvm_io_device *dev,
 537                               gpa_t addr, int len, const void *val)
 538 {
 539         return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
 540                             addr, len, val);
 541 }
 542
 543 static int picdev_slave_read(struct kvm_io_device *dev,
 544                              gpa_t addr, int len, void *val)
 545 {
 546         return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
 547                             addr, len, val);
 548 }
 549
 550 static int picdev_eclr_write(struct kvm_io_device *dev,
 551                              gpa_t addr, int len, const void *val)
 552 {
 553         return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
 554                             addr, len, val);
 555 }
 556
 557 static int picdev_eclr_read(struct kvm_io_device *dev,
 558                             gpa_t addr, int len, void *val)
 559 {
 560         return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
 561                             addr, len, val);
 562 }
 563
 564 /*
 565  * callback when PIC0 irq status changed
 566  */
 567 static void pic_irq_request(struct kvm *kvm, int level)
 568 {
 569         struct kvm_pic *s = pic_irqchip(kvm);
 570
 571         if (!s->output)
 572                 s->wakeup_needed = true;
 573         s->output = level;
 574 }
 575
 576 static const struct kvm_io_device_ops picdev_master_ops = {
 577         .read     = picdev_master_read,
 578         .write    = picdev_master_write,
 579 };
 580
 581 static const struct kvm_io_device_ops picdev_slave_ops = {
 582         .read     = picdev_slave_read,
 583         .write    = picdev_slave_write,
 584 };
 585
 586 static const struct kvm_io_device_ops picdev_eclr_ops = {
 587         .read     = picdev_eclr_read,
 588         .write    = picdev_eclr_write,
 589 };
 590
 591 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 592 {
 593         struct kvm_pic *s;
 594         int ret;
 595
 596         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 597         if (!s)
 598                 return NULL;
 599         spin_lock_init(&s->lock);
 600         s->kvm = kvm;
 601         s->pics[0].elcr_mask = 0xf8;
 602         s->pics[1].elcr_mask = 0xde;
 603         s->pics[0].pics_state = s;
 604         s->pics[1].pics_state = s;
 605
 606         /*
 607          * Initialize PIO device
 608          */
 609         kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
 610         kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
 611         kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
 612         mutex_lock(&kvm->slots_lock);
 613         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
 614                                       &s->dev_master);
 615         if (ret < 0)
 616                 goto fail_unlock;
 617
 618         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
 619         if (ret < 0)
 620                 goto fail_unreg_2;
 621
 622         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
 623         if (ret < 0)
 624                 goto fail_unreg_1;
 625
 626         mutex_unlock(&kvm->slots_lock);
 627
 628         return s;
 629
 630 fail_unreg_1:
 631         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
 632
 633 fail_unreg_2:
 634         kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
 635
 636 fail_unlock:
 637         mutex_unlock(&kvm->slots_lock);
 638
 639         kfree(s);
 640
 641         return NULL;
 642 }
 643
 644 void kvm_destroy_pic(struct kvm *kvm)
 645 {
 646         struct kvm_pic *vpic = kvm->arch.vpic;
 647
 648         if (vpic) {
 649                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_master);
 650                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_slave);
 651                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev_eclr);
 652                 kvm->arch.vpic = NULL;
 653                 kfree(vpic);
 654         }
 655 }