2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
62 char *audit_point_name
[] = {
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
87 module_param(dbg
, bool, 0644);
90 static int oos_shadow
= 1;
91 module_param(oos_shadow
, bool, 0644);
94 #define ASSERT(x) do { } while (0)
98 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
99 __FILE__, __LINE__, #x); \
103 #define PTE_PREFETCH_NUM 8
105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
108 #define PT64_LEVEL_BITS 9
110 #define PT64_LEVEL_SHIFT(level) \
111 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
113 #define PT64_INDEX(address, level)\
114 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
117 #define PT32_LEVEL_BITS 10
119 #define PT32_LEVEL_SHIFT(level) \
120 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT64_LEVEL_BITS))) - 1))
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145 * PT32_LEVEL_BITS))) - 1))
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
150 #define PTE_LIST_EXT 4
152 #define ACC_EXEC_MASK 1
153 #define ACC_WRITE_MASK PT_WRITABLE_MASK
154 #define ACC_USER_MASK PT_USER_MASK
155 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
157 #include <trace/events/kvm.h>
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
166 struct pte_list_desc
{
167 u64
*sptes
[PTE_LIST_EXT
];
168 struct pte_list_desc
*more
;
171 struct kvm_shadow_walk_iterator
{
179 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
180 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
181 shadow_walk_okay(&(_walker)); \
182 shadow_walk_next(&(_walker)))
184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
185 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
186 shadow_walk_okay(&(_walker)) && \
187 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
188 __shadow_walk_next(&(_walker), spte))
190 static struct kmem_cache
*pte_list_desc_cache
;
191 static struct kmem_cache
*mmu_page_header_cache
;
192 static struct percpu_counter kvm_total_used_mmu_pages
;
194 static u64 __read_mostly shadow_nx_mask
;
195 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask
;
197 static u64 __read_mostly shadow_accessed_mask
;
198 static u64 __read_mostly shadow_dirty_mask
;
199 static u64 __read_mostly shadow_mmio_mask
;
201 static void mmu_spte_set(u64
*sptep
, u64 spte
);
203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
205 shadow_mmio_mask
= mmio_mask
;
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
209 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
211 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
213 trace_mark_mmio_spte(sptep
, gfn
, access
);
214 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
217 static bool is_mmio_spte(u64 spte
)
219 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
222 static gfn_t
get_mmio_spte_gfn(u64 spte
)
224 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
227 static unsigned get_mmio_spte_access(u64 spte
)
229 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
232 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
234 if (unlikely(is_noslot_pfn(pfn
))) {
235 mark_mmio_spte(sptep
, gfn
, access
);
242 static inline u64
rsvd_bits(int s
, int e
)
244 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
247 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
248 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
250 shadow_user_mask
= user_mask
;
251 shadow_accessed_mask
= accessed_mask
;
252 shadow_dirty_mask
= dirty_mask
;
253 shadow_nx_mask
= nx_mask
;
254 shadow_x_mask
= x_mask
;
256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
258 static int is_cpuid_PSE36(void)
263 static int is_nx(struct kvm_vcpu
*vcpu
)
265 return vcpu
->arch
.efer
& EFER_NX
;
268 static int is_shadow_present_pte(u64 pte
)
270 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
273 static int is_large_pte(u64 pte
)
275 return pte
& PT_PAGE_SIZE_MASK
;
278 static int is_dirty_gpte(unsigned long pte
)
280 return pte
& PT_DIRTY_MASK
;
283 static int is_rmap_spte(u64 pte
)
285 return is_shadow_present_pte(pte
);
288 static int is_last_spte(u64 pte
, int level
)
290 if (level
== PT_PAGE_TABLE_LEVEL
)
292 if (is_large_pte(pte
))
297 static pfn_t
spte_to_pfn(u64 pte
)
299 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
302 static gfn_t
pse36_gfn_delta(u32 gpte
)
304 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
306 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
310 static void __set_spte(u64
*sptep
, u64 spte
)
315 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
320 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
322 return xchg(sptep
, spte
);
325 static u64
__get_spte_lockless(u64
*sptep
)
327 return ACCESS_ONCE(*sptep
);
330 static bool __check_direct_spte_mmio_pf(u64 spte
)
332 /* It is valid if the spte is zapped. */
344 static void count_spte_clear(u64
*sptep
, u64 spte
)
346 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
348 if (is_shadow_present_pte(spte
))
351 /* Ensure the spte is completely set before we increase the count */
353 sp
->clear_spte_count
++;
356 static void __set_spte(u64
*sptep
, u64 spte
)
358 union split_spte
*ssptep
, sspte
;
360 ssptep
= (union split_spte
*)sptep
;
361 sspte
= (union split_spte
)spte
;
363 ssptep
->spte_high
= sspte
.spte_high
;
366 * If we map the spte from nonpresent to present, We should store
367 * the high bits firstly, then set present bit, so cpu can not
368 * fetch this spte while we are setting the spte.
372 ssptep
->spte_low
= sspte
.spte_low
;
375 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
377 union split_spte
*ssptep
, sspte
;
379 ssptep
= (union split_spte
*)sptep
;
380 sspte
= (union split_spte
)spte
;
382 ssptep
->spte_low
= sspte
.spte_low
;
385 * If we map the spte from present to nonpresent, we should clear
386 * present bit firstly to avoid vcpu fetch the old high bits.
390 ssptep
->spte_high
= sspte
.spte_high
;
391 count_spte_clear(sptep
, spte
);
394 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
396 union split_spte
*ssptep
, sspte
, orig
;
398 ssptep
= (union split_spte
*)sptep
;
399 sspte
= (union split_spte
)spte
;
401 /* xchg acts as a barrier before the setting of the high bits */
402 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
403 orig
.spte_high
= ssptep
->spte_high
;
404 ssptep
->spte_high
= sspte
.spte_high
;
405 count_spte_clear(sptep
, spte
);
411 * The idea using the light way get the spte on x86_32 guest is from
412 * gup_get_pte(arch/x86/mm/gup.c).
413 * The difference is we can not catch the spte tlb flush if we leave
414 * guest mode, so we emulate it by increase clear_spte_count when spte
417 static u64
__get_spte_lockless(u64
*sptep
)
419 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
420 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
424 count
= sp
->clear_spte_count
;
427 spte
.spte_low
= orig
->spte_low
;
430 spte
.spte_high
= orig
->spte_high
;
433 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
434 count
!= sp
->clear_spte_count
))
440 static bool __check_direct_spte_mmio_pf(u64 spte
)
442 union split_spte sspte
= (union split_spte
)spte
;
443 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
445 /* It is valid if the spte is zapped. */
449 /* It is valid if the spte is being zapped. */
450 if (sspte
.spte_low
== 0ull &&
451 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
458 static bool spte_has_volatile_bits(u64 spte
)
460 if (!shadow_accessed_mask
)
463 if (!is_shadow_present_pte(spte
))
466 if ((spte
& shadow_accessed_mask
) &&
467 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
473 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
475 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
478 /* Rules for using mmu_spte_set:
479 * Set the sptep from nonpresent to present.
480 * Note: the sptep being assigned *must* be either not present
481 * or in a state where the hardware will not attempt to update
484 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
486 WARN_ON(is_shadow_present_pte(*sptep
));
487 __set_spte(sptep
, new_spte
);
490 /* Rules for using mmu_spte_update:
491 * Update the state bits, it means the mapped pfn is not changged.
493 static void mmu_spte_update(u64
*sptep
, u64 new_spte
)
495 u64 mask
, old_spte
= *sptep
;
497 WARN_ON(!is_rmap_spte(new_spte
));
499 if (!is_shadow_present_pte(old_spte
))
500 return mmu_spte_set(sptep
, new_spte
);
502 new_spte
|= old_spte
& shadow_dirty_mask
;
504 mask
= shadow_accessed_mask
;
505 if (is_writable_pte(old_spte
))
506 mask
|= shadow_dirty_mask
;
508 if (!spte_has_volatile_bits(old_spte
) || (new_spte
& mask
) == mask
)
509 __update_clear_spte_fast(sptep
, new_spte
);
511 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
513 if (!shadow_accessed_mask
)
516 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
517 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
518 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
519 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
523 * Rules for using mmu_spte_clear_track_bits:
524 * It sets the sptep from present to nonpresent, and track the
525 * state bits, it is used to clear the last level sptep.
527 static int mmu_spte_clear_track_bits(u64
*sptep
)
530 u64 old_spte
= *sptep
;
532 if (!spte_has_volatile_bits(old_spte
))
533 __update_clear_spte_fast(sptep
, 0ull);
535 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
537 if (!is_rmap_spte(old_spte
))
540 pfn
= spte_to_pfn(old_spte
);
541 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
542 kvm_set_pfn_accessed(pfn
);
543 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
544 kvm_set_pfn_dirty(pfn
);
549 * Rules for using mmu_spte_clear_no_track:
550 * Directly clear spte without caring the state bits of sptep,
551 * it is used to set the upper level spte.
553 static void mmu_spte_clear_no_track(u64
*sptep
)
555 __update_clear_spte_fast(sptep
, 0ull);
558 static u64
mmu_spte_get_lockless(u64
*sptep
)
560 return __get_spte_lockless(sptep
);
563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
566 atomic_inc(&vcpu
->kvm
->arch
.reader_counter
);
568 /* Increase the counter before walking shadow page table */
569 smp_mb__after_atomic_inc();
572 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
574 /* Decrease the counter after walking shadow page table finished */
575 smp_mb__before_atomic_dec();
576 atomic_dec(&vcpu
->kvm
->arch
.reader_counter
);
580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
581 struct kmem_cache
*base_cache
, int min
)
585 if (cache
->nobjs
>= min
)
587 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
588 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
591 cache
->objects
[cache
->nobjs
++] = obj
;
596 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
597 struct kmem_cache
*cache
)
600 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
603 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
608 if (cache
->nobjs
>= min
)
610 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
611 page
= (void *)__get_free_page(GFP_KERNEL
);
614 cache
->objects
[cache
->nobjs
++] = page
;
619 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
622 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
625 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
629 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
630 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
633 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
636 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
637 mmu_page_header_cache
, 4);
642 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
644 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
645 pte_list_desc_cache
);
646 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
647 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
648 mmu_page_header_cache
);
651 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
,
657 p
= mc
->objects
[--mc
->nobjs
];
661 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
663 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
,
664 sizeof(struct pte_list_desc
));
667 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
669 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
672 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
674 if (!sp
->role
.direct
)
675 return sp
->gfns
[index
];
677 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
680 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
683 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
685 sp
->gfns
[index
] = gfn
;
689 * Return the pointer to the large page information for a given gfn,
690 * handling slots that are not large page aligned.
692 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
693 struct kvm_memory_slot
*slot
,
698 idx
= (gfn
>> KVM_HPAGE_GFN_SHIFT(level
)) -
699 (slot
->base_gfn
>> KVM_HPAGE_GFN_SHIFT(level
));
700 return &slot
->lpage_info
[level
- 2][idx
];
703 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
705 struct kvm_memory_slot
*slot
;
706 struct kvm_lpage_info
*linfo
;
709 slot
= gfn_to_memslot(kvm
, gfn
);
710 for (i
= PT_DIRECTORY_LEVEL
;
711 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
712 linfo
= lpage_info_slot(gfn
, slot
, i
);
713 linfo
->write_count
+= 1;
715 kvm
->arch
.indirect_shadow_pages
++;
718 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
720 struct kvm_memory_slot
*slot
;
721 struct kvm_lpage_info
*linfo
;
724 slot
= gfn_to_memslot(kvm
, gfn
);
725 for (i
= PT_DIRECTORY_LEVEL
;
726 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
727 linfo
= lpage_info_slot(gfn
, slot
, i
);
728 linfo
->write_count
-= 1;
729 WARN_ON(linfo
->write_count
< 0);
731 kvm
->arch
.indirect_shadow_pages
--;
734 static int has_wrprotected_page(struct kvm
*kvm
,
738 struct kvm_memory_slot
*slot
;
739 struct kvm_lpage_info
*linfo
;
741 slot
= gfn_to_memslot(kvm
, gfn
);
743 linfo
= lpage_info_slot(gfn
, slot
, level
);
744 return linfo
->write_count
;
750 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
752 unsigned long page_size
;
755 page_size
= kvm_host_page_size(kvm
, gfn
);
757 for (i
= PT_PAGE_TABLE_LEVEL
;
758 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
759 if (page_size
>= KVM_HPAGE_SIZE(i
))
768 static struct kvm_memory_slot
*
769 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
772 struct kvm_memory_slot
*slot
;
774 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
775 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
776 (no_dirty_log
&& slot
->dirty_bitmap
))
782 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
784 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
787 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
789 int host_level
, level
, max_level
;
791 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
793 if (host_level
== PT_PAGE_TABLE_LEVEL
)
796 max_level
= kvm_x86_ops
->get_lpage_level() < host_level
?
797 kvm_x86_ops
->get_lpage_level() : host_level
;
799 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
800 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
807 * Pte mapping structures:
809 * If pte_list bit zero is zero, then pte_list point to the spte.
811 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
812 * pte_list_desc containing more mappings.
814 * Returns the number of pte entries before the spte was added or zero if
815 * the spte was not added.
818 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
819 unsigned long *pte_list
)
821 struct pte_list_desc
*desc
;
825 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
826 *pte_list
= (unsigned long)spte
;
827 } else if (!(*pte_list
& 1)) {
828 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
829 desc
= mmu_alloc_pte_list_desc(vcpu
);
830 desc
->sptes
[0] = (u64
*)*pte_list
;
831 desc
->sptes
[1] = spte
;
832 *pte_list
= (unsigned long)desc
| 1;
835 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
836 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
837 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
839 count
+= PTE_LIST_EXT
;
841 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
842 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
845 for (i
= 0; desc
->sptes
[i
]; ++i
)
847 desc
->sptes
[i
] = spte
;
852 static u64
*pte_list_next(unsigned long *pte_list
, u64
*spte
)
854 struct pte_list_desc
*desc
;
860 else if (!(*pte_list
& 1)) {
862 return (u64
*)*pte_list
;
865 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
868 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
869 if (prev_spte
== spte
)
870 return desc
->sptes
[i
];
871 prev_spte
= desc
->sptes
[i
];
879 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
880 int i
, struct pte_list_desc
*prev_desc
)
884 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
886 desc
->sptes
[i
] = desc
->sptes
[j
];
887 desc
->sptes
[j
] = NULL
;
890 if (!prev_desc
&& !desc
->more
)
891 *pte_list
= (unsigned long)desc
->sptes
[0];
894 prev_desc
->more
= desc
->more
;
896 *pte_list
= (unsigned long)desc
->more
| 1;
897 mmu_free_pte_list_desc(desc
);
900 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
902 struct pte_list_desc
*desc
;
903 struct pte_list_desc
*prev_desc
;
907 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
909 } else if (!(*pte_list
& 1)) {
910 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
911 if ((u64
*)*pte_list
!= spte
) {
912 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
917 rmap_printk("pte_list_remove: %p many->many\n", spte
);
918 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
921 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
922 if (desc
->sptes
[i
] == spte
) {
923 pte_list_desc_remove_entry(pte_list
,
931 pr_err("pte_list_remove: %p many->many\n", spte
);
936 typedef void (*pte_list_walk_fn
) (u64
*spte
);
937 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
939 struct pte_list_desc
*desc
;
945 if (!(*pte_list
& 1))
946 return fn((u64
*)*pte_list
);
948 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
950 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
957 * Take gfn and return the reverse mapping to it.
959 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
961 struct kvm_memory_slot
*slot
;
962 struct kvm_lpage_info
*linfo
;
964 slot
= gfn_to_memslot(kvm
, gfn
);
965 if (likely(level
== PT_PAGE_TABLE_LEVEL
))
966 return &slot
->rmap
[gfn
- slot
->base_gfn
];
968 linfo
= lpage_info_slot(gfn
, slot
, level
);
970 return &linfo
->rmap_pde
;
973 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
975 struct kvm_mmu_page
*sp
;
976 unsigned long *rmapp
;
978 sp
= page_header(__pa(spte
));
979 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
980 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
981 return pte_list_add(vcpu
, spte
, rmapp
);
984 static u64
*rmap_next(struct kvm
*kvm
, unsigned long *rmapp
, u64
*spte
)
986 return pte_list_next(rmapp
, spte
);
989 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
991 struct kvm_mmu_page
*sp
;
993 unsigned long *rmapp
;
995 sp
= page_header(__pa(spte
));
996 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
997 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
998 pte_list_remove(spte
, rmapp
);
1001 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1003 if (mmu_spte_clear_track_bits(sptep
))
1004 rmap_remove(kvm
, sptep
);
1007 static int rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1009 unsigned long *rmapp
;
1011 int i
, write_protected
= 0;
1013 rmapp
= gfn_to_rmap(kvm
, gfn
, PT_PAGE_TABLE_LEVEL
);
1015 spte
= rmap_next(kvm
, rmapp
, NULL
);
1018 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1019 rmap_printk("rmap_write_protect: spte %p %llx\n", spte
, *spte
);
1020 if (is_writable_pte(*spte
)) {
1021 mmu_spte_update(spte
, *spte
& ~PT_WRITABLE_MASK
);
1022 write_protected
= 1;
1024 spte
= rmap_next(kvm
, rmapp
, spte
);
1027 /* check for huge page mappings */
1028 for (i
= PT_DIRECTORY_LEVEL
;
1029 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1030 rmapp
= gfn_to_rmap(kvm
, gfn
, i
);
1031 spte
= rmap_next(kvm
, rmapp
, NULL
);
1034 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1035 BUG_ON((*spte
& (PT_PAGE_SIZE_MASK
|PT_PRESENT_MASK
)) != (PT_PAGE_SIZE_MASK
|PT_PRESENT_MASK
));
1036 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte
, *spte
, gfn
);
1037 if (is_writable_pte(*spte
)) {
1038 drop_spte(kvm
, spte
);
1041 write_protected
= 1;
1043 spte
= rmap_next(kvm
, rmapp
, spte
);
1047 return write_protected
;
1050 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1054 int need_tlb_flush
= 0;
1056 while ((spte
= rmap_next(kvm
, rmapp
, NULL
))) {
1057 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1058 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte
, *spte
);
1059 drop_spte(kvm
, spte
);
1062 return need_tlb_flush
;
1065 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1069 u64
*spte
, new_spte
;
1070 pte_t
*ptep
= (pte_t
*)data
;
1073 WARN_ON(pte_huge(*ptep
));
1074 new_pfn
= pte_pfn(*ptep
);
1075 spte
= rmap_next(kvm
, rmapp
, NULL
);
1077 BUG_ON(!is_shadow_present_pte(*spte
));
1078 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte
, *spte
);
1080 if (pte_write(*ptep
)) {
1081 drop_spte(kvm
, spte
);
1082 spte
= rmap_next(kvm
, rmapp
, NULL
);
1084 new_spte
= *spte
&~ (PT64_BASE_ADDR_MASK
);
1085 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1087 new_spte
&= ~PT_WRITABLE_MASK
;
1088 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1089 new_spte
&= ~shadow_accessed_mask
;
1090 mmu_spte_clear_track_bits(spte
);
1091 mmu_spte_set(spte
, new_spte
);
1092 spte
= rmap_next(kvm
, rmapp
, spte
);
1096 kvm_flush_remote_tlbs(kvm
);
1101 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1103 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1104 unsigned long data
))
1109 struct kvm_memslots
*slots
;
1111 slots
= kvm_memslots(kvm
);
1113 for (i
= 0; i
< slots
->nmemslots
; i
++) {
1114 struct kvm_memory_slot
*memslot
= &slots
->memslots
[i
];
1115 unsigned long start
= memslot
->userspace_addr
;
1118 end
= start
+ (memslot
->npages
<< PAGE_SHIFT
);
1119 if (hva
>= start
&& hva
< end
) {
1120 gfn_t gfn_offset
= (hva
- start
) >> PAGE_SHIFT
;
1121 gfn_t gfn
= memslot
->base_gfn
+ gfn_offset
;
1123 ret
= handler(kvm
, &memslot
->rmap
[gfn_offset
], data
);
1125 for (j
= 0; j
< KVM_NR_PAGE_SIZES
- 1; ++j
) {
1126 struct kvm_lpage_info
*linfo
;
1128 linfo
= lpage_info_slot(gfn
, memslot
,
1129 PT_DIRECTORY_LEVEL
+ j
);
1130 ret
|= handler(kvm
, &linfo
->rmap_pde
, data
);
1132 trace_kvm_age_page(hva
, memslot
, ret
);
1140 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1142 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1145 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1147 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1150 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1157 * Emulate the accessed bit for EPT, by checking if this page has
1158 * an EPT mapping, and clearing it if it does. On the next access,
1159 * a new EPT mapping will be established.
1160 * This has some overhead, but not as much as the cost of swapping
1161 * out actively used pages or breaking up actively used hugepages.
1163 if (!shadow_accessed_mask
)
1164 return kvm_unmap_rmapp(kvm
, rmapp
, data
);
1166 spte
= rmap_next(kvm
, rmapp
, NULL
);
1170 BUG_ON(!(_spte
& PT_PRESENT_MASK
));
1171 _young
= _spte
& PT_ACCESSED_MASK
;
1174 clear_bit(PT_ACCESSED_SHIFT
, (unsigned long *)spte
);
1176 spte
= rmap_next(kvm
, rmapp
, spte
);
1181 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1188 * If there's no access bit in the secondary pte set by the
1189 * hardware it's up to gup-fast/gup to set the access bit in
1190 * the primary pte or in the page structure.
1192 if (!shadow_accessed_mask
)
1195 spte
= rmap_next(kvm
, rmapp
, NULL
);
1198 BUG_ON(!(_spte
& PT_PRESENT_MASK
));
1199 young
= _spte
& PT_ACCESSED_MASK
;
1204 spte
= rmap_next(kvm
, rmapp
, spte
);
1210 #define RMAP_RECYCLE_THRESHOLD 1000
1212 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1214 unsigned long *rmapp
;
1215 struct kvm_mmu_page
*sp
;
1217 sp
= page_header(__pa(spte
));
1219 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1221 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, 0);
1222 kvm_flush_remote_tlbs(vcpu
->kvm
);
1225 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1227 return kvm_handle_hva(kvm
, hva
, 0, kvm_age_rmapp
);
1230 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1232 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1236 static int is_empty_shadow_page(u64
*spt
)
1241 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1242 if (is_shadow_present_pte(*pos
)) {
1243 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1252 * This value is the sum of all of the kvm instances's
1253 * kvm->arch.n_used_mmu_pages values. We need a global,
1254 * aggregate version in order to make the slab shrinker
1257 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1259 kvm
->arch
.n_used_mmu_pages
+= nr
;
1260 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1264 * Remove the sp from shadow page cache, after call it,
1265 * we can not find this sp from the cache, and the shadow
1266 * page table is still valid.
1267 * It should be under the protection of mmu lock.
1269 static void kvm_mmu_isolate_page(struct kvm_mmu_page
*sp
)
1271 ASSERT(is_empty_shadow_page(sp
->spt
));
1272 hlist_del(&sp
->hash_link
);
1273 if (!sp
->role
.direct
)
1274 free_page((unsigned long)sp
->gfns
);
1278 * Free the shadow page table and the sp, we can do it
1279 * out of the protection of mmu lock.
1281 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1283 list_del(&sp
->link
);
1284 free_page((unsigned long)sp
->spt
);
1285 kmem_cache_free(mmu_page_header_cache
, sp
);
1288 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1290 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1293 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1294 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1299 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1302 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1305 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1308 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1311 mmu_page_remove_parent_pte(sp
, parent_pte
);
1312 mmu_spte_clear_no_track(parent_pte
);
1315 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1316 u64
*parent_pte
, int direct
)
1318 struct kvm_mmu_page
*sp
;
1319 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
,
1321 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
, PAGE_SIZE
);
1323 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
,
1325 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1326 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1327 bitmap_zero(sp
->slot_bitmap
, KVM_MEMORY_SLOTS
+ KVM_PRIVATE_MEM_SLOTS
);
1328 sp
->parent_ptes
= 0;
1329 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1330 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1334 static void mark_unsync(u64
*spte
);
1335 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1337 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1340 static void mark_unsync(u64
*spte
)
1342 struct kvm_mmu_page
*sp
;
1345 sp
= page_header(__pa(spte
));
1346 index
= spte
- sp
->spt
;
1347 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1349 if (sp
->unsync_children
++)
1351 kvm_mmu_mark_parents_unsync(sp
);
1354 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1355 struct kvm_mmu_page
*sp
)
1360 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1364 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1365 struct kvm_mmu_page
*sp
, u64
*spte
,
1371 #define KVM_PAGE_ARRAY_NR 16
1373 struct kvm_mmu_pages
{
1374 struct mmu_page_and_offset
{
1375 struct kvm_mmu_page
*sp
;
1377 } page
[KVM_PAGE_ARRAY_NR
];
1381 #define for_each_unsync_children(bitmap, idx) \
1382 for (idx = find_first_bit(bitmap, 512); \
1384 idx = find_next_bit(bitmap, 512, idx+1))
1386 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1392 for (i
=0; i
< pvec
->nr
; i
++)
1393 if (pvec
->page
[i
].sp
== sp
)
1396 pvec
->page
[pvec
->nr
].sp
= sp
;
1397 pvec
->page
[pvec
->nr
].idx
= idx
;
1399 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1402 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1403 struct kvm_mmu_pages
*pvec
)
1405 int i
, ret
, nr_unsync_leaf
= 0;
1407 for_each_unsync_children(sp
->unsync_child_bitmap
, i
) {
1408 struct kvm_mmu_page
*child
;
1409 u64 ent
= sp
->spt
[i
];
1411 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1412 goto clear_child_bitmap
;
1414 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1416 if (child
->unsync_children
) {
1417 if (mmu_pages_add(pvec
, child
, i
))
1420 ret
= __mmu_unsync_walk(child
, pvec
);
1422 goto clear_child_bitmap
;
1424 nr_unsync_leaf
+= ret
;
1427 } else if (child
->unsync
) {
1429 if (mmu_pages_add(pvec
, child
, i
))
1432 goto clear_child_bitmap
;
1437 __clear_bit(i
, sp
->unsync_child_bitmap
);
1438 sp
->unsync_children
--;
1439 WARN_ON((int)sp
->unsync_children
< 0);
1443 return nr_unsync_leaf
;
1446 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1447 struct kvm_mmu_pages
*pvec
)
1449 if (!sp
->unsync_children
)
1452 mmu_pages_add(pvec
, sp
, 0);
1453 return __mmu_unsync_walk(sp
, pvec
);
1456 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1458 WARN_ON(!sp
->unsync
);
1459 trace_kvm_mmu_sync_page(sp
);
1461 --kvm
->stat
.mmu_unsync
;
1464 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1465 struct list_head
*invalid_list
);
1466 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1467 struct list_head
*invalid_list
);
1469 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1470 hlist_for_each_entry(sp, pos, \
1471 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1472 if ((sp)->gfn != (gfn)) {} else
1474 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1475 hlist_for_each_entry(sp, pos, \
1476 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1477 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1478 (sp)->role.invalid) {} else
1480 /* @sp->gfn should be write-protected at the call site */
1481 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1482 struct list_head
*invalid_list
, bool clear_unsync
)
1484 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1485 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1490 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1492 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1493 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1497 kvm_mmu_flush_tlb(vcpu
);
1501 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1502 struct kvm_mmu_page
*sp
)
1504 LIST_HEAD(invalid_list
);
1507 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1509 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1514 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1515 struct list_head
*invalid_list
)
1517 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1520 /* @gfn should be write-protected at the call site */
1521 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1523 struct kvm_mmu_page
*s
;
1524 struct hlist_node
*node
;
1525 LIST_HEAD(invalid_list
);
1528 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
1532 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1533 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1534 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1535 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1536 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1542 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1544 kvm_mmu_flush_tlb(vcpu
);
1547 struct mmu_page_path
{
1548 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1549 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1552 #define for_each_sp(pvec, sp, parents, i) \
1553 for (i = mmu_pages_next(&pvec, &parents, -1), \
1554 sp = pvec.page[i].sp; \
1555 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1556 i = mmu_pages_next(&pvec, &parents, i))
1558 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1559 struct mmu_page_path
*parents
,
1564 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1565 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1567 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1568 parents
->idx
[0] = pvec
->page
[n
].idx
;
1572 parents
->parent
[sp
->role
.level
-2] = sp
;
1573 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1579 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1581 struct kvm_mmu_page
*sp
;
1582 unsigned int level
= 0;
1585 unsigned int idx
= parents
->idx
[level
];
1587 sp
= parents
->parent
[level
];
1591 --sp
->unsync_children
;
1592 WARN_ON((int)sp
->unsync_children
< 0);
1593 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1595 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1598 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1599 struct mmu_page_path
*parents
,
1600 struct kvm_mmu_pages
*pvec
)
1602 parents
->parent
[parent
->role
.level
-1] = NULL
;
1606 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1607 struct kvm_mmu_page
*parent
)
1610 struct kvm_mmu_page
*sp
;
1611 struct mmu_page_path parents
;
1612 struct kvm_mmu_pages pages
;
1613 LIST_HEAD(invalid_list
);
1615 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1616 while (mmu_unsync_walk(parent
, &pages
)) {
1619 for_each_sp(pages
, sp
, parents
, i
)
1620 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1623 kvm_flush_remote_tlbs(vcpu
->kvm
);
1625 for_each_sp(pages
, sp
, parents
, i
) {
1626 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1627 mmu_pages_clear_parents(&parents
);
1629 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1630 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1631 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1635 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1639 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1643 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1651 union kvm_mmu_page_role role
;
1653 struct kvm_mmu_page
*sp
;
1654 struct hlist_node
*node
;
1655 bool need_sync
= false;
1657 role
= vcpu
->arch
.mmu
.base_role
;
1659 role
.direct
= direct
;
1662 role
.access
= access
;
1663 if (!vcpu
->arch
.mmu
.direct_map
1664 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1665 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1666 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1667 role
.quadrant
= quadrant
;
1669 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
, node
) {
1670 if (!need_sync
&& sp
->unsync
)
1673 if (sp
->role
.word
!= role
.word
)
1676 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1679 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1680 if (sp
->unsync_children
) {
1681 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1682 kvm_mmu_mark_parents_unsync(sp
);
1683 } else if (sp
->unsync
)
1684 kvm_mmu_mark_parents_unsync(sp
);
1686 trace_kvm_mmu_get_page(sp
, false);
1689 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1690 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1695 hlist_add_head(&sp
->hash_link
,
1696 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1698 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1699 kvm_flush_remote_tlbs(vcpu
->kvm
);
1700 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1701 kvm_sync_pages(vcpu
, gfn
);
1703 account_shadowed(vcpu
->kvm
, gfn
);
1705 init_shadow_page_table(sp
);
1706 trace_kvm_mmu_get_page(sp
, true);
1710 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1711 struct kvm_vcpu
*vcpu
, u64 addr
)
1713 iterator
->addr
= addr
;
1714 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1715 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1717 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1718 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1719 !vcpu
->arch
.mmu
.direct_map
)
1722 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1723 iterator
->shadow_addr
1724 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1725 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1727 if (!iterator
->shadow_addr
)
1728 iterator
->level
= 0;
1732 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1734 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1737 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1738 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1742 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1745 if (is_last_spte(spte
, iterator
->level
)) {
1746 iterator
->level
= 0;
1750 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1754 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1756 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1759 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1763 spte
= __pa(sp
->spt
)
1764 | PT_PRESENT_MASK
| PT_ACCESSED_MASK
1765 | PT_WRITABLE_MASK
| PT_USER_MASK
;
1766 mmu_spte_set(sptep
, spte
);
1769 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1771 if (is_large_pte(*sptep
)) {
1772 drop_spte(vcpu
->kvm
, sptep
);
1773 kvm_flush_remote_tlbs(vcpu
->kvm
);
1777 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1778 unsigned direct_access
)
1780 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1781 struct kvm_mmu_page
*child
;
1784 * For the direct sp, if the guest pte's dirty bit
1785 * changed form clean to dirty, it will corrupt the
1786 * sp's access: allow writable in the read-only sp,
1787 * so we should update the spte at this point to get
1788 * a new sp with the correct access.
1790 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
1791 if (child
->role
.access
== direct_access
)
1794 drop_parent_pte(child
, sptep
);
1795 kvm_flush_remote_tlbs(vcpu
->kvm
);
1799 static void mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1803 struct kvm_mmu_page
*child
;
1806 if (is_shadow_present_pte(pte
)) {
1807 if (is_last_spte(pte
, sp
->role
.level
))
1808 drop_spte(kvm
, spte
);
1810 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
1811 drop_parent_pte(child
, spte
);
1813 } else if (is_mmio_spte(pte
))
1814 mmu_spte_clear_no_track(spte
);
1816 if (is_large_pte(pte
))
1820 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
1821 struct kvm_mmu_page
*sp
)
1825 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1826 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
1829 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1831 mmu_page_remove_parent_pte(sp
, parent_pte
);
1834 static void kvm_mmu_reset_last_pte_updated(struct kvm
*kvm
)
1837 struct kvm_vcpu
*vcpu
;
1839 kvm_for_each_vcpu(i
, vcpu
, kvm
)
1840 vcpu
->arch
.last_pte_updated
= NULL
;
1843 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1847 while ((parent_pte
= pte_list_next(&sp
->parent_ptes
, NULL
)))
1848 drop_parent_pte(sp
, parent_pte
);
1851 static int mmu_zap_unsync_children(struct kvm
*kvm
,
1852 struct kvm_mmu_page
*parent
,
1853 struct list_head
*invalid_list
)
1856 struct mmu_page_path parents
;
1857 struct kvm_mmu_pages pages
;
1859 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
1862 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1863 while (mmu_unsync_walk(parent
, &pages
)) {
1864 struct kvm_mmu_page
*sp
;
1866 for_each_sp(pages
, sp
, parents
, i
) {
1867 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
1868 mmu_pages_clear_parents(&parents
);
1871 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1877 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1878 struct list_head
*invalid_list
)
1882 trace_kvm_mmu_prepare_zap_page(sp
);
1883 ++kvm
->stat
.mmu_shadow_zapped
;
1884 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
1885 kvm_mmu_page_unlink_children(kvm
, sp
);
1886 kvm_mmu_unlink_parents(kvm
, sp
);
1887 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
1888 unaccount_shadowed(kvm
, sp
->gfn
);
1890 kvm_unlink_unsync_page(kvm
, sp
);
1891 if (!sp
->root_count
) {
1894 list_move(&sp
->link
, invalid_list
);
1895 kvm_mod_used_mmu_pages(kvm
, -1);
1897 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
1898 kvm_reload_remote_mmus(kvm
);
1901 sp
->role
.invalid
= 1;
1902 kvm_mmu_reset_last_pte_updated(kvm
);
1906 static void kvm_mmu_isolate_pages(struct list_head
*invalid_list
)
1908 struct kvm_mmu_page
*sp
;
1910 list_for_each_entry(sp
, invalid_list
, link
)
1911 kvm_mmu_isolate_page(sp
);
1914 static void free_pages_rcu(struct rcu_head
*head
)
1916 struct kvm_mmu_page
*next
, *sp
;
1918 sp
= container_of(head
, struct kvm_mmu_page
, rcu
);
1920 if (!list_empty(&sp
->link
))
1921 next
= list_first_entry(&sp
->link
,
1922 struct kvm_mmu_page
, link
);
1925 kvm_mmu_free_page(sp
);
1930 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1931 struct list_head
*invalid_list
)
1933 struct kvm_mmu_page
*sp
;
1935 if (list_empty(invalid_list
))
1938 kvm_flush_remote_tlbs(kvm
);
1940 if (atomic_read(&kvm
->arch
.reader_counter
)) {
1941 kvm_mmu_isolate_pages(invalid_list
);
1942 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
1943 list_del_init(invalid_list
);
1945 trace_kvm_mmu_delay_free_pages(sp
);
1946 call_rcu(&sp
->rcu
, free_pages_rcu
);
1951 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
1952 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
1953 kvm_mmu_isolate_page(sp
);
1954 kvm_mmu_free_page(sp
);
1955 } while (!list_empty(invalid_list
));
1960 * Changing the number of mmu pages allocated to the vm
1961 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1963 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
1965 LIST_HEAD(invalid_list
);
1967 * If we set the number of mmu pages to be smaller be than the
1968 * number of actived pages , we must to free some mmu pages before we
1972 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
1973 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
&&
1974 !list_empty(&kvm
->arch
.active_mmu_pages
)) {
1975 struct kvm_mmu_page
*page
;
1977 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
1978 struct kvm_mmu_page
, link
);
1979 kvm_mmu_prepare_zap_page(kvm
, page
, &invalid_list
);
1981 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
1982 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
1985 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
1988 static int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
1990 struct kvm_mmu_page
*sp
;
1991 struct hlist_node
*node
;
1992 LIST_HEAD(invalid_list
);
1995 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
1998 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
1999 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2002 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2004 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2008 static void mmu_unshadow(struct kvm
*kvm
, gfn_t gfn
)
2010 struct kvm_mmu_page
*sp
;
2011 struct hlist_node
*node
;
2012 LIST_HEAD(invalid_list
);
2014 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2015 pgprintk("%s: zap %llx %x\n",
2016 __func__
, gfn
, sp
->role
.word
);
2017 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2019 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2022 static void page_header_update_slot(struct kvm
*kvm
, void *pte
, gfn_t gfn
)
2024 int slot
= memslot_id(kvm
, gfn
);
2025 struct kvm_mmu_page
*sp
= page_header(__pa(pte
));
2027 __set_bit(slot
, sp
->slot_bitmap
);
2031 * The function is based on mtrr_type_lookup() in
2032 * arch/x86/kernel/cpu/mtrr/generic.c
2034 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2039 u8 prev_match
, curr_match
;
2040 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2042 if (!mtrr_state
->enabled
)
2045 /* Make end inclusive end, instead of exclusive */
2048 /* Look in fixed ranges. Just return the type as per start */
2049 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2052 if (start
< 0x80000) {
2054 idx
+= (start
>> 16);
2055 return mtrr_state
->fixed_ranges
[idx
];
2056 } else if (start
< 0xC0000) {
2058 idx
+= ((start
- 0x80000) >> 14);
2059 return mtrr_state
->fixed_ranges
[idx
];
2060 } else if (start
< 0x1000000) {
2062 idx
+= ((start
- 0xC0000) >> 12);
2063 return mtrr_state
->fixed_ranges
[idx
];
2068 * Look in variable ranges
2069 * Look of multiple ranges matching this address and pick type
2070 * as per MTRR precedence
2072 if (!(mtrr_state
->enabled
& 2))
2073 return mtrr_state
->def_type
;
2076 for (i
= 0; i
< num_var_ranges
; ++i
) {
2077 unsigned short start_state
, end_state
;
2079 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2082 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2083 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2084 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2085 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2087 start_state
= ((start
& mask
) == (base
& mask
));
2088 end_state
= ((end
& mask
) == (base
& mask
));
2089 if (start_state
!= end_state
)
2092 if ((start
& mask
) != (base
& mask
))
2095 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2096 if (prev_match
== 0xFF) {
2097 prev_match
= curr_match
;
2101 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2102 curr_match
== MTRR_TYPE_UNCACHABLE
)
2103 return MTRR_TYPE_UNCACHABLE
;
2105 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2106 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2107 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2108 curr_match
== MTRR_TYPE_WRBACK
)) {
2109 prev_match
= MTRR_TYPE_WRTHROUGH
;
2110 curr_match
= MTRR_TYPE_WRTHROUGH
;
2113 if (prev_match
!= curr_match
)
2114 return MTRR_TYPE_UNCACHABLE
;
2117 if (prev_match
!= 0xFF)
2120 return mtrr_state
->def_type
;
2123 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2127 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2128 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2129 if (mtrr
== 0xfe || mtrr
== 0xff)
2130 mtrr
= MTRR_TYPE_WRBACK
;
2133 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2135 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2137 trace_kvm_mmu_unsync_page(sp
);
2138 ++vcpu
->kvm
->stat
.mmu_unsync
;
2141 kvm_mmu_mark_parents_unsync(sp
);
2144 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2146 struct kvm_mmu_page
*s
;
2147 struct hlist_node
*node
;
2149 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2152 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2153 __kvm_unsync_page(vcpu
, s
);
2157 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2160 struct kvm_mmu_page
*s
;
2161 struct hlist_node
*node
;
2162 bool need_unsync
= false;
2164 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2168 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2171 if (!need_unsync
&& !s
->unsync
) {
2178 kvm_unsync_pages(vcpu
, gfn
);
2182 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2183 unsigned pte_access
, int user_fault
,
2184 int write_fault
, int level
,
2185 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2186 bool can_unsync
, bool host_writable
)
2188 u64 spte
, entry
= *sptep
;
2191 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2195 * We don't set the accessed bit, since we sometimes want to see
2196 * whether the guest actually used the pte (in order to detect
2199 spte
= PT_PRESENT_MASK
;
2201 spte
|= shadow_accessed_mask
;
2203 if (pte_access
& ACC_EXEC_MASK
)
2204 spte
|= shadow_x_mask
;
2206 spte
|= shadow_nx_mask
;
2207 if (pte_access
& ACC_USER_MASK
)
2208 spte
|= shadow_user_mask
;
2209 if (level
> PT_PAGE_TABLE_LEVEL
)
2210 spte
|= PT_PAGE_SIZE_MASK
;
2212 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2213 kvm_is_mmio_pfn(pfn
));
2216 spte
|= SPTE_HOST_WRITEABLE
;
2218 pte_access
&= ~ACC_WRITE_MASK
;
2220 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2222 if ((pte_access
& ACC_WRITE_MASK
)
2223 || (!vcpu
->arch
.mmu
.direct_map
&& write_fault
2224 && !is_write_protection(vcpu
) && !user_fault
)) {
2226 if (level
> PT_PAGE_TABLE_LEVEL
&&
2227 has_wrprotected_page(vcpu
->kvm
, gfn
, level
)) {
2229 drop_spte(vcpu
->kvm
, sptep
);
2233 spte
|= PT_WRITABLE_MASK
;
2235 if (!vcpu
->arch
.mmu
.direct_map
2236 && !(pte_access
& ACC_WRITE_MASK
)) {
2237 spte
&= ~PT_USER_MASK
;
2239 * If we converted a user page to a kernel page,
2240 * so that the kernel can write to it when cr0.wp=0,
2241 * then we should prevent the kernel from executing it
2242 * if SMEP is enabled.
2244 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
2245 spte
|= PT64_NX_MASK
;
2249 * Optimization: for pte sync, if spte was writable the hash
2250 * lookup is unnecessary (and expensive). Write protection
2251 * is responsibility of mmu_get_page / kvm_sync_page.
2252 * Same reasoning can be applied to dirty page accounting.
2254 if (!can_unsync
&& is_writable_pte(*sptep
))
2257 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2258 pgprintk("%s: found shadow page for %llx, marking ro\n",
2261 pte_access
&= ~ACC_WRITE_MASK
;
2262 if (is_writable_pte(spte
))
2263 spte
&= ~PT_WRITABLE_MASK
;
2267 if (pte_access
& ACC_WRITE_MASK
)
2268 mark_page_dirty(vcpu
->kvm
, gfn
);
2271 mmu_spte_update(sptep
, spte
);
2273 * If we overwrite a writable spte with a read-only one we
2274 * should flush remote TLBs. Otherwise rmap_write_protect
2275 * will find a read-only spte, even though the writable spte
2276 * might be cached on a CPU's TLB.
2278 if (is_writable_pte(entry
) && !is_writable_pte(*sptep
))
2279 kvm_flush_remote_tlbs(vcpu
->kvm
);
2284 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2285 unsigned pt_access
, unsigned pte_access
,
2286 int user_fault
, int write_fault
,
2287 int *emulate
, int level
, gfn_t gfn
,
2288 pfn_t pfn
, bool speculative
,
2291 int was_rmapped
= 0;
2294 pgprintk("%s: spte %llx access %x write_fault %d"
2295 " user_fault %d gfn %llx\n",
2296 __func__
, *sptep
, pt_access
,
2297 write_fault
, user_fault
, gfn
);
2299 if (is_rmap_spte(*sptep
)) {
2301 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2302 * the parent of the now unreachable PTE.
2304 if (level
> PT_PAGE_TABLE_LEVEL
&&
2305 !is_large_pte(*sptep
)) {
2306 struct kvm_mmu_page
*child
;
2309 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2310 drop_parent_pte(child
, sptep
);
2311 kvm_flush_remote_tlbs(vcpu
->kvm
);
2312 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2313 pgprintk("hfn old %llx new %llx\n",
2314 spte_to_pfn(*sptep
), pfn
);
2315 drop_spte(vcpu
->kvm
, sptep
);
2316 kvm_flush_remote_tlbs(vcpu
->kvm
);
2321 if (set_spte(vcpu
, sptep
, pte_access
, user_fault
, write_fault
,
2322 level
, gfn
, pfn
, speculative
, true,
2326 kvm_mmu_flush_tlb(vcpu
);
2329 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2332 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2333 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2334 is_large_pte(*sptep
)? "2MB" : "4kB",
2335 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2337 if (!was_rmapped
&& is_large_pte(*sptep
))
2338 ++vcpu
->kvm
->stat
.lpages
;
2340 if (is_shadow_present_pte(*sptep
)) {
2341 page_header_update_slot(vcpu
->kvm
, sptep
, gfn
);
2343 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2344 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2345 rmap_recycle(vcpu
, sptep
, gfn
);
2348 kvm_release_pfn_clean(pfn
);
2350 vcpu
->arch
.last_pte_updated
= sptep
;
2351 vcpu
->arch
.last_pte_gfn
= gfn
;
2355 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2359 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2362 struct kvm_memory_slot
*slot
;
2365 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2367 get_page(fault_page
);
2368 return page_to_pfn(fault_page
);
2371 hva
= gfn_to_hva_memslot(slot
, gfn
);
2373 return hva_to_pfn_atomic(vcpu
->kvm
, hva
);
2376 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2377 struct kvm_mmu_page
*sp
,
2378 u64
*start
, u64
*end
)
2380 struct page
*pages
[PTE_PREFETCH_NUM
];
2381 unsigned access
= sp
->role
.access
;
2385 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2386 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2389 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2393 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2394 mmu_set_spte(vcpu
, start
, ACC_ALL
,
2396 sp
->role
.level
, gfn
,
2397 page_to_pfn(pages
[i
]), true, true);
2402 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2403 struct kvm_mmu_page
*sp
, u64
*sptep
)
2405 u64
*spte
, *start
= NULL
;
2408 WARN_ON(!sp
->role
.direct
);
2410 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2413 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2414 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2417 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2425 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2427 struct kvm_mmu_page
*sp
;
2430 * Since it's no accessed bit on EPT, it's no way to
2431 * distinguish between actually accessed translations
2432 * and prefetched, so disable pte prefetch if EPT is
2435 if (!shadow_accessed_mask
)
2438 sp
= page_header(__pa(sptep
));
2439 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2442 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2445 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2446 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2449 struct kvm_shadow_walk_iterator iterator
;
2450 struct kvm_mmu_page
*sp
;
2454 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2455 if (iterator
.level
== level
) {
2456 unsigned pte_access
= ACC_ALL
;
2458 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
, pte_access
,
2460 level
, gfn
, pfn
, prefault
, map_writable
);
2461 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2462 ++vcpu
->stat
.pf_fixed
;
2466 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2467 u64 base_addr
= iterator
.addr
;
2469 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2470 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2471 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2473 1, ACC_ALL
, iterator
.sptep
);
2475 pgprintk("nonpaging_map: ENOMEM\n");
2476 kvm_release_pfn_clean(pfn
);
2480 mmu_spte_set(iterator
.sptep
,
2482 | PT_PRESENT_MASK
| PT_WRITABLE_MASK
2483 | shadow_user_mask
| shadow_x_mask
2484 | shadow_accessed_mask
);
2490 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2494 info
.si_signo
= SIGBUS
;
2496 info
.si_code
= BUS_MCEERR_AR
;
2497 info
.si_addr
= (void __user
*)address
;
2498 info
.si_addr_lsb
= PAGE_SHIFT
;
2500 send_sig_info(SIGBUS
, &info
, tsk
);
2503 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2505 kvm_release_pfn_clean(pfn
);
2506 if (is_hwpoison_pfn(pfn
)) {
2507 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2514 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2515 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2519 int level
= *levelp
;
2522 * Check if it's a transparent hugepage. If this would be an
2523 * hugetlbfs page, level wouldn't be set to
2524 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2527 if (!is_error_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2528 level
== PT_PAGE_TABLE_LEVEL
&&
2529 PageTransCompound(pfn_to_page(pfn
)) &&
2530 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2533 * mmu_notifier_retry was successful and we hold the
2534 * mmu_lock here, so the pmd can't become splitting
2535 * from under us, and in turn
2536 * __split_huge_page_refcount() can't run from under
2537 * us and we can safely transfer the refcount from
2538 * PG_tail to PG_head as we switch the pfn to tail to
2541 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2542 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2543 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2547 kvm_release_pfn_clean(pfn
);
2549 if (!get_page_unless_zero(pfn_to_page(pfn
)))
2556 static bool mmu_invalid_pfn(pfn_t pfn
)
2558 return unlikely(is_invalid_pfn(pfn
));
2561 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2562 pfn_t pfn
, unsigned access
, int *ret_val
)
2566 /* The pfn is invalid, report the error! */
2567 if (unlikely(is_invalid_pfn(pfn
))) {
2568 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2572 if (unlikely(is_noslot_pfn(pfn
)))
2573 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2580 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2581 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2583 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, int write
, gfn_t gfn
,
2590 unsigned long mmu_seq
;
2593 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2594 if (likely(!force_pt_level
)) {
2595 level
= mapping_level(vcpu
, gfn
);
2597 * This path builds a PAE pagetable - so we can map
2598 * 2mb pages at maximum. Therefore check if the level
2599 * is larger than that.
2601 if (level
> PT_DIRECTORY_LEVEL
)
2602 level
= PT_DIRECTORY_LEVEL
;
2604 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2606 level
= PT_PAGE_TABLE_LEVEL
;
2608 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2611 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2614 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2617 spin_lock(&vcpu
->kvm
->mmu_lock
);
2618 if (mmu_notifier_retry(vcpu
, mmu_seq
))
2620 kvm_mmu_free_some_pages(vcpu
);
2621 if (likely(!force_pt_level
))
2622 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2623 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2625 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2631 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2632 kvm_release_pfn_clean(pfn
);
2637 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2640 struct kvm_mmu_page
*sp
;
2641 LIST_HEAD(invalid_list
);
2643 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2645 spin_lock(&vcpu
->kvm
->mmu_lock
);
2646 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2647 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2648 vcpu
->arch
.mmu
.direct_map
)) {
2649 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2651 sp
= page_header(root
);
2653 if (!sp
->root_count
&& sp
->role
.invalid
) {
2654 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2655 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2657 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2658 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2661 for (i
= 0; i
< 4; ++i
) {
2662 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2665 root
&= PT64_BASE_ADDR_MASK
;
2666 sp
= page_header(root
);
2668 if (!sp
->root_count
&& sp
->role
.invalid
)
2669 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2672 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2674 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2675 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2676 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2679 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2683 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2684 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2691 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2693 struct kvm_mmu_page
*sp
;
2696 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2697 spin_lock(&vcpu
->kvm
->mmu_lock
);
2698 kvm_mmu_free_some_pages(vcpu
);
2699 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2702 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2703 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2704 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2705 for (i
= 0; i
< 4; ++i
) {
2706 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2708 ASSERT(!VALID_PAGE(root
));
2709 spin_lock(&vcpu
->kvm
->mmu_lock
);
2710 kvm_mmu_free_some_pages(vcpu
);
2711 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2713 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2715 root
= __pa(sp
->spt
);
2717 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2718 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2720 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2727 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2729 struct kvm_mmu_page
*sp
;
2734 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2736 if (mmu_check_root(vcpu
, root_gfn
))
2740 * Do we shadow a long mode page table? If so we need to
2741 * write-protect the guests page table root.
2743 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2744 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2746 ASSERT(!VALID_PAGE(root
));
2748 spin_lock(&vcpu
->kvm
->mmu_lock
);
2749 kvm_mmu_free_some_pages(vcpu
);
2750 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
2752 root
= __pa(sp
->spt
);
2754 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2755 vcpu
->arch
.mmu
.root_hpa
= root
;
2760 * We shadow a 32 bit page table. This may be a legacy 2-level
2761 * or a PAE 3-level page table. In either case we need to be aware that
2762 * the shadow page table may be a PAE or a long mode page table.
2764 pm_mask
= PT_PRESENT_MASK
;
2765 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
2766 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
2768 for (i
= 0; i
< 4; ++i
) {
2769 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2771 ASSERT(!VALID_PAGE(root
));
2772 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
2773 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
2774 if (!is_present_gpte(pdptr
)) {
2775 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
2778 root_gfn
= pdptr
>> PAGE_SHIFT
;
2779 if (mmu_check_root(vcpu
, root_gfn
))
2782 spin_lock(&vcpu
->kvm
->mmu_lock
);
2783 kvm_mmu_free_some_pages(vcpu
);
2784 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
2787 root
= __pa(sp
->spt
);
2789 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2791 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
2793 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2796 * If we shadow a 32 bit page table with a long mode page
2797 * table we enter this path.
2799 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2800 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
2802 * The additional page necessary for this is only
2803 * allocated on demand.
2808 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
2809 if (lm_root
== NULL
)
2812 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
2814 vcpu
->arch
.mmu
.lm_root
= lm_root
;
2817 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
2823 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
2825 if (vcpu
->arch
.mmu
.direct_map
)
2826 return mmu_alloc_direct_roots(vcpu
);
2828 return mmu_alloc_shadow_roots(vcpu
);
2831 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
2834 struct kvm_mmu_page
*sp
;
2836 if (vcpu
->arch
.mmu
.direct_map
)
2839 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2842 vcpu_clear_mmio_info(vcpu
, ~0ul);
2843 trace_kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
2844 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2845 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2846 sp
= page_header(root
);
2847 mmu_sync_children(vcpu
, sp
);
2848 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
2851 for (i
= 0; i
< 4; ++i
) {
2852 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2854 if (root
&& VALID_PAGE(root
)) {
2855 root
&= PT64_BASE_ADDR_MASK
;
2856 sp
= page_header(root
);
2857 mmu_sync_children(vcpu
, sp
);
2860 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
2863 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
2865 spin_lock(&vcpu
->kvm
->mmu_lock
);
2866 mmu_sync_roots(vcpu
);
2867 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2870 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
2871 u32 access
, struct x86_exception
*exception
)
2874 exception
->error_code
= 0;
2878 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
2880 struct x86_exception
*exception
)
2883 exception
->error_code
= 0;
2884 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
2887 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
2890 return vcpu_match_mmio_gpa(vcpu
, addr
);
2892 return vcpu_match_mmio_gva(vcpu
, addr
);
2897 * On direct hosts, the last spte is only allows two states
2898 * for mmio page fault:
2899 * - It is the mmio spte
2900 * - It is zapped or it is being zapped.
2902 * This function completely checks the spte when the last spte
2903 * is not the mmio spte.
2905 static bool check_direct_spte_mmio_pf(u64 spte
)
2907 return __check_direct_spte_mmio_pf(spte
);
2910 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
2912 struct kvm_shadow_walk_iterator iterator
;
2915 walk_shadow_page_lockless_begin(vcpu
);
2916 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
2917 if (!is_shadow_present_pte(spte
))
2919 walk_shadow_page_lockless_end(vcpu
);
2925 * If it is a real mmio page fault, return 1 and emulat the instruction
2926 * directly, return 0 to let CPU fault again on the address, -1 is
2927 * returned if bug is detected.
2929 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
2933 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
2936 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
2938 if (is_mmio_spte(spte
)) {
2939 gfn_t gfn
= get_mmio_spte_gfn(spte
);
2940 unsigned access
= get_mmio_spte_access(spte
);
2945 trace_handle_mmio_page_fault(addr
, gfn
, access
);
2946 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
2951 * It's ok if the gva is remapped by other cpus on shadow guest,
2952 * it's a BUG if the gfn is not a mmio page.
2954 if (direct
&& !check_direct_spte_mmio_pf(spte
))
2958 * If the page table is zapped by other cpus, let CPU fault again on
2963 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
2965 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
2966 u32 error_code
, bool direct
)
2970 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
2975 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
2976 u32 error_code
, bool prefault
)
2981 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
2983 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2984 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
2986 r
= mmu_topup_memory_caches(vcpu
);
2991 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
2993 gfn
= gva
>> PAGE_SHIFT
;
2995 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
2996 error_code
& PFERR_WRITE_MASK
, gfn
, prefault
);
2999 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3001 struct kvm_arch_async_pf arch
;
3003 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3005 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3006 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3008 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3011 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3013 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3014 kvm_event_needs_reinjection(vcpu
)))
3017 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3020 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3021 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3025 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3028 return false; /* *pfn has correct page already */
3030 put_page(pfn_to_page(*pfn
));
3032 if (!prefault
&& can_do_async_pf(vcpu
)) {
3033 trace_kvm_try_async_get_page(gva
, gfn
);
3034 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3035 trace_kvm_async_pf_doublefault(gva
, gfn
);
3036 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3038 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3042 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3047 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3054 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3055 unsigned long mmu_seq
;
3056 int write
= error_code
& PFERR_WRITE_MASK
;
3060 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3062 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3063 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3065 r
= mmu_topup_memory_caches(vcpu
);
3069 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3070 if (likely(!force_pt_level
)) {
3071 level
= mapping_level(vcpu
, gfn
);
3072 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3074 level
= PT_PAGE_TABLE_LEVEL
;
3076 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3079 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3082 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3085 spin_lock(&vcpu
->kvm
->mmu_lock
);
3086 if (mmu_notifier_retry(vcpu
, mmu_seq
))
3088 kvm_mmu_free_some_pages(vcpu
);
3089 if (likely(!force_pt_level
))
3090 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3091 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3092 level
, gfn
, pfn
, prefault
);
3093 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3098 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3099 kvm_release_pfn_clean(pfn
);
3103 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3105 mmu_free_roots(vcpu
);
3108 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3109 struct kvm_mmu
*context
)
3111 context
->new_cr3
= nonpaging_new_cr3
;
3112 context
->page_fault
= nonpaging_page_fault
;
3113 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3114 context
->free
= nonpaging_free
;
3115 context
->sync_page
= nonpaging_sync_page
;
3116 context
->invlpg
= nonpaging_invlpg
;
3117 context
->update_pte
= nonpaging_update_pte
;
3118 context
->root_level
= 0;
3119 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3120 context
->root_hpa
= INVALID_PAGE
;
3121 context
->direct_map
= true;
3122 context
->nx
= false;
3126 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3128 ++vcpu
->stat
.tlb_flush
;
3129 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3132 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3134 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3135 mmu_free_roots(vcpu
);
3138 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3140 return kvm_read_cr3(vcpu
);
3143 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3144 struct x86_exception
*fault
)
3146 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3149 static void paging_free(struct kvm_vcpu
*vcpu
)
3151 nonpaging_free(vcpu
);
3154 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3158 bit7
= (gpte
>> 7) & 1;
3159 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
3162 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3165 if (unlikely(is_mmio_spte(*sptep
))) {
3166 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3167 mmu_spte_clear_no_track(sptep
);
3172 mark_mmio_spte(sptep
, gfn
, access
);
3180 #include "paging_tmpl.h"
3184 #include "paging_tmpl.h"
3187 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3188 struct kvm_mmu
*context
,
3191 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3192 u64 exb_bit_rsvd
= 0;
3195 exb_bit_rsvd
= rsvd_bits(63, 63);
3197 case PT32_ROOT_LEVEL
:
3198 /* no rsvd bits for 2 level 4K page table entries */
3199 context
->rsvd_bits_mask
[0][1] = 0;
3200 context
->rsvd_bits_mask
[0][0] = 0;
3201 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3203 if (!is_pse(vcpu
)) {
3204 context
->rsvd_bits_mask
[1][1] = 0;
3208 if (is_cpuid_PSE36())
3209 /* 36bits PSE 4MB page */
3210 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3212 /* 32 bits PSE 4MB page */
3213 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3215 case PT32E_ROOT_LEVEL
:
3216 context
->rsvd_bits_mask
[0][2] =
3217 rsvd_bits(maxphyaddr
, 63) |
3218 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3219 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3220 rsvd_bits(maxphyaddr
, 62); /* PDE */
3221 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3222 rsvd_bits(maxphyaddr
, 62); /* PTE */
3223 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3224 rsvd_bits(maxphyaddr
, 62) |
3225 rsvd_bits(13, 20); /* large page */
3226 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3228 case PT64_ROOT_LEVEL
:
3229 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3230 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3231 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3232 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3233 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3234 rsvd_bits(maxphyaddr
, 51);
3235 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3236 rsvd_bits(maxphyaddr
, 51);
3237 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3238 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3239 rsvd_bits(maxphyaddr
, 51) |
3241 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3242 rsvd_bits(maxphyaddr
, 51) |
3243 rsvd_bits(13, 20); /* large page */
3244 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3249 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3250 struct kvm_mmu
*context
,
3253 context
->nx
= is_nx(vcpu
);
3255 reset_rsvds_bits_mask(vcpu
, context
, level
);
3257 ASSERT(is_pae(vcpu
));
3258 context
->new_cr3
= paging_new_cr3
;
3259 context
->page_fault
= paging64_page_fault
;
3260 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3261 context
->sync_page
= paging64_sync_page
;
3262 context
->invlpg
= paging64_invlpg
;
3263 context
->update_pte
= paging64_update_pte
;
3264 context
->free
= paging_free
;
3265 context
->root_level
= level
;
3266 context
->shadow_root_level
= level
;
3267 context
->root_hpa
= INVALID_PAGE
;
3268 context
->direct_map
= false;
3272 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3273 struct kvm_mmu
*context
)
3275 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3278 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3279 struct kvm_mmu
*context
)
3281 context
->nx
= false;
3283 reset_rsvds_bits_mask(vcpu
, context
, PT32_ROOT_LEVEL
);
3285 context
->new_cr3
= paging_new_cr3
;
3286 context
->page_fault
= paging32_page_fault
;
3287 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3288 context
->free
= paging_free
;
3289 context
->sync_page
= paging32_sync_page
;
3290 context
->invlpg
= paging32_invlpg
;
3291 context
->update_pte
= paging32_update_pte
;
3292 context
->root_level
= PT32_ROOT_LEVEL
;
3293 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3294 context
->root_hpa
= INVALID_PAGE
;
3295 context
->direct_map
= false;
3299 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3300 struct kvm_mmu
*context
)
3302 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3305 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3307 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3309 context
->base_role
.word
= 0;
3310 context
->new_cr3
= nonpaging_new_cr3
;
3311 context
->page_fault
= tdp_page_fault
;
3312 context
->free
= nonpaging_free
;
3313 context
->sync_page
= nonpaging_sync_page
;
3314 context
->invlpg
= nonpaging_invlpg
;
3315 context
->update_pte
= nonpaging_update_pte
;
3316 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3317 context
->root_hpa
= INVALID_PAGE
;
3318 context
->direct_map
= true;
3319 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3320 context
->get_cr3
= get_cr3
;
3321 context
->get_pdptr
= kvm_pdptr_read
;
3322 context
->inject_page_fault
= kvm_inject_page_fault
;
3323 context
->nx
= is_nx(vcpu
);
3325 if (!is_paging(vcpu
)) {
3326 context
->nx
= false;
3327 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3328 context
->root_level
= 0;
3329 } else if (is_long_mode(vcpu
)) {
3330 context
->nx
= is_nx(vcpu
);
3331 reset_rsvds_bits_mask(vcpu
, context
, PT64_ROOT_LEVEL
);
3332 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3333 context
->root_level
= PT64_ROOT_LEVEL
;
3334 } else if (is_pae(vcpu
)) {
3335 context
->nx
= is_nx(vcpu
);
3336 reset_rsvds_bits_mask(vcpu
, context
, PT32E_ROOT_LEVEL
);
3337 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3338 context
->root_level
= PT32E_ROOT_LEVEL
;
3340 context
->nx
= false;
3341 reset_rsvds_bits_mask(vcpu
, context
, PT32_ROOT_LEVEL
);
3342 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3343 context
->root_level
= PT32_ROOT_LEVEL
;
3349 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3352 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3354 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3356 if (!is_paging(vcpu
))
3357 r
= nonpaging_init_context(vcpu
, context
);
3358 else if (is_long_mode(vcpu
))
3359 r
= paging64_init_context(vcpu
, context
);
3360 else if (is_pae(vcpu
))
3361 r
= paging32E_init_context(vcpu
, context
);
3363 r
= paging32_init_context(vcpu
, context
);
3365 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3366 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3367 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3368 = smep
&& !is_write_protection(vcpu
);
3372 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3374 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3376 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3378 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3379 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3380 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3381 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3386 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3388 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3390 g_context
->get_cr3
= get_cr3
;
3391 g_context
->get_pdptr
= kvm_pdptr_read
;
3392 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3395 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3396 * translation of l2_gpa to l1_gpa addresses is done using the
3397 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3398 * functions between mmu and nested_mmu are swapped.
3400 if (!is_paging(vcpu
)) {
3401 g_context
->nx
= false;
3402 g_context
->root_level
= 0;
3403 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3404 } else if (is_long_mode(vcpu
)) {
3405 g_context
->nx
= is_nx(vcpu
);
3406 reset_rsvds_bits_mask(vcpu
, g_context
, PT64_ROOT_LEVEL
);
3407 g_context
->root_level
= PT64_ROOT_LEVEL
;
3408 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3409 } else if (is_pae(vcpu
)) {
3410 g_context
->nx
= is_nx(vcpu
);
3411 reset_rsvds_bits_mask(vcpu
, g_context
, PT32E_ROOT_LEVEL
);
3412 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3413 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3415 g_context
->nx
= false;
3416 reset_rsvds_bits_mask(vcpu
, g_context
, PT32_ROOT_LEVEL
);
3417 g_context
->root_level
= PT32_ROOT_LEVEL
;
3418 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3424 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3426 if (mmu_is_nested(vcpu
))
3427 return init_kvm_nested_mmu(vcpu
);
3428 else if (tdp_enabled
)
3429 return init_kvm_tdp_mmu(vcpu
);
3431 return init_kvm_softmmu(vcpu
);
3434 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3437 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3438 /* mmu.free() should set root_hpa = INVALID_PAGE */
3439 vcpu
->arch
.mmu
.free(vcpu
);
3442 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3444 destroy_kvm_mmu(vcpu
);
3445 return init_kvm_mmu(vcpu
);
3447 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3449 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3453 r
= mmu_topup_memory_caches(vcpu
);
3456 r
= mmu_alloc_roots(vcpu
);
3457 spin_lock(&vcpu
->kvm
->mmu_lock
);
3458 mmu_sync_roots(vcpu
);
3459 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3462 /* set_cr3() should ensure TLB has been flushed */
3463 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3467 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3469 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3471 mmu_free_roots(vcpu
);
3473 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3475 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3476 struct kvm_mmu_page
*sp
, u64
*spte
,
3479 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3480 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3484 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3485 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3488 static bool need_remote_flush(u64 old
, u64
new)
3490 if (!is_shadow_present_pte(old
))
3492 if (!is_shadow_present_pte(new))
3494 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3496 old
^= PT64_NX_MASK
;
3497 new ^= PT64_NX_MASK
;
3498 return (old
& ~new & PT64_PERM_MASK
) != 0;
3501 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3502 bool remote_flush
, bool local_flush
)
3508 kvm_flush_remote_tlbs(vcpu
->kvm
);
3509 else if (local_flush
)
3510 kvm_mmu_flush_tlb(vcpu
);
3513 static bool last_updated_pte_accessed(struct kvm_vcpu
*vcpu
)
3515 u64
*spte
= vcpu
->arch
.last_pte_updated
;
3517 return !!(spte
&& (*spte
& shadow_accessed_mask
));
3520 static void kvm_mmu_access_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
3522 u64
*spte
= vcpu
->arch
.last_pte_updated
;
3525 && vcpu
->arch
.last_pte_gfn
== gfn
3526 && shadow_accessed_mask
3527 && !(*spte
& shadow_accessed_mask
)
3528 && is_shadow_present_pte(*spte
))
3529 set_bit(PT_ACCESSED_SHIFT
, (unsigned long *)spte
);
3532 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3533 const u8
*new, int bytes
,
3534 bool guest_initiated
)
3536 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3537 union kvm_mmu_page_role mask
= { .word
= 0 };
3538 struct kvm_mmu_page
*sp
;
3539 struct hlist_node
*node
;
3540 LIST_HEAD(invalid_list
);
3541 u64 entry
, gentry
, *spte
;
3542 unsigned pte_size
, page_offset
, misaligned
, quadrant
, offset
;
3543 int level
, npte
, invlpg_counter
, r
, flooded
= 0;
3544 bool remote_flush
, local_flush
, zap_page
;
3547 * If we don't have indirect shadow pages, it means no page is
3548 * write-protected, so we can exit simply.
3550 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3553 zap_page
= remote_flush
= local_flush
= false;
3554 offset
= offset_in_page(gpa
);
3556 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3558 invlpg_counter
= atomic_read(&vcpu
->kvm
->arch
.invlpg_counter
);
3561 * Assume that the pte write on a page table of the same type
3562 * as the current vcpu paging mode since we update the sptes only
3563 * when they have the same mode.
3565 if ((is_pae(vcpu
) && bytes
== 4) || !new) {
3566 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3571 r
= kvm_read_guest(vcpu
->kvm
, gpa
, &gentry
, min(bytes
, 8));
3574 new = (const u8
*)&gentry
;
3579 gentry
= *(const u32
*)new;
3582 gentry
= *(const u64
*)new;
3589 spin_lock(&vcpu
->kvm
->mmu_lock
);
3590 if (atomic_read(&vcpu
->kvm
->arch
.invlpg_counter
) != invlpg_counter
)
3592 kvm_mmu_free_some_pages(vcpu
);
3593 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3594 trace_kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3595 if (guest_initiated
) {
3596 kvm_mmu_access_page(vcpu
, gfn
);
3597 if (gfn
== vcpu
->arch
.last_pt_write_gfn
3598 && !last_updated_pte_accessed(vcpu
)) {
3599 ++vcpu
->arch
.last_pt_write_count
;
3600 if (vcpu
->arch
.last_pt_write_count
>= 3)
3603 vcpu
->arch
.last_pt_write_gfn
= gfn
;
3604 vcpu
->arch
.last_pt_write_count
= 1;
3605 vcpu
->arch
.last_pte_updated
= NULL
;
3609 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3610 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
, node
) {
3611 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3612 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3613 misaligned
|= bytes
< 4;
3614 if (misaligned
|| flooded
) {
3616 * Misaligned accesses are too much trouble to fix
3617 * up; also, they usually indicate a page is not used
3620 * If we're seeing too many writes to a page,
3621 * it may no longer be a page table, or we may be
3622 * forking, in which case it is better to unmap the
3625 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3626 gpa
, bytes
, sp
->role
.word
);
3627 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3629 ++vcpu
->kvm
->stat
.mmu_flooded
;
3632 page_offset
= offset
;
3633 level
= sp
->role
.level
;
3635 if (!sp
->role
.cr4_pae
) {
3636 page_offset
<<= 1; /* 32->64 */
3638 * A 32-bit pde maps 4MB while the shadow pdes map
3639 * only 2MB. So we need to double the offset again
3640 * and zap two pdes instead of one.
3642 if (level
== PT32_ROOT_LEVEL
) {
3643 page_offset
&= ~7; /* kill rounding error */
3647 quadrant
= page_offset
>> PAGE_SHIFT
;
3648 page_offset
&= ~PAGE_MASK
;
3649 if (quadrant
!= sp
->role
.quadrant
)
3653 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3656 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
3658 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
3660 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
3661 if (!remote_flush
&& need_remote_flush(entry
, *spte
))
3662 remote_flush
= true;
3666 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
3667 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3668 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
3669 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3672 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
3677 if (vcpu
->arch
.mmu
.direct_map
)
3680 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
3682 spin_lock(&vcpu
->kvm
->mmu_lock
);
3683 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
3684 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3687 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
3689 void __kvm_mmu_free_some_pages(struct kvm_vcpu
*vcpu
)
3691 LIST_HEAD(invalid_list
);
3693 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
&&
3694 !list_empty(&vcpu
->kvm
->arch
.active_mmu_pages
)) {
3695 struct kvm_mmu_page
*sp
;
3697 sp
= container_of(vcpu
->kvm
->arch
.active_mmu_pages
.prev
,
3698 struct kvm_mmu_page
, link
);
3699 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3700 ++vcpu
->kvm
->stat
.mmu_recycled
;
3702 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3705 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
3706 void *insn
, int insn_len
)
3709 enum emulation_result er
;
3711 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
3720 r
= mmu_topup_memory_caches(vcpu
);
3724 er
= x86_emulate_instruction(vcpu
, cr2
, 0, insn
, insn_len
);
3729 case EMULATE_DO_MMIO
:
3730 ++vcpu
->stat
.mmio_exits
;
3740 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
3742 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
3744 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
3745 kvm_mmu_flush_tlb(vcpu
);
3746 ++vcpu
->stat
.invlpg
;
3748 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
3750 void kvm_enable_tdp(void)
3754 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
3756 void kvm_disable_tdp(void)
3758 tdp_enabled
= false;
3760 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
3762 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
3764 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
3765 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
3766 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
3769 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
3777 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3778 * Therefore we need to allocate shadow page tables in the first
3779 * 4GB of memory, which happens to fit the DMA32 zone.
3781 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
3785 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
3786 for (i
= 0; i
< 4; ++i
)
3787 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3792 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
3795 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3797 return alloc_mmu_pages(vcpu
);
3800 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
3803 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3805 return init_kvm_mmu(vcpu
);
3808 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
3810 struct kvm_mmu_page
*sp
;
3812 list_for_each_entry(sp
, &kvm
->arch
.active_mmu_pages
, link
) {
3816 if (!test_bit(slot
, sp
->slot_bitmap
))
3820 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
) {
3821 if (!is_shadow_present_pte(pt
[i
]) ||
3822 !is_last_spte(pt
[i
], sp
->role
.level
))
3825 if (is_large_pte(pt
[i
])) {
3826 drop_spte(kvm
, &pt
[i
]);
3832 if (is_writable_pte(pt
[i
]))
3833 mmu_spte_update(&pt
[i
],
3834 pt
[i
] & ~PT_WRITABLE_MASK
);
3837 kvm_flush_remote_tlbs(kvm
);
3840 void kvm_mmu_zap_all(struct kvm
*kvm
)
3842 struct kvm_mmu_page
*sp
, *node
;
3843 LIST_HEAD(invalid_list
);
3845 spin_lock(&kvm
->mmu_lock
);
3847 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
)
3848 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
3851 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3852 spin_unlock(&kvm
->mmu_lock
);
3855 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm
*kvm
,
3856 struct list_head
*invalid_list
)
3858 struct kvm_mmu_page
*page
;
3860 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
3861 struct kvm_mmu_page
, link
);
3862 return kvm_mmu_prepare_zap_page(kvm
, page
, invalid_list
);
3865 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
3868 struct kvm
*kvm_freed
= NULL
;
3869 int nr_to_scan
= sc
->nr_to_scan
;
3871 if (nr_to_scan
== 0)
3874 raw_spin_lock(&kvm_lock
);
3876 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
3877 int idx
, freed_pages
;
3878 LIST_HEAD(invalid_list
);
3880 idx
= srcu_read_lock(&kvm
->srcu
);
3881 spin_lock(&kvm
->mmu_lock
);
3882 if (!kvm_freed
&& nr_to_scan
> 0 &&
3883 kvm
->arch
.n_used_mmu_pages
> 0) {
3884 freed_pages
= kvm_mmu_remove_some_alloc_mmu_pages(kvm
,
3890 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3891 spin_unlock(&kvm
->mmu_lock
);
3892 srcu_read_unlock(&kvm
->srcu
, idx
);
3895 list_move_tail(&kvm_freed
->vm_list
, &vm_list
);
3897 raw_spin_unlock(&kvm_lock
);
3900 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
3903 static struct shrinker mmu_shrinker
= {
3904 .shrink
= mmu_shrink
,
3905 .seeks
= DEFAULT_SEEKS
* 10,
3908 static void mmu_destroy_caches(void)
3910 if (pte_list_desc_cache
)
3911 kmem_cache_destroy(pte_list_desc_cache
);
3912 if (mmu_page_header_cache
)
3913 kmem_cache_destroy(mmu_page_header_cache
);
3916 int kvm_mmu_module_init(void)
3918 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
3919 sizeof(struct pte_list_desc
),
3921 if (!pte_list_desc_cache
)
3924 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
3925 sizeof(struct kvm_mmu_page
),
3927 if (!mmu_page_header_cache
)
3930 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
3933 register_shrinker(&mmu_shrinker
);
3938 mmu_destroy_caches();
3943 * Caculate mmu pages needed for kvm.
3945 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
3948 unsigned int nr_mmu_pages
;
3949 unsigned int nr_pages
= 0;
3950 struct kvm_memslots
*slots
;
3952 slots
= kvm_memslots(kvm
);
3954 for (i
= 0; i
< slots
->nmemslots
; i
++)
3955 nr_pages
+= slots
->memslots
[i
].npages
;
3957 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
3958 nr_mmu_pages
= max(nr_mmu_pages
,
3959 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
3961 return nr_mmu_pages
;
3964 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer
*buffer
,
3967 if (len
> buffer
->len
)
3972 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer
*buffer
,
3977 ret
= pv_mmu_peek_buffer(buffer
, len
);
3982 buffer
->processed
+= len
;
3986 static int kvm_pv_mmu_write(struct kvm_vcpu
*vcpu
,
3987 gpa_t addr
, gpa_t value
)
3992 if (!is_long_mode(vcpu
) && !is_pae(vcpu
))
3995 r
= mmu_topup_memory_caches(vcpu
);
3999 if (!emulator_write_phys(vcpu
, addr
, &value
, bytes
))
4005 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
4007 (void)kvm_set_cr3(vcpu
, kvm_read_cr3(vcpu
));
4011 static int kvm_pv_mmu_release_pt(struct kvm_vcpu
*vcpu
, gpa_t addr
)
4013 spin_lock(&vcpu
->kvm
->mmu_lock
);
4014 mmu_unshadow(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
4015 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4019 static int kvm_pv_mmu_op_one(struct kvm_vcpu
*vcpu
,
4020 struct kvm_pv_mmu_op_buffer
*buffer
)
4022 struct kvm_mmu_op_header
*header
;
4024 header
= pv_mmu_peek_buffer(buffer
, sizeof *header
);
4027 switch (header
->op
) {
4028 case KVM_MMU_OP_WRITE_PTE
: {
4029 struct kvm_mmu_op_write_pte
*wpte
;
4031 wpte
= pv_mmu_read_buffer(buffer
, sizeof *wpte
);
4034 return kvm_pv_mmu_write(vcpu
, wpte
->pte_phys
,
4037 case KVM_MMU_OP_FLUSH_TLB
: {
4038 struct kvm_mmu_op_flush_tlb
*ftlb
;
4040 ftlb
= pv_mmu_read_buffer(buffer
, sizeof *ftlb
);
4043 return kvm_pv_mmu_flush_tlb(vcpu
);
4045 case KVM_MMU_OP_RELEASE_PT
: {
4046 struct kvm_mmu_op_release_pt
*rpt
;
4048 rpt
= pv_mmu_read_buffer(buffer
, sizeof *rpt
);
4051 return kvm_pv_mmu_release_pt(vcpu
, rpt
->pt_phys
);
4057 int kvm_pv_mmu_op(struct kvm_vcpu
*vcpu
, unsigned long bytes
,
4058 gpa_t addr
, unsigned long *ret
)
4061 struct kvm_pv_mmu_op_buffer
*buffer
= &vcpu
->arch
.mmu_op_buffer
;
4063 buffer
->ptr
= buffer
->buf
;
4064 buffer
->len
= min_t(unsigned long, bytes
, sizeof buffer
->buf
);
4065 buffer
->processed
= 0;
4067 r
= kvm_read_guest(vcpu
->kvm
, addr
, buffer
->buf
, buffer
->len
);
4071 while (buffer
->len
) {
4072 r
= kvm_pv_mmu_op_one(vcpu
, buffer
);
4081 *ret
= buffer
->processed
;
4085 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4087 struct kvm_shadow_walk_iterator iterator
;
4091 walk_shadow_page_lockless_begin(vcpu
);
4092 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4093 sptes
[iterator
.level
-1] = spte
;
4095 if (!is_shadow_present_pte(spte
))
4098 walk_shadow_page_lockless_end(vcpu
);
4102 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4104 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4108 destroy_kvm_mmu(vcpu
);
4109 free_mmu_pages(vcpu
);
4110 mmu_free_memory_caches(vcpu
);
4113 #ifdef CONFIG_KVM_MMU_AUDIT
4114 #include "mmu_audit.c"
4116 static void mmu_audit_disable(void) { }
4119 void kvm_mmu_module_exit(void)
4121 mmu_destroy_caches();
4122 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4123 unregister_shrinker(&mmu_shrinker
);
4124 mmu_audit_disable();